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init.c
资源名称：SMDK2440.rar　[点击查看]
上传用户：qiulin1960
上传日期：2013-10-16
资源大小：2844k
文件大小：15k
源码类别：

Windows CE

开发平台：

Windows_Unix

init.c：源码内容
  1. /*++
  2. THIS CODE AND INFORMATION IS PROVIDED "AS IS" WITHOUT WARRANTY OF
  3. ANY KIND, EITHER EXPRESSED OR IMPLIED, INCLUDING BUT NOT LIMITED TO
  4. THE IMPLIED WARRANTIES OF MERCHANTABILITY AND/OR FITNESS FOR A
  5. PARTICULAR PURPOSE.
  6. Copyright (c) 2002. Samsung Electronics, co. ltd  All rights reserved.
  8. [Updates]
  10. 2003.03.14 PCMCIA Wakeup fixed. jylee
  12. --*/
  14. #include <windows.h>
  15. #include <types.h>
  16. #include <cardserv.h>
  17. #include <sockserv.h>
  18. #include <sockpd.h>
  19. #include <ceddk.h>
  20. //#include <pc.h>
  21. #include <nkintr.h>
  22. #include <oalintr.h>
  23. #include <S2440.h> 
  24. #include <pd6710.h>
  25. #include <drv_glob.h>
  27. extern VOID InitSocketNoCard(UINT uSocket);
  29. //void PD_DataBackup();
  30. void PD_DataRestore();
  32. DWORD gIntrPcmciaState = SYSINTR_PCMCIA_STATE;
  33. DWORD gIntrPcmciaLevel = SYSINTR_PCMCIA_LEVEL;
  34. DWORD g_Irq = 3;        // fixed by S3C2440 development platform
  36. volatile PUCHAR g_PCICIndex;
  37. volatile PUCHAR g_PCICData;
  38. CRITICAL_SECTION g_PCIC_Crit;
  40. volatile IOPreg *v_pIOPRegs;
  41. volatile MEMreg *v_pMEMRegs;
  42. volatile PUCHAR *v_pPCMCIAPort;  
  44. // be written by fwood for wake-up
  45. //volatile IOPreg IOPRegs_bak;
  46. //volatile MEMreg MEMRegs_bak;
  49. // when power up, restore datas
  50. // by shlim
  51. void PD_DataRestore()
  52. {
  53. UINT8 tmp;
  55. // Register Restore for wake-up
  57. // Initialize S3C2440 for PD6710           
  58. // EINT3(GPF3) is enabled.
  59. v_pIOPRegs->rGPFCON = (v_pIOPRegs->rGPFCON & ~(0x3<<6)) | (0x2<<6); 
  60. // EINT3 is PULLUP enabled.
  61. v_pIOPRegs->rGPFUP = (v_pIOPRegs->rGPFUP & ~(0x1<<3));              
  63. // EINT8(GPG0) is enabled.
  64. v_pIOPRegs->rGPGCON = (v_pIOPRegs->rGPGCON & ~(0x3<<0)) | (0x2<<0); 
  65. // EINT8 is *not* PULLUP enabled.
  66. //v_pIOPRegs->rGPGUP = (v_pIOPRegs->rGPGUP | (0x1<<0));
  67. // jylee
  68. v_pIOPRegs->rGPGUP = (v_pIOPRegs->rGPGUP & ~(0x1<<0)); // pullup enabled
  71. // nGCS2=nUB/nLB(nSBHE),nWAIT,16-bit
  72. v_pMEMRegs->rBWSCON = (v_pMEMRegs->rBWSCON & ~(0xf<<8)) | (0xd<<8); 
  74. // BANK2 access timing
  75. v_pMEMRegs->rBANKCON2 = ((B6710_Tacs<<13)+(B6710_Tcos<<11)+(B6710_Tacc<<8)+(B6710_Tcoh<<6)
  76. +(B6710_Tah<<4)+(B6710_Tacp<<2)+(B6710_PMC));
  78. //v_pIOPRegs->rEINTMASK |= (1<<8);
  79. v_pIOPRegs->rEXTINT1=(v_pIOPRegs->rEXTINT1 & ~(0xf<<0)) | (0x2<<0);  // EINT8 : falling edge trigger
  80. v_pIOPRegs->rEXTINT0=(v_pIOPRegs->rEXTINT0 & ~(0xf<<12)) | (0x2<<12);  // EINT3 : falling edge trigger
  81. v_pIOPRegs->rEINTMASK &= ~(1<<8);
  83. g_PCICIndex = ((volatile PUCHAR)((ULONG)v_pPCMCIAPort+0x3e0));
  84. g_PCICData  = ((volatile PUCHAR)((ULONG)v_pPCMCIAPort+0x3e1));
  86. //
  87. // 0x3E0 is the standard Intel compatible socket controller I/O port.
  88. //
  89. PCICIndex(0, REG_CHIP_REVISION);
  90. tmp = PCICDataRead();
  91. if ((tmp != 0x83) && (tmp != 0x82)) {
  92. DEBUGMSG(1,
  93. (TEXT("PDCardInitServices CHIP_REVISION = 0x%x, expected = 0x83 !!!rn"), tmp));
  94. return ;
  95. }
  97. // otput2card_disable, AUTO_POWER, VCC_POWER_OFF,Vpp1=0V
  98. PCICIndex(0, REG_POWER_CONTROL);
  99. PCICDataWrite((0<<7) | (1<<5) | (0<<4) | (0<<0));
  101. // INPACK_ignored,speak_enable,edge_irq_intr,edge_management_intr,nVCC_3_enabled(temp)
  102. PCICIndex(0, REG_GENERAL_CONTROL);
  104. // Management int, System int -> edge triggering(PULSE)  
  105. //  PCICDataWrite(MISC1_VCC_33|MISC1_PM_IRQ|MISC1_PS_IRQ|MISC1_SPK_ENABLE);
  106. // Management int -> edge triggering(PULSE), System int -> LEVEL triggering 
  107. PCICDataWrite(MISC1_VCC_33|MISC1_PM_IRQ|MISC1_SPK_ENABLE);
  109. // 25Mhz_bypass,low_power_dynamic,IRQ12=drive_LED
  110. PCICIndex(0, REG_GLOBAL_CONTROL);
  111. //  PCICDataWrite(MISC2_BFS|MISC2_LOW_POWER_MODE|MISC2_LED_ENABLE);
  112. PCICDataWrite(MISC2_LOW_POWER_MODE|MISC2_LED_ENABLE);
  114. // before configuring timing register, FIFO should be cleared.
  115. PCICIndex(0, REG_FIFO_CTRL);
  116. PCICDataWrite(FIFO_EMPTY_WRITE);    //Flush FIFO
  118. //default access time is 300ns
  119. PCICIndex(0, REG_SETUP_TIMING0);
  120. PCICDataWrite(5);                   //80ns(no spec)
  121. PCICIndex(0, REG_CMD_TIMING0);
  122. PCICDataWrite(20);                  //320ns(by spec,25Mhz clock)
  123. PCICIndex(0, REG_RECOVERY_TIMING0);
  124. PCICDataWrite(5);                   //80ns(no spec)
  126. //default access time is 300ns
  127. PCICIndex(0, REG_SETUP_TIMING1);
  128. PCICDataWrite(2);                   //80ns(no spec)
  129. PCICIndex(0, REG_CMD_TIMING1);
  130. PCICDataWrite(8);                   //320ns(by spec,25Mhz clock)
  131. PCICIndex(0, REG_RECOVERY_TIMING1);
  132. PCICDataWrite(2);                   //80ns(no spec)
  134. PCICIndex(0, REG_CHIP_INFO);
  135. PCICDataWrite(0);
  137. PCICIndex(0, REG_CHIP_REVISION);
  138. tmp = PCICDataRead();
  139. RETAILMSG(0, (TEXT("PDCardInitServices REG_CHIP_REVISION = 0x%xrn"), tmp));
  141. DEBUGMSG(1, (TEXT("InitSocketNoCard(0) is calledrn")));
  142. // InitSocketNoCard(0);
  144. }
  147. //
  148. // The PCMCIA MDD calls PDCardInitServices to initialize the PDD layer.
  149. //
  150. STATUS
  151. PDCardInitServices(DWORD dwInfo)
  152. {
  153. UINT8 tmp;
  154.  
  155. DEBUGMSG (1,(TEXT("++PDCardInitServicesnr")));
  157. // Since the single PCMCIA slot can be used for download/KITL, we need to check to see if it's in use supporting a KITL
  158. // NIC.  If so, we shouldn't proceed with PCMCIA initialization.
  159. //
  161. // Allocate PCMCIA buffers.
  162. v_pIOPRegs = VirtualAlloc(0, sizeof(IOPreg), MEM_RESERVE, PAGE_NOACCESS);
  163. if (v_pIOPRegs == NULL) 
  164. {
  165. DEBUGMSG (1,(TEXT("v_pIOPRegs is not allocatednr")));
  166. goto pcis_fail;
  167. }
  168. if (!VirtualCopy((PVOID)v_pIOPRegs, (PVOID)IOP_BASE, sizeof(IOPreg), PAGE_READWRITE|PAGE_NOCACHE)) {
  169. DEBUGMSG (1,(TEXT("v_pIOPRegs is not mappednr")));
  170. goto pcis_fail;
  171. }
  172. DEBUGMSG (1,(TEXT("v_pIOPRegs is mapped to %xnr"), v_pIOPRegs));
  174. v_pMEMRegs = VirtualAlloc(0,sizeof(MEMreg), MEM_RESERVE,PAGE_NOACCESS);
  175. if(v_pMEMRegs == NULL) 
  176. {
  177. DEBUGMSG (1,(TEXT("v_pMEMRegs is not allocatednr")));
  178. goto pcis_fail;
  179. }
  180. if(!VirtualCopy((PVOID)v_pMEMRegs,(PVOID)MEMCTRL_BASE,sizeof(MEMreg), PAGE_READWRITE|PAGE_NOCACHE)) {
  181. DEBUGMSG (1,(TEXT("v_pMEMRegs is not mappednr")));
  182. goto pcis_fail;
  183. }    
  184. DEBUGMSG (1,(TEXT("v_pMEMRegs is mapped to %xnr"), v_pMEMRegs));
  186. v_pPCMCIAPort = VirtualAlloc(0, 0x0400, MEM_RESERVE,PAGE_NOACCESS);
  187. if(v_pPCMCIAPort == NULL) 
  188. {
  189. DEBUGMSG (1,(TEXT("v_pPCMCIAPort is not allocatednr")));
  190. goto pcis_fail;
  191. }
  192. if(!VirtualCopy((PVOID)v_pPCMCIAPort,(PVOID)PD6710_IO_BASE_ADDRESS, 0x0400, PAGE_READWRITE|PAGE_NOCACHE)) {
  193. DEBUGMSG (1,(TEXT("v_pPCMCIAPort is not mappednr")));
  194. goto pcis_fail;
  195. }    
  196. DEBUGMSG (1,(TEXT("v_pPCMCIAPort is mapped to %xnr"), v_pPCMCIAPort));
  198. // Initialize S3C2440 for PD6710           
  199. // EINT3(GPF3) is enabled.
  200. v_pIOPRegs->rGPFCON = (v_pIOPRegs->rGPFCON & ~(0x3<<6)) | (0x2<<6); 
  201. // EINT3 is PULLUP enabled.
  202. v_pIOPRegs->rGPFUP = (v_pIOPRegs->rGPFUP & ~(0x1<<3));              
  204. // EINT8(GPG0) is enabled.
  205. v_pIOPRegs->rGPGCON = (v_pIOPRegs->rGPGCON & ~(0x3<<0)) | (0x2<<0); 
  206. // EINT8 is *not* PULLUP enabled.
  207. //v_pIOPRegs->rGPGUP = (v_pIOPRegs->rGPGUP | (0x1<<0));
  208. // jylee
  209. v_pIOPRegs->rGPGUP = (v_pIOPRegs->rGPGUP & ~(0x1<<0)); // pullup enabled
  212. // nGCS2=nUB/nLB(nSBHE),nWAIT,16-bit
  213. v_pMEMRegs->rBWSCON = (v_pMEMRegs->rBWSCON & ~(0xf<<8)) | (0xd<<8); 
  215. // BANK2 access timing
  216. v_pMEMRegs->rBANKCON2 = ((B6710_Tacs<<13)+(B6710_Tcos<<11)+(B6710_Tacc<<8)+(B6710_Tcoh<<6)
  217. +(B6710_Tah<<4)+(B6710_Tacp<<2)+(B6710_PMC));
  220. // jylee 2003.03.19
  221. //v_pIOPRegs->rEXTINT1=(v_pIOPRegs->rEXTINT1 & ~(0xf<<0)) | (0x7<<0); // both edge trigger
  222. v_pIOPRegs->rEXTINT1=(v_pIOPRegs->rEXTINT1 & ~(0xf<<0)) | (0x2<<0);  // EINT8 : falling edge trigger
  223. v_pIOPRegs->rEXTINT0=(v_pIOPRegs->rEXTINT0 & ~(0xf<<12)) | (0x2<<12);  // EINT3 : falling edge trigger
  225. g_PCICIndex = ((volatile PUCHAR)((ULONG)v_pPCMCIAPort+0x3e0));
  226. g_PCICData = ((volatile PUCHAR)((ULONG)v_pPCMCIAPort+0x3e1));
  228. DEBUGMSG(1,
  229. (TEXT("PDCardInitServices g_PCICIndex = 0x%x, g_PCICData = 0x%xrn"),
  230. g_PCICIndex, g_PCICData));
  232. InitializeCriticalSection(&g_PCIC_Crit);
  234. //
  235. // 0x3E0 is the standard Intel compatible socket controller I/O port.
  236. //
  237. PCICIndex(0, REG_CHIP_REVISION);
  238. tmp = PCICDataRead();
  239. if ((tmp != 0x83) && (tmp != 0x82)) {
  240. DEBUGMSG(1,
  241. (TEXT("PDCardInitServices CHIP_REVISION = 0x%x, expected = 0x83 !!!rn"), tmp));
  242. return CERR_BAD_ADAPTER;
  243. }
  245. // otput2card_disable, AUTO_POWER, VCC_POWER_OFF,Vpp1=0V
  246. PCICIndex(0, REG_POWER_CONTROL);
  247. PCICDataWrite((0<<7) | (1<<5) | (0<<4) | (0<<0));
  249. // INPACK_ignored,speak_enable,edge_irq_intr,edge_management_intr,nVCC_3_enabled(temp)
  250. PCICIndex(0, REG_GENERAL_CONTROL);
  252. // Management int, System int -> edge triggering(PULSE)  
  253. //  PCICDataWrite(MISC1_VCC_33|MISC1_PM_IRQ|MISC1_PS_IRQ|MISC1_SPK_ENABLE);
  254. // Management int -> edge triggering(PULSE), System int -> LEVEL triggering 
  255. PCICDataWrite(MISC1_VCC_33|MISC1_PM_IRQ|MISC1_SPK_ENABLE);
  257. // 25Mhz_bypass,low_power_dynamic,IRQ12=drive_LED
  258. PCICIndex(0, REG_GLOBAL_CONTROL);
  259. //  PCICDataWrite(MISC2_BFS|MISC2_LOW_POWER_MODE|MISC2_LED_ENABLE);
  260. PCICDataWrite(MISC2_LOW_POWER_MODE|MISC2_LED_ENABLE);
  262. // before configuring timing register, FIFO should be cleared.
  263. PCICIndex(0, REG_FIFO_CTRL);
  264. PCICDataWrite(FIFO_EMPTY_WRITE);    //Flush FIFO
  266. //default access time is 300ns
  267. PCICIndex(0, REG_SETUP_TIMING0);
  268. PCICDataWrite(5);                   //80ns(no spec)
  269. PCICIndex(0, REG_CMD_TIMING0);
  270. PCICDataWrite(20);                  //320ns(by spec,25Mhz clock)
  271. PCICIndex(0, REG_RECOVERY_TIMING0);
  272. PCICDataWrite(5);                   //80ns(no spec)
  274. //default access time is 300ns
  275. PCICIndex(0, REG_SETUP_TIMING1);
  276. PCICDataWrite(2);                   //80ns(no spec)
  277. PCICIndex(0, REG_CMD_TIMING1);
  278. PCICDataWrite(8);                   //320ns(by spec,25Mhz clock)
  279. PCICIndex(0, REG_RECOVERY_TIMING1);
  280. PCICDataWrite(2);                   //80ns(no spec)
  282. DEBUGMSG(1, (TEXT("InitSocketNoCard(0) is calledrn")));
  283. InitSocketNoCard(0);
  284. //  InitSocketNoCard(1);
  286. PCICIndex(0, REG_CHIP_REVISION);
  287. tmp = PCICDataRead();
  288. DEBUGMSG(1, (TEXT("PDCardInitServices REG_CHIP_REVISION = 0x%xrn"), tmp));
  290. #ifdef DEBUG
  291. DumpSocketRegisters(0);
  292. #endif
  295. DEBUGMSG (1,(TEXT("--PDCardInitServicesnr")));
  297. return CERR_SUCCESS;
  299. pcis_fail:
  300. if (v_pIOPRegs) {
  301. VirtualFree((LPVOID)v_pIOPRegs, 0, MEM_RELEASE);
  302. }
  303. if (v_pMEMRegs) {
  304. VirtualFree((LPVOID)v_pMEMRegs, 0, MEM_RELEASE);
  305. }
  306. if (v_pPCMCIAPort) {
  307. VirtualFree((LPVOID)v_pPCMCIAPort, 0, MEM_RELEASE);
  308. }
  310. return CERR_OUT_OF_RESOURCE;    
  311. }
  314. //
  315. // Function to set the PCIC index register
  316. //
  317. VOID
  318. PCICIndex(
  319. UINT socket_num,
  320. UINT8  register_num
  321. )
  322. {
  323. WRITE_PORT_UCHAR(g_PCICIndex,
  324. (UINT8)((socket_num == 0 ? 0 : 0x40)|register_num));
  325. }
  327. //
  328. // Function to write to the PCIC data register
  329. //
  330. VOID
  331. PCICDataWrite(
  332. UINT8 value
  333. )
  334. {
  335. WRITE_PORT_UCHAR(g_PCICData, value);
  336. }
  338. //
  339. // Function to read the PCIC data register
  340. //
  341. UINT8
  342. PCICDataRead(VOID)
  343. {
  344. return READ_PORT_UCHAR(g_PCICData);
  345. }
  347. #ifdef DEBUG
  348. UCHAR SocketRegisters[2][REG_LAST_INDEX+1];
  350. LPWSTR RegisterNames[] = {
  351. TEXT("REG_CHIP_REVISION"), //                    0x00
  352. TEXT("REG_INTERFACE_STATUS"), //                 0x01
  353. TEXT("REG_POWER_CONTROL"), //                    0x02
  354. TEXT("REG_INTERRUPT_AND_GENERAL_CONTROL"), //    0x03
  355. TEXT("REG_CARD_STATUS_CHANGE"), //               0x04
  356. TEXT("REG_STATUS_CHANGE_INT_CONFIG"), //         0x05
  357. TEXT("REG_WINDOW_ENABLE"), //                    0x06
  358. TEXT("REG_IO_WINDOW_CONTROL"), //                0x07
  359. TEXT("REG_IO_MAP0_START_ADDR_LO"), //            0x08
  360. TEXT("REG_IO_MAP0_START_ADDR_HI"), //            0x09
  361. TEXT("REG_IO_MAP0_END_ADDR_LO"), //              0x0A
  362. TEXT("REG_IO_MAP0_END_ADDR_HI"), //              0x0B
  363. TEXT("REG_IO_MAP1_START_ADDR_LO"), //            0x0C
  364. TEXT("REG_IO_MAP1_START_ADDR_HI"), //            0x0D
  365. TEXT("REG_IO_MAP1_END_ADDR_LO"), //              0x0E
  366. TEXT("REG_IO_MAP1_END_ADDR_HI"), //              0x0F
  367. TEXT("REG_MEM_MAP0_START_ADDR_LO"), //           0x10
  368. TEXT("REG_MEM_MAP0_START_ADDR_HI"), //           0x11
  369. TEXT("REG_MEM_MAP0_END_ADDR_LO"), //             0x12
  370. TEXT("REG_MEM_MAP0_END_ADDR_HI"), //             0x13
  371. TEXT("REG_MEM_MAP0_ADDR_OFFSET_LO"), //          0x14
  372. TEXT("REG_MEM_MAP0_ADDR_OFFSET_HI"), //          0x15
  373. TEXT("REG_GENERAL_CONTROL"), //                  0x16
  374. TEXT("REG_FIFO_CTRL"), //                        0x17
  375. TEXT("REG_MEM_MAP1_START_ADDR_LO"), //           0x18
  376. TEXT("REG_MEM_MAP1_START_ADDR_HI"), //           0x19
  377. TEXT("REG_MEM_MAP1_END_ADDR_LO"), //             0x1A
  378. TEXT("REG_MEM_MAP1_END_ADDR_HI"), //             0x1B
  379. TEXT("REG_MEM_MAP1_ADDR_OFFSET_LO"), //          0x1C
  380. TEXT("REG_MEM_MAP1_ADDR_OFFSET_HI"), //          0x1D
  381. TEXT("REG_GLOBAL_CONTROL"), //                   0x1E
  382. TEXT("REG_CHIP_INFO"), //                        0x1F
  383. TEXT("REG_MEM_MAP2_START_ADDR_LO"), //           0x20
  384. TEXT("REG_MEM_MAP2_START_ADDR_HI"), //           0x21
  385. TEXT("REG_MEM_MAP2_END_ADDR_LO"), //             0x22
  386. TEXT("REG_MEM_MAP2_END_ADDR_HI"), //             0x23
  387. TEXT("REG_MEM_MAP2_ADDR_OFFSET_LO"), //          0x24
  388. TEXT("REG_MEM_MAP2_ADDR_OFFSET_HI"), //          0x25
  389. TEXT("REG_ATA_CTRL"), //                         0x26
  390. TEXT("REG_SCRATCHPAD"), //                       0x27
  391. TEXT("REG_MEM_MAP3_START_ADDR_LO"), //           0x28
  392. TEXT("REG_MEM_MAP3_START_ADDR_HI"), //           0x29
  393. TEXT("REG_MEM_MAP3_END_ADDR_LO"), //             0x2A
  394. TEXT("REG_MEM_MAP3_END_ADDR_HI"), //             0x2B
  395. TEXT("REG_MEM_MAP3_ADDR_OFFSET_LO"), //          0x2C
  396. TEXT("REG_MEM_MAP3_ADDR_OFFSET_HI"), //          0x2D
  397. TEXT("REG_EXTENDED_INDEX"), //                   0x2E
  398. TEXT("REG_EXTENDED_DATA"), //                    0x2F
  399. TEXT("REG_MEM_MAP4_START_ADDR_LO"), //           0x30
  400. TEXT("REG_MEM_MAP4_START_ADDR_HI"), //           0x31
  401. TEXT("REG_MEM_MAP4_END_ADDR_LO"), //             0x32
  402. TEXT("REG_MEM_MAP4_END_ADDR_HI"), //             0x33
  403. TEXT("REG_MEM_MAP4_ADDR_OFFSET_LO"), //          0x34
  404. TEXT("REG_MEM_MAP4_ADDR_OFFSET_HI"), //          0x35
  405. TEXT("REG_CARD_IO_MAP0_OFFSET_L"), //            0x36
  406. TEXT("REG_CARD_IO_MAP0_OFFSET_H"), //            0x37
  407. TEXT("REG_CARD_IO_MAP1_OFFSET_L"), //            0x38
  408. TEXT("REG_CARD_IO_MAP1_OFFSET_H"), //            0x39
  409. TEXT("REG_SETUP_TIMING0"), //                    0x3A
  410. TEXT("REG_CMD_TIMING0"), //                      0x3B
  411. TEXT("REG_RECOVERY_TIMING0"), //                 0x3C
  412. TEXT("REG_CMD_TIMING1"), //                      0x3D
  413. TEXT("REG_CMD_TIMING1"), //                      0x3E
  414. TEXT("REG_RECOVERY_TIMING1"), //                 0x3F
  415. };
  418. VOID
  419. DisplaySocketRegister(
  420. UINT socket,
  421. UCHAR reg,
  422. UCHAR value
  423. )
  424. {
  425. if (reg > (REG_LAST_INDEX+1)) return;
  427. if (RegisterNames[reg] != NULL) {
  428. DEBUGMSG(1,
  429. (TEXT("PCMCIA:PCIC Register[%d:%2x:%s] = 0x%xrn"),
  430. socket, reg, RegisterNames[reg & 0x3f], value));
  431. }
  432. }
  435. VOID
  436. DumpSocketRegisters(
  437. UINT socket
  438. )
  439. {
  440. UCHAR i;
  442.     if (!DEBUGZONE(ZONE_PDD)) return;
  444. for (i = 0; i < REG_LAST_INDEX+1; i++) {
  445. PCICIndex(socket, i);
  446. SocketRegisters[socket][i] = PCICDataRead();
  447. DisplaySocketRegister(socket, i, SocketRegisters[socket][i]);
  448. }
  449. }
  451. VOID
  452. DeltaSocketRegisters(
  453. UINT socket
  454. )
  455. {
  456. static UCHAR idx;
  457. UCHAR CurrentRegisters[REG_LAST_INDEX];
  459.     if (!DEBUGZONE(ZONE_PDD)) return;
  461. DEBUGMSG (1,(TEXT("++DeltaSocketRegisters #%xnr"), socket));
  463. for (idx = 0; idx < REG_LAST_INDEX+1; idx++) {
  464. PCICIndex(socket, idx);
  465. CurrentRegisters[idx] = PCICDataRead();
  466. }
  468. for (idx = 0; idx < REG_LAST_INDEX+1; idx++) {
  469. if (CurrentRegisters[idx] != SocketRegisters[socket][idx]) {
  470. DisplaySocketRegister(socket, idx, CurrentRegisters[idx]);
  471. SocketRegisters[socket][idx] = CurrentRegisters[idx];
  472. }
  473. }
  474. DEBUGMSG (1,(TEXT("--DeltaSocketRegistersnr")));
  475. }
  476. #endif  // DEBUG