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usb.c
资源名称：SMDK2440.rar　[点击查看]
上传用户：qiulin1960
上传日期：2013-10-16
资源大小：2844k
文件大小：35k
源码类别：

Windows CE

开发平台：

Windows_Unix

usb.c：源码内容
  1. //
  2. // Copyright (c) Microsoft Corporation.  All rights reserved.
  3. //
  4. //
  5. // Use of this source code is subject to the terms of the Microsoft end-user
  6. // license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
  7. // If you did not accept the terms of the EULA, you are not authorized to use
  8. // this source code. For a copy of the EULA, please see the LICENSE.RTF on your
  9. // install media.
  10. //
  12. #include <windows.h>
  13. #include <halether.h>
  14. #include <s2440.h>
  15. // #include <S3C2440EVBD.h>
  16. #include "loader.h"
  17. #include <drv_glob.h>
  19. #define USB_BASE 0xB1200140
  20. volatile struct udcreg  * pUSBCtrlAddr;
  21. int g_DMAbufIndex = 0;
  22. int debugM = 0;
  23. volatile int DMADone = 0;
  25. #define REAL_PHYSICAL_ADDR_EP3_FIFO (0x520001CC) //Endpoint 3 FIFO
  26. ULONG realPhysicalAddr_UsbdRxBuf=0;
  28. //OUT_CSR2
  29. #define EPO_OUT_DMA_INT_MASK (1<<5)
  30. #define EPO_ISO   (1<<6)
  31. #define EPO_BULK   (0<<6)
  32. #define EPO_AUTO_CLR (1<<7)
  34. //USB DMA control register
  35. #define UDMA_IN_RUN_OB (1<<7)
  36. #define UDMA_IGNORE_TTC (1<<7)
  37. #define UDMA_DEMAND_MODE (1<<3)
  38. #define UDMA_OUT_RUN_OB (1<<2)
  39. #define UDMA_OUT_DMA_RUN (1<<2)
  40. #define UDMA_IN_DMA_RUN (1<<1)
  41. #define UDMA_DMA_MODE_EN (1<<0)
  43. #define pISR (*(unsigned *)(0x30000000+0x18)) // Virtual Address 0x0 is mapped to 0x30000000, ISR Address is VA 0x18
  44. #define U8 unsigned char
  45. #define U32 unsigned int
  46. #define BUFARRAYSIZE 64
  47. volatile unsigned char downArr[BUFARRAYSIZE];
  48. volatile unsigned char *downPt;
  50. #define DMABUFFER 0x32000000
  51. volatile unsigned int downPtIndex = DMABUFFER;
  52. volatile unsigned int readPtIndex = DMABUFFER;
  53. #define BULK_PKT_SIZE 64
  54. #define EP0_PKT_SIZE 8
  55. #define EP1_PKT_SIZE BULK_PKT_SIZE
  56. #define EP3_PKT_SIZE BULK_PKT_SIZE
  57. U8 ep1Buf[EP1_PKT_SIZE];
  58. int transferIndex=0;
  59. void Isr_Init(void);
  60. void IsrUsbd(unsigned int val);
  61. void IsrHandler(void);
  62. void Ep3Handler(void);
  63. void ConfigEp3DmaMode(U32 bufAddr,U32 count);
  64. void DMA2Handler(void);
  66. #define rEP3_DMA_TTC_L     (*(volatile unsigned char *)0x5200024c) //EP3 DMA total Tx counter
  67. #define rEP3_DMA_TTC_M     (*(volatile unsigned char *)0x52000250)
  68. #define rEP3_DMA_TTC_H     (*(volatile unsigned char *)0x52000254)
  69. #define rEP3_DMA_TTC (pUSBCtrlAddr->EP3DTL.ep3_ttl_l+(pUSBCtrlAddr->EP3DTM.ep3_ttl_m<<8)+(pUSBCtrlAddr->EP3DTH.ep3_ttl_h<<16))
  71. #define SKIP 1
  72. #define DOIT 0
  74. // Standard bmRequestType (Recipient)
  75. #define DEVICE_RECIPIENT            (0)
  76. #define INTERFACE_RECIPIENT         (1)
  77. #define ENDPOINT_RECIPIENT          (2)
  78. #define OTHER_RECIPIENT             (3)
  80. #define EP0_STATE_INIT (0)  
  81. #define EP0_STATE_GD_DEV_0 (10)  //10-10=0 
  82. #define EP0_STATE_GD_DEV_1 (11)  //11-10=1
  83. #define EP0_STATE_GD_DEV_2 (12)  //12-10=2
  84. #define EP0_STATE_GD_CFG_0 (20)
  85. #define EP0_STATE_GD_CFG_1 (21)
  86. #define EP0_STATE_GD_CFG_2 (22)
  87. #define EP0_STATE_GD_CFG_3 (23)
  88. #define EP0_STATE_GD_CFG_4 (24)
  89. #define EP0_STATE_GD_CFG_ONLY_0 (40)
  90. #define EP0_STATE_GD_CFG_ONLY_1 (41)
  91. #define EP0_STATE_GD_IF_ONLY_0 (42)
  92. #define EP0_STATE_GD_IF_ONLY_1 (43)
  93. #define EP0_STATE_GD_EP0_ONLY_0 (44)
  94. #define EP0_STATE_GD_EP1_ONLY_0 (45)
  95. #define EP0_INTERFACE_GET (46)
  96. #define EP0_STATE_GD_STR_I0 (30)  
  97. #define EP0_STATE_GD_STR_I1 (31)  
  98. #define EP0_STATE_GD_STR_I2 (32)  
  99. #define EP0_CONFIG_SET (33)
  100. #define EP0_GET_STATUS0 (35)
  101. #define EP0_GET_STATUS1 (36)
  102. #define EP0_GET_STATUS2 (37)
  103. #define EP0_GET_STATUS3 (38)
  104. #define EP0_GET_STATUS4 (39)
  106. #define CLR_EP0_OUT_PKT_RDY() pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1; pUSBCtrlAddr->EP0ICSR1.sse_ = 0;
  107. #define CLR_EP0_OUTPKTRDY_DATAEND() pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1; pUSBCtrlAddr->EP0ICSR1.de_ff = 1;; pUSBCtrlAddr->EP0ICSR1.sse_ = 0;
  108. #define SET_EP0_IN_PKT_RDY()  pUSBCtrlAddr->EP0ICSR1.ipr_ = 1; pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 0; pUSBCtrlAddr->EP0ICSR1.sse_ = 0;
  110. #define SET_EP0_INPKTRDY_DATAEND()  pUSBCtrlAddr->EP0ICSR1.ipr_ = 1; pUSBCtrlAddr->EP0ICSR1.de_ff = 1; pUSBCtrlAddr->EP0ICSR1.sse_ = 0; pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 0;
  111. #define CLR_EP0_SETUP_END()  pUSBCtrlAddr->EP0ICSR1.sse_ = 1; pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 0;
  112. #define CLR_EP0_SENT_STALL()  pUSBCtrlAddr->EP0ICSR1.sts_ur = 0; pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 0; pUSBCtrlAddr->EP0ICSR1.sse_ = 0;
  113. #define FLUSH_EP0_FIFO()  {while(pUSBCtrlAddr->OFCR1.out_cnt_low) pUSBCtrlAddr->EP0F.fifo_data;}
  115. #define CLR_EP3_OUT_PKT_READY() pUSBCtrlAddr->OCSR1.fifo_flush = 0; pUSBCtrlAddr->OCSR1.send_stall = 0; pUSBCtrlAddr->OCSR1.clr_data_tog = 0; pUSBCtrlAddr->OCSR1.out_pkt_rdy = 0;
  116. #define CLR_EP3_SENT_STALL() pUSBCtrlAddr->OCSR1.fifo_flush = 0; pUSBCtrlAddr->OCSR1.send_stall = 0; pUSBCtrlAddr->OCSR1.clr_data_tog = 0; pUSBCtrlAddr->OCSR1.sent_stall = 0;
  118. volatile U8 Rwuen;
  119. volatile U8 Selfpwr=TRUE;
  120. U32 ep0State;
  122. struct USB_SETUP_DATA{
  123. U8 bmRequestType;    
  124. U8 bRequest;         
  125. U8 bValueL;          
  126. U8 bValueH;          
  127. U8 bIndexL;          
  128. U8 bIndexH;          
  129. U8 bLengthL;         
  130. U8 bLengthH;         
  131. };
  133. struct USB_DEVICE_DESCRIPTOR{
  134. U8 bLength;    
  135. U8 bDescriptorType;         
  136. U8 bcdUSBL;
  137. U8 bcdUSBH;
  138. U8 bDeviceClass;
  139. U8 bDeviceSubClass;
  140. U8 bDeviceProtocol;
  141. U8 bMaxPacketSize0;
  142. U8 idVendorL;
  143. U8 idVendorH;
  144. U8 idProductL;
  145. U8 idProductH;
  146. U8 bcdDeviceL;
  147. U8 bcdDeviceH;
  148. U8 iManufacturer;
  149. U8 iProduct;
  150. U8 iSerialNumber;
  151. U8 bNumConfigurations;
  152. };
  154. struct USB_CONFIGURATION_DESCRIPTOR{
  155. U8 bLength;    
  156. U8 bDescriptorType;         
  157. U8 wTotalLengthL;
  158. U8 wTotalLengthH;
  159. U8 bNumInterfaces;
  160. U8 bConfigurationValue;
  161. U8 iConfiguration;
  162. U8 bmAttributes;
  163. U8 maxPower;          
  164. };
  166. struct USB_INTERFACE_DESCRIPTOR{
  167. U8 bLength;    
  168. U8 bDescriptorType;         
  169. U8 bInterfaceNumber;
  170. U8 bAlternateSetting;
  171. U8 bNumEndpoints;
  172. U8 bInterfaceClass;
  173. U8 bInterfaceSubClass;
  174. U8 bInterfaceProtocol;
  175. U8 iInterface;
  176. };
  178. struct USB_ENDPOINT_DESCRIPTOR{
  179. U8 bLength;    
  180. U8 bDescriptorType;         
  181. U8 bEndpointAddress;
  182. U8 bmAttributes;
  183. U8 wMaxPacketSizeL;
  184. U8 wMaxPacketSizeH;
  185. U8 bInterval;
  186. };
  188. struct USB_CONFIGURATION_SET{
  189. U8 ConfigurationValue;
  190. };
  192. struct USB_GET_STATUS{
  193. U8 Device;
  194. U8 Interface;
  195. U8 Endpoint0;
  196. U8 Endpoint1;
  197. U8 Endpoint3;
  198. };
  200. struct USB_INTERFACE_GET{
  201. U8 AlternateSetting;
  202. };
  204. struct USB_SETUP_DATA descSetup;
  205. struct USB_DEVICE_DESCRIPTOR descDev;
  206. struct USB_CONFIGURATION_DESCRIPTOR descConf;
  207. struct USB_INTERFACE_DESCRIPTOR descIf;
  208. struct USB_ENDPOINT_DESCRIPTOR descEndpt0;
  209. struct USB_ENDPOINT_DESCRIPTOR descEndpt1;
  210. struct USB_CONFIGURATION_SET ConfigSet;
  211. struct USB_INTERFACE_GET InterfaceGet;
  212. struct USB_GET_STATUS StatusGet;   //={0,0,0,0,0};
  214. // Descriptor Types
  215. #define USB_DEVICE_TYPE                 (1)
  216. #define CONFIGURATION_TYPE          (2)
  217. #define STRING_TYPE                 (3)
  218. #define INTERFACE_TYPE              (4)
  219. #define ENDPOINT_TYPE               (5)
  221. //string descriptor
  222. #define LANGID_US_L      (0x09)  
  223. #define LANGID_US_H      (0x04)
  225. // Standard Request Codes 
  226. #define GET_STATUS                  (0)
  227. #define CLEAR_FEATURE               (1)
  228. #define SET_FEATURE                 (3)
  229. #define SET_ADDRESS                 (5)
  230. #define GET_DESCRIPTOR              (6)
  231. #define SET_DESCRIPTOR              (7)
  232. #define GET_CONFIGURATION           (8)
  233. #define SET_CONFIGURATION           (9)
  234. #define GET_INTERFACE               (10)
  235. #define SET_INTERFACE               (11)
  236. #define SYNCH_FRAME                 (12)
  238. //configuration descriptor: bmAttributes 
  239. #define CONF_ATTR_DEFAULT     (0x80) //Spec 1.0 it was BUSPOWERED bit.
  240. #define CONF_ATTR_REMOTE_WAKEUP     (0x20)
  241. #define CONF_ATTR_SELFPOWERED       (0x40)
  243. //endpoint descriptor
  244. #define EP_ADDR_IN     (0x80)
  245. #define EP_ADDR_OUT     (0x00)
  247. #define EP_ATTR_CONTROL     (0x0)
  248. #define EP_ATTR_ISOCHRONOUS     (0x1)
  249. #define EP_ATTR_BULK     (0x2)
  250. #define EP_ATTR_INTERRUPT     (0x3)
  252. static const U8 descStr0[]={
  253. 4,STRING_TYPE,LANGID_US_L,LANGID_US_H,  //codes representing languages
  254.     };
  256. static const U8 descStr1[]={  //Manufacturer  
  257.         (0x14+2),STRING_TYPE, 
  258.         'S',0x0,'y',0x0,'s',0x0,'t',0x0,'e',0x0,'m',0x0,' ',0x0,'M',0x0,
  259.         'C',0x0,'U',0x0,
  260.     };
  261.     
  262. static const U8 descStr2[]={  //Product  
  263.         (0x2a+2),STRING_TYPE, 
  264.         'S',0x0,'E',0x0,'C',0x0,' ',0x0,'S',0x0,'3',0x0,'C',0x0,'2',0x0,
  265.         '4',0x0,'1',0x0,'0',0x0,'X',0x0,' ',0x0,'T',0x0,'e',0x0,'s',0x0,
  266.         't',0x0,' ',0x0,'B',0x0,'/',0x0,'D',0x0
  267.     };
  269. void InitDescriptorTable(void)
  270. {
  271.     //Standard device descriptor
  272.     descDev.bLength=0x12; //EP0_DEV_DESC_SIZE=0x12 bytes    
  273.     descDev.bDescriptorType=USB_DEVICE_TYPE;
  274.     descDev.bcdUSBL=0x10;
  275.     descDev.bcdUSBH=0x01;  //Ver 1.10
  276.     descDev.bDeviceClass=0xFF; //0x0          
  277.     descDev.bDeviceSubClass=0x0;          
  278.     descDev.bDeviceProtocol=0x0;          
  279.     descDev.bMaxPacketSize0=0x8;         
  280.     descDev.idVendorL=0x45;
  281.     descDev.idVendorH=0x53;
  282.     descDev.idProductL=0x34;
  283.     descDev.idProductH=0x12;
  284.     descDev.bcdDeviceL=0x00;
  285.     descDev.bcdDeviceH=0x01;
  286.     descDev.iManufacturer=0x1;  //index of string descriptor
  287.     descDev.iProduct=0x2; //index of string descriptor 
  288.     descDev.iSerialNumber=0x0;
  289.     descDev.bNumConfigurations=0x1;
  291.     //Standard configuration descriptor
  292.     descConf.bLength=0x9;    
  293.     descConf.bDescriptorType=CONFIGURATION_TYPE;         
  294.     descConf.wTotalLengthL=0x20; //<cfg desc>+<if desc>+<endp0 desc>+<endp1 desc>
  295.     descConf.wTotalLengthH=0;
  296.     descConf.bNumInterfaces=1;
  297. //dbg    descConf.bConfigurationValue=2;  //why 2? There's no reason.
  298.     descConf.bConfigurationValue=1;  
  299.     descConf.iConfiguration=0;
  300.     descConf.bmAttributes=CONF_ATTR_DEFAULT|CONF_ATTR_SELFPOWERED;  //bus powered only.
  301.     descConf.maxPower=25; //draws 50mA current from the USB bus.          
  303.     //Standard interface descriptor
  304.     descIf.bLength=0x9;    
  305.     descIf.bDescriptorType=INTERFACE_TYPE;         
  306.     descIf.bInterfaceNumber=0x0;
  307.     descIf.bAlternateSetting=0x0; //?
  308.     descIf.bNumEndpoints=2; //# of endpoints except EP0
  309.     descIf.bInterfaceClass=0xff; //0x0 ?
  310.     descIf.bInterfaceSubClass=0x0;  
  311.     descIf.bInterfaceProtocol=0x0;
  312.     descIf.iInterface=0x0;
  314.     //Standard endpoint0 descriptor
  315.     descEndpt0.bLength=0x7;    
  316.     descEndpt0.bDescriptorType=ENDPOINT_TYPE;         
  317.     descEndpt0.bEndpointAddress=1|EP_ADDR_IN;   // 2400Xendpoint 1 is IN endpoint.
  318.     descEndpt0.bmAttributes=EP_ATTR_BULK;
  319.     descEndpt0.wMaxPacketSizeL=EP1_PKT_SIZE; //64
  320.     descEndpt0.wMaxPacketSizeH=0x0;
  321.     descEndpt0.bInterval=0x0; //not used
  323.     //Standard endpoint1 descriptor
  324.     descEndpt1.bLength=0x7;    
  325.     descEndpt1.bDescriptorType=ENDPOINT_TYPE;         
  326.     descEndpt1.bEndpointAddress=3|EP_ADDR_OUT;   // 2400X endpoint 3 is OUT endpoint.
  327.     descEndpt1.bmAttributes=EP_ATTR_BULK;
  328.     descEndpt1.wMaxPacketSizeL=EP3_PKT_SIZE; //64
  329.     descEndpt1.wMaxPacketSizeH=0x0;
  330.     descEndpt1.bInterval=0x0; //not used 
  331. }
  333. BOOL InitUSB()
  334. {
  335. BYTE index;
  336. UCHAR cRxChar;
  338. volatile INTreg *s2440INT = (INTreg *)INT_BASE;
  339. pUSBCtrlAddr = (PUSHORT)(USB_BASE);
  341.     InitDescriptorTable();
  343.     //
  344.     // Initialize the USBD Controller
  345.     //
  346.     index = pUSBCtrlAddr->INDEX.index;
  348.     // suspend mode disable
  349.     pUSBCtrlAddr->PMR.sus_en = 0x0;
  351.     // setup endpoint 0
  352.     pUSBCtrlAddr->INDEX.index = 0;
  353.     pUSBCtrlAddr->MAXP.maxp = 0x1;         // 8 BYTE
  354.     pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;   // OUT_PKT_RDY
  355.     pUSBCtrlAddr->EP0ICSR1.sse_ = 1;       // SETUP_END
  357.     // setup endpoint 1
  358.     pUSBCtrlAddr->INDEX.index = 1;
  359.     pUSBCtrlAddr->MAXP.maxp = 0x8;     // 64 BYTE
  360. pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
  361. pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
  362.     pUSBCtrlAddr->ICSR2.mode_in = 1;   // IN
  363.     pUSBCtrlAddr->ICSR2.iso = 0;       // BULK
  365.     // setup endpoint 3
  366.     pUSBCtrlAddr->INDEX.index = 3;
  367.     pUSBCtrlAddr->MAXP.maxp = 0x8;     // 64 BYTE
  368. pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
  369. pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
  370.     pUSBCtrlAddr->ICSR2.mode_in = 0;   // OUT
  371.     pUSBCtrlAddr->OCSR2.iso = 0;       // BULK
  373.     // clear all EP interrupts
  374.     pUSBCtrlAddr->EIR.ep0_int = 0x1;
  375.     pUSBCtrlAddr->EIR.ep1_int = 0x1;
  376.     pUSBCtrlAddr->EIR.ep2_int = 0x1;
  377.     pUSBCtrlAddr->EIR.ep3_int = 0x1;
  378.     pUSBCtrlAddr->EIR.ep4_int = 0x1;
  380.     // clear reset int
  381.     pUSBCtrlAddr->UIR.reset_int = 0x1;
  383.     // EP0, 1, & 3 Enabled, EP2, 4 Disabled
  384.     pUSBCtrlAddr->EIER.ep0_int_en = 0x1;
  385.     pUSBCtrlAddr->EIER.ep2_int_en = 0x0;
  386.     pUSBCtrlAddr->EIER.ep4_int_en = 0x0;
  387.     pUSBCtrlAddr->EIER.ep1_int_en = 0x1;
  388.     pUSBCtrlAddr->EIER.ep3_int_en = 0x1;
  390.     // enable reset int 
  391.     pUSBCtrlAddr->UIER.reset_int_en = 0x1;
  393. return TRUE;
  394. }
  396. void PrintEp0Pkt(U8 *pt)
  397. {
  398.     int i;
  399. EdbgOutputDebugString("[RCV:");
  400. for(i=0;i<EP0_PKT_SIZE;i++)
  401. EdbgOutputDebugString("%x,",pt[i]);
  402. EdbgOutputDebugString("]rn");
  403. }
  405. void WrPktEp0(U8 *buf,int num)
  406. {
  407. int i;
  408.     
  409. for(i=0;i<num;i++)
  410. {
  411. pUSBCtrlAddr->EP0F.fifo_data = buf[i];
  412. }
  413. }
  415. void WrPktEp1(U8 *buf,int num)
  416. {
  417.     int i;
  418.     
  419.     for(i=0;i<num;i++)
  420.     {
  421.         pUSBCtrlAddr->EP1F.fifo_data = buf[i];
  422.     }
  423. }
  425. void RdPktEp0(U8 *buf,int num)
  426. {
  427.     int i;
  428.     
  429.     for(i=0;i<num;i++)
  430.     {
  431.         buf[i]=(U8)pUSBCtrlAddr->EP0F.fifo_data;
  432.     }
  433. }
  435. void RdPktEp3(U8 *buf,int num)
  436. {
  437. int i;
  439. for(i=0;i<num;i++)
  440. {
  441. buf[i]=(U8)(pUSBCtrlAddr->EP3F.fifo_data);
  442.     }
  443. }
  445. void PrepareEp1Fifo(void) 
  446. {
  447.     int i;
  448.     pUSBCtrlAddr->INDEX.index=1;
  449.     
  450.     for(i=0;i<EP1_PKT_SIZE;i++)ep1Buf[i]=(U8)(transferIndex+i);
  451.     WrPktEp1(ep1Buf,EP1_PKT_SIZE);
  452. pUSBCtrlAddr->EP0ICSR1.opr_ipr = 1;
  453. pUSBCtrlAddr->EP0ICSR1.sts_ur = 0;
  454. pUSBCtrlAddr->EP0ICSR1.de_ff = 0;
  455. }
  457. void Ep1Handler(void)
  458. {
  459.     pUSBCtrlAddr->INDEX.index=1;
  460.     
  461.     if(pUSBCtrlAddr->EP0ICSR1.sds_sts)
  462.     {   
  463. pUSBCtrlAddr->EP0ICSR1.opr_ipr = 0;
  464. pUSBCtrlAddr->EP0ICSR1.sts_ur = 0;
  465. pUSBCtrlAddr->EP0ICSR1.de_ff = 0;
  466. pUSBCtrlAddr->EP0ICSR1.sds_sts = 0;
  467.     return;
  468.     }
  470.     transferIndex++;
  472.     PrepareEp1Fifo(); 
  474.     return;
  475. }
  477. void Ep0Handler(void)
  478. {
  479. static int ep0SubState;
  481. pUSBCtrlAddr->INDEX.index=0;
  483. //DATAEND interrupt(ep0_csr==0x0) will be ignored 
  484. //because ep0State==EP0_STATE_INIT when the DATAEND interrupt is issued.
  486. // EdbgOutputDebugString("INFO : Ep0Handlerrn");
  488. if(pUSBCtrlAddr->EP0ICSR1.se_sds)
  489. {   
  490. // Host may end GET_DESCRIPTOR operation without completing the IN data stage.
  491. // If host does that, SETUP_END bit will be set.
  492. // OUT_PKT_RDY has to be also cleared because status stage sets OUT_PKT_RDY to 1.
  493. CLR_EP0_SETUP_END();
  494. if(pUSBCtrlAddr->EP0ICSR1.opr_ipr) 
  495. {
  496. FLUSH_EP0_FIFO(); //(???)
  497. //I think this isn't needed because EP0 flush is done automatically.   
  498. CLR_EP0_OUT_PKT_RDY();
  499. }
  501. ep0State=EP0_STATE_INIT;
  502. return;
  503. }
  505. //I think that EP0_SENT_STALL will not be set to 1.
  506. if(pUSBCtrlAddr->EP0ICSR1.sts_ur)
  507. {   
  508. EdbgOutputDebugString("[STALL]rn");
  509. CLR_EP0_SENT_STALL();
  510. if(pUSBCtrlAddr->EP0ICSR1.opr_ipr)
  511. {
  512. CLR_EP0_OUT_PKT_RDY();
  513. }
  515. ep0State=EP0_STATE_INIT;
  516. return;
  517. }
  519. if((pUSBCtrlAddr->EP0ICSR1.opr_ipr) && (ep0State==EP0_STATE_INIT))
  520. {
  521. RdPktEp0((U8 *)&descSetup,EP0_PKT_SIZE);
  523. switch(descSetup.bRequest)
  524. {
  525. case GET_DESCRIPTOR:
  526. switch(descSetup.bValueH)        
  527. {
  528.             case USB_DEVICE_TYPE:
  529. CLR_EP0_OUT_PKT_RDY();
  530. ep0State=EP0_STATE_GD_DEV_0;         
  531. break;
  532. case CONFIGURATION_TYPE:
  533. CLR_EP0_OUT_PKT_RDY();
  534. if((descSetup.bLengthL+(descSetup.bLengthH<<8))>0x9)
  535. //bLengthH should be used for bLength=0x209 at WIN2K.    
  536. ep0State=EP0_STATE_GD_CFG_0; //for WIN98,WIN2K
  537. else          
  538. ep0State=EP0_STATE_GD_CFG_ONLY_0; //for WIN2K
  539. break;
  540. case STRING_TYPE:
  541. CLR_EP0_OUT_PKT_RDY();
  542. switch(descSetup.bValueL)
  543. {
  544. case 0:
  545. ep0State=EP0_STATE_GD_STR_I0;
  546. break;
  547. case 1:
  548. ep0State=EP0_STATE_GD_STR_I1;
  549. break;
  550. case 2:
  551. ep0State=EP0_STATE_GD_STR_I2;
  552. break;
  553. default:
  554. EdbgOutputDebugString("[UE:STRI?]rn");
  555. break;
  556. }
  557. ep0SubState=0;
  558. break;
  559. case INTERFACE_TYPE:
  560. EdbgOutputDebugString("[GDI]rn");
  561. CLR_EP0_OUT_PKT_RDY();
  562. ep0State=EP0_STATE_GD_IF_ONLY_0; //for WIN98
  563. break;
  564. case ENDPOINT_TYPE:     
  565. EdbgOutputDebugString("[GDE]rn");
  566. CLR_EP0_OUT_PKT_RDY();
  567. switch(descSetup.bValueL&0xf)
  568. {
  569. case 0:
  570. ep0State=EP0_STATE_GD_EP0_ONLY_0;
  571. break;
  572. case 1:
  573. ep0State=EP0_STATE_GD_EP1_ONLY_0;
  574. break;
  575. default:
  576. EdbgOutputDebugString("[UE:GDE?]rn");
  577. break;
  578. }
  579. break;
  580. default:
  581. EdbgOutputDebugString("[UE:GD?]rn");
  582. break;
  583. }
  584. break;
  586. case SET_ADDRESS:
  587. pUSBCtrlAddr->udcFAR.func_addr = descSetup.bValueL;
  588. pUSBCtrlAddr->udcFAR.addr_up = 1;
  589. CLR_EP0_OUTPKTRDY_DATAEND(); //Because of no data control transfers.
  590. ep0State=EP0_STATE_INIT;
  591. break;
  592.     
  593. case SET_CONFIGURATION:
  594. ConfigSet.ConfigurationValue=descSetup.bValueL;
  595. CLR_EP0_OUTPKTRDY_DATAEND(); //Because of no data control transfers.
  596. ep0State=EP0_STATE_INIT;
  598. break;
  600. //////////////////////// For chapter 9 test ////////////////////
  602. case CLEAR_FEATURE:
  603. switch (descSetup.bmRequestType)
  604. {
  605. case DEVICE_RECIPIENT:
  606. if (descSetup.bValueL == 1)
  607. Rwuen = FALSE;
  608. break;
  610. case ENDPOINT_RECIPIENT:
  611. if (descSetup.bValueL == 0)
  612. {
  613. if((descSetup.bIndexL & 0x7f) == 0x00){
  614. StatusGet.Endpoint0= 0;    
  615. }
  616. if((descSetup.bIndexL & 0x8f) == 0x81){           // IN  Endpoint 1
  617. StatusGet.Endpoint1= 0;           
  618. }
  619. if((descSetup.bIndexL & 0x8f) == 0x03){          // OUT Endpoint 3
  620. StatusGet.Endpoint3= 0;      
  621. }
  622. }
  623. break;
  625. default:
  626. break;
  627. }
  628. CLR_EP0_OUTPKTRDY_DATAEND();
  629. ep0State=EP0_STATE_INIT;
  630. break;
  632. case GET_CONFIGURATION:
  633. CLR_EP0_OUT_PKT_RDY();
  634. ep0State=EP0_CONFIG_SET;
  635. break;
  637. case GET_INTERFACE:
  638. CLR_EP0_OUT_PKT_RDY();
  639. ep0State=EP0_INTERFACE_GET;
  640. break;
  642. case GET_STATUS:
  643. switch(descSetup.bmRequestType)
  644. {
  645. case  (0x80):
  646. CLR_EP0_OUT_PKT_RDY();
  647. StatusGet.Device=((U8)Rwuen<<1)|(U8)Selfpwr;
  648. ep0State=EP0_GET_STATUS0;
  649. break;
  651. case  (0x81):
  652. CLR_EP0_OUT_PKT_RDY();
  653. StatusGet.Interface=0;
  654. ep0State=EP0_GET_STATUS1;
  655. break;
  657. case  (0x82):
  658. CLR_EP0_OUT_PKT_RDY();
  659. if((descSetup.bIndexL & 0x7f) == 0x00){
  660. ep0State=EP0_GET_STATUS2;
  661. }
  662. if((descSetup.bIndexL & 0x8f) == 0x81){
  663. ep0State=EP0_GET_STATUS3;
  664. }
  665. if((descSetup.bIndexL & 0x8f) == 0x03){
  666. ep0State=EP0_GET_STATUS4;
  667. }
  668. break;
  670. default:
  671. break;
  672.         }
  673.         break;
  675. case SET_DESCRIPTOR:
  676. CLR_EP0_OUTPKTRDY_DATAEND();
  677. ep0State=EP0_STATE_INIT;
  678. break;
  680. case SET_FEATURE:
  681. switch (descSetup.bmRequestType)
  682. {
  683. case DEVICE_RECIPIENT:
  684. if (descSetup.bValueL == 1)
  685. Rwuen = TRUE;
  686. break;
  688. case ENDPOINT_RECIPIENT:
  689. if (descSetup.bValueL == 0)
  690. {
  691. if((descSetup.bIndexL & 0x7f) == 0x00){
  692. StatusGet.Endpoint0= 1;
  693. }
  694. if((descSetup.bIndexL & 0x8f) == 0x81){
  695. StatusGet.Endpoint1= 1;
  696. }
  697. if((descSetup.bIndexL & 0x8f) == 0x03){
  698. StatusGet.Endpoint3= 1;
  699. }
  700. }
  701. break;
  702. default:
  703. break;
  704. }
  705. CLR_EP0_OUTPKTRDY_DATAEND();
  706. ep0State=EP0_STATE_INIT;
  707. break;
  709. case SET_INTERFACE:
  710. InterfaceGet.AlternateSetting= descSetup.bValueL;
  711. CLR_EP0_OUTPKTRDY_DATAEND(); 
  712. ep0State=EP0_STATE_INIT;
  713. break;
  715. case SYNCH_FRAME:
  716. ep0State=EP0_STATE_INIT;
  717. break;
  719.        //////////////////////////////////////////////////////////////
  721. default:
  722. EdbgOutputDebugString("[UE:SETUP=%x]rn",descSetup.bRequest);
  723. CLR_EP0_OUTPKTRDY_DATAEND(); //Because of no data control transfers.
  724. ep0State=EP0_STATE_INIT;
  725. break;
  726. }
  727. }
  729. switch(ep0State)
  730. {
  731. case EP0_STATE_INIT:
  732. break; 
  734. //=== GET_DESCRIPTOR:DEVICE ===
  735. case EP0_STATE_GD_DEV_0:
  736. WrPktEp0((U8 *)&descDev+0,8); //EP0_PKT_SIZE
  737. SET_EP0_IN_PKT_RDY();
  738. ep0State=EP0_STATE_GD_DEV_1;
  739. break;
  741. case EP0_STATE_GD_DEV_1:
  742. WrPktEp0((U8 *)&descDev+0x8,8); 
  743. SET_EP0_IN_PKT_RDY();
  744. ep0State=EP0_STATE_GD_DEV_2;
  745. break;
  747. case EP0_STATE_GD_DEV_2:
  748. WrPktEp0((U8 *)&descDev+0x10,2);   //8+8+2=0x12
  749. SET_EP0_INPKTRDY_DATAEND();
  750. ep0State=EP0_STATE_INIT;
  751. break;
  753. //=== GET_DESCRIPTOR:CONFIGURATION+INTERFACE+ENDPOINT0+ENDPOINT1 ===
  754. //Windows98 gets these 4 descriptors all together by issuing only a request.
  755. //Windows2000 gets each descriptor seperately.
  756. case EP0_STATE_GD_CFG_0:
  757. WrPktEp0((U8 *)&descConf+0,8); //EP0_PKT_SIZE
  758. SET_EP0_IN_PKT_RDY();
  759. ep0State=EP0_STATE_GD_CFG_1;
  760. break;
  762. case EP0_STATE_GD_CFG_1:
  763. WrPktEp0((U8 *)&descConf+8,1); 
  764. WrPktEp0((U8 *)&descIf+0,7); 
  765. SET_EP0_IN_PKT_RDY();
  766. ep0State=EP0_STATE_GD_CFG_2;
  767. break;
  769. case EP0_STATE_GD_CFG_2:
  770. WrPktEp0((U8 *)&descIf+7,2); 
  771. WrPktEp0((U8 *)&descEndpt0+0,6); 
  772. SET_EP0_IN_PKT_RDY();
  773. ep0State=EP0_STATE_GD_CFG_3;
  774. break;
  776. case EP0_STATE_GD_CFG_3:
  777. WrPktEp0((U8 *)&descEndpt0+6,1); 
  778. WrPktEp0((U8 *)&descEndpt1+0,7); 
  779. SET_EP0_IN_PKT_RDY();
  780. ep0State=EP0_STATE_GD_CFG_4;            
  781. break;
  783. case EP0_STATE_GD_CFG_4:
  784.  //zero length data packit 
  785. SET_EP0_INPKTRDY_DATAEND();
  786. ep0State=EP0_STATE_INIT;            
  787. break;
  789. //=== GET_DESCRIPTOR:CONFIGURATION ONLY===
  790. case EP0_STATE_GD_CFG_ONLY_0:
  791. WrPktEp0((U8 *)&descConf+0,8); //EP0_PKT_SIZE
  792. SET_EP0_IN_PKT_RDY();
  793. ep0State=EP0_STATE_GD_CFG_ONLY_1;
  794. break;
  795.     
  796. case EP0_STATE_GD_CFG_ONLY_1:
  797. WrPktEp0((U8 *)&descConf+8,1); 
  798. SET_EP0_INPKTRDY_DATAEND();
  799. ep0State=EP0_STATE_INIT;            
  800. break;
  802. //=== GET_DESCRIPTOR:INTERFACE ONLY===
  803. case EP0_STATE_GD_IF_ONLY_0:
  804. EdbgOutputDebugString("[GDI0]rn");
  805. WrPktEp0((U8 *)&descIf+0,8); 
  806. SET_EP0_IN_PKT_RDY();
  807. ep0State=EP0_STATE_GD_IF_ONLY_1;
  808. break;
  810. case EP0_STATE_GD_IF_ONLY_1:
  811. EdbgOutputDebugString("[GDI1]rn");
  812. WrPktEp0((U8 *)&descIf+8,1); 
  813. SET_EP0_INPKTRDY_DATAEND();
  814. ep0State=EP0_STATE_INIT;            
  815. break;
  817. //=== GET_DESCRIPTOR:ENDPOINT 0 ONLY===
  818. case EP0_STATE_GD_EP0_ONLY_0:
  819. EdbgOutputDebugString("[GDE00]rn");
  820. WrPktEp0((U8 *)&descEndpt0+0,7); 
  821. SET_EP0_INPKTRDY_DATAEND();
  822. ep0State=EP0_STATE_INIT;            
  823. break;
  824.             
  825. //=== GET_DESCRIPTOR:ENDPOINT 1 ONLY===
  826. case EP0_STATE_GD_EP1_ONLY_0:
  827. EdbgOutputDebugString("[GDE10]rn");
  828. WrPktEp0((U8 *)&descEndpt1+0,7); 
  829. SET_EP0_INPKTRDY_DATAEND();
  830. ep0State=EP0_STATE_INIT;            
  831. break;
  832.             
  833. ////////////////////////////////////////////
  835. case EP0_INTERFACE_GET:
  836. WrPktEp0((U8 *)&InterfaceGet+0,1);
  837. SET_EP0_INPKTRDY_DATAEND();
  838. ep0State=EP0_STATE_INIT;      
  839. break;
  841.  
  842. //=== GET_DESCRIPTOR:STRING ===
  843. case EP0_STATE_GD_STR_I0:
  844. WrPktEp0((U8 *)descStr0, 4 );  
  845. SET_EP0_INPKTRDY_DATAEND();
  846. ep0State=EP0_STATE_INIT;     
  847. ep0SubState=0;
  848. break;
  850. case EP0_STATE_GD_STR_I1:
  851. if( (ep0SubState*EP0_PKT_SIZE+EP0_PKT_SIZE)<sizeof(descStr1) )
  852. {
  853. WrPktEp0((U8 *)descStr1+(ep0SubState*EP0_PKT_SIZE),EP0_PKT_SIZE); 
  854. SET_EP0_IN_PKT_RDY();
  855. ep0State=EP0_STATE_GD_STR_I1;
  856. ep0SubState++;
  857. }
  858. else
  859. {
  860. WrPktEp0((U8 *)descStr1+(ep0SubState*EP0_PKT_SIZE),
  861. sizeof(descStr1)-(ep0SubState*EP0_PKT_SIZE)); 
  862. SET_EP0_INPKTRDY_DATAEND();
  863. ep0State=EP0_STATE_INIT;     
  864. ep0SubState=0;
  865. }
  866. break;
  868. case EP0_STATE_GD_STR_I2:
  869. if( (ep0SubState*EP0_PKT_SIZE+EP0_PKT_SIZE)<sizeof(descStr2) )
  870. {
  871. WrPktEp0((U8 *)descStr2+(ep0SubState*EP0_PKT_SIZE),EP0_PKT_SIZE); 
  872. SET_EP0_IN_PKT_RDY();
  873. ep0State=EP0_STATE_GD_STR_I2;
  874. ep0SubState++;
  875. }
  876. else
  877. {
  878. WrPktEp0((U8 *)descStr2+(ep0SubState*EP0_PKT_SIZE),
  879. sizeof(descStr2)-(ep0SubState*EP0_PKT_SIZE)); 
  880. SET_EP0_INPKTRDY_DATAEND();
  881. ep0State=EP0_STATE_INIT;     
  882. ep0SubState=0;
  883. }
  884. break;
  886. case EP0_CONFIG_SET:
  887. WrPktEp0((U8 *)&ConfigSet+0,1); 
  888. SET_EP0_INPKTRDY_DATAEND();
  889. ep0State=EP0_STATE_INIT;      
  890. break;
  892. case EP0_GET_STATUS0:
  893. WrPktEp0((U8 *)&StatusGet+0,1);
  894. SET_EP0_INPKTRDY_DATAEND();
  895. ep0State=EP0_STATE_INIT;      
  896. break;
  898. case EP0_GET_STATUS1:
  899. WrPktEp0((U8 *)&StatusGet+1,1);
  900. SET_EP0_INPKTRDY_DATAEND();
  901. ep0State=EP0_STATE_INIT;      
  902. break;
  904. case EP0_GET_STATUS2:
  905. WrPktEp0((U8 *)&StatusGet+2,1);
  906. SET_EP0_INPKTRDY_DATAEND();
  907. ep0State=EP0_STATE_INIT;      
  908. break;
  910. case EP0_GET_STATUS3:
  911. WrPktEp0((U8 *)&StatusGet+3,1);
  912. SET_EP0_INPKTRDY_DATAEND();
  913. ep0State=EP0_STATE_INIT;      
  914. break;
  916. case EP0_GET_STATUS4:
  917. WrPktEp0((U8 *)&StatusGet+4,1);
  918. SET_EP0_INPKTRDY_DATAEND();
  919. ep0State=EP0_STATE_INIT;      
  920. break;
  922. default:
  923. // DbgPrintf("UE:G?D");
  924. EdbgOutputDebugString("[UE:G?D]rn");
  925. break;
  926. }
  927. }
  929. void ReconfigUsbd(void)
  930. {
  931. // *** End point information ***
  932. //   EP0: control
  933. //   EP1: bulk in end point
  934. //   EP2: not used
  935. //   EP3: bulk out end point
  936. //   EP4: not used
  937.     
  938. pUSBCtrlAddr->PMR.sus_en = 0;
  939. pUSBCtrlAddr->PMR.sus_mo = 0;
  940. pUSBCtrlAddr->PMR.muc_res = 0;
  941. pUSBCtrlAddr->PMR.usb_re = 0;
  942. pUSBCtrlAddr->PMR.iso_up = 0;
  944. pUSBCtrlAddr->INDEX.index = 0;
  945. pUSBCtrlAddr->MAXP.maxp = 0x01; //EP0 max packit size = 8 
  946. pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
  947. pUSBCtrlAddr->EP0ICSR1.sse_ = 1;
  948. //EP0:clear OUT_PKT_RDY & SETUP_END
  950. pUSBCtrlAddr->INDEX.index = 1;
  951. pUSBCtrlAddr->MAXP.maxp = 0x08; //EP1 max packit size = 64 
  952. pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
  953. pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
  954. pUSBCtrlAddr->ICSR2.mode_in = 1;
  955. pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
  956. pUSBCtrlAddr->ICSR2.iso = 0;
  957. pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
  958. pUSBCtrlAddr->OCSR2.iso = 0;
  959. pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
  961. pUSBCtrlAddr->INDEX.index = 2;
  962. pUSBCtrlAddr->MAXP.maxp = 0x08; //EP2 max packit size = 64 
  963. pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
  964. pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
  965. pUSBCtrlAddr->ICSR2.mode_in = 1;
  966. pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
  967. pUSBCtrlAddr->ICSR2.iso = 0;
  968. pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
  969. pUSBCtrlAddr->OCSR2.iso = 0;
  970. pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
  972. pUSBCtrlAddr->INDEX.index = 3;
  973. pUSBCtrlAddr->MAXP.maxp = 0x08; //EP3 max packit size = 64 
  974. pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
  975. pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
  976. pUSBCtrlAddr->ICSR2.mode_in = 0;
  977. pUSBCtrlAddr->ICSR2.in_dma_int_en = 0;
  978. pUSBCtrlAddr->ICSR2.iso = 0;
  979. pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
  980. //clear OUT_PKT_RDY, data_toggle_bit.
  981. //The data toggle bit should be cleared when initialization.
  982. pUSBCtrlAddr->OCSR2.iso = 0;
  983. pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
  985. pUSBCtrlAddr->INDEX.index = 4;
  986. pUSBCtrlAddr->MAXP.maxp = 0x08; //EP4 max packit size = 64 
  987. pUSBCtrlAddr->EP0ICSR1.de_ff = 1;
  988. pUSBCtrlAddr->EP0ICSR1.sopr_cdt = 1;
  989. pUSBCtrlAddr->ICSR2.mode_in = 0;
  990. pUSBCtrlAddr->ICSR2.in_dma_int_en = 1;
  991. pUSBCtrlAddr->ICSR2.iso = 0;
  992. pUSBCtrlAddr->OCSR1.clr_data_tog = 1;
  993. //clear OUT_PKT_RDY, data_toggle_bit.
  994. //The data toggle bit should be cleared when initialization.
  995. pUSBCtrlAddr->OCSR2.iso = 0;
  996. pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
  998. pUSBCtrlAddr->EIR.ep0_int=1;
  999. pUSBCtrlAddr->EIR.ep1_int=1;
  1000. pUSBCtrlAddr->EIR.ep2_int=1;
  1001. pUSBCtrlAddr->EIR.ep3_int=1;
  1002. pUSBCtrlAddr->EIR.ep4_int=1;
  1003. pUSBCtrlAddr->UIR.reset_int = 1;
  1004. pUSBCtrlAddr->UIR.sus_int = 1;
  1005. pUSBCtrlAddr->UIR.resume_int = 1;
  1007. //Clear all usbd pending bits
  1009. //EP0,1,3 & reset interrupt are enabled
  1010. pUSBCtrlAddr->EIER.ep0_int_en = 1;
  1011. pUSBCtrlAddr->EIER.ep1_int_en = 1;
  1012. pUSBCtrlAddr->EIER.ep3_int_en = 1;
  1014. pUSBCtrlAddr->UIER.reset_int_en = 1;
  1015. ep0State=EP0_STATE_INIT;
  1017. }
  1019. void Isr_Init(void)
  1020. {
  1021. volatile INTreg *s2440INT = (INTreg *)INT_BASE;
  1023. s2440INT->rINTMOD=0x0;   // All=IRQ mode
  1024. s2440INT->rINTMSK=BIT_ALLMSK;   // All interrupt is masked.
  1026. // EdbgOutputDebugString("INFO: (unsigned)IsrUsbd : 0x%xrn", (unsigned)IsrUsbd);
  1027. // EdbgOutputDebugString("INFO: (unsigned)IsrHandler : 0x%xrn", (unsigned)IsrHandler);
  1029. // make value to assemble code "b IsrHandler"
  1030. pISR =(unsigned)(0xEA000000)+(((unsigned)IsrHandler - (0x8c000000 + 0x18 + 0x8) )>>2);
  1032. s2440INT->rSRCPND  = BIT_USBD;
  1033. if (s2440INT->rINTPND & BIT_USBD) s2440INT->rINTPND = BIT_USBD;
  1034. s2440INT->rINTMSK &= ~BIT_USBD; // USB Interrupt enable.
  1036. s2440INT->rSRCPND  = BIT_DMA2;
  1037. if (s2440INT->rINTPND & BIT_DMA2) s2440INT->rINTPND = BIT_DMA2;
  1038. s2440INT->rINTMSK &= ~BIT_DMA2; // DMA Interrupt enable.
  1039. }
  1041. void IsrUsbd(unsigned int val)
  1042. {
  1043.     U8 saveIndexReg=pUSBCtrlAddr->INDEX.index;
  1044. volatile INTreg *s2440INT = (INTreg *)INT_BASE;
  1046. // EdbgOutputDebugString("INFO : IsrUsbd : Interrupt occurred rn");
  1048. if (s2440INT->rINTPND & BIT_DMA2)
  1049. {
  1050. DMA2Handler();
  1051. goto Exit;
  1052. }
  1054.     if(pUSBCtrlAddr->UIR.sus_int)
  1055.     {
  1056. pUSBCtrlAddr->UIR.sus_int = 1;
  1057. EdbgOutputDebugString("<SUS]rn");
  1058.     }
  1059.     if(pUSBCtrlAddr->UIR.resume_int)
  1060.     {
  1061. pUSBCtrlAddr->UIR.resume_int = 1;
  1062. EdbgOutputDebugString("<RSM]rn");
  1063.     }
  1064.     if(pUSBCtrlAddr->UIR.reset_int)
  1065.     {
  1066. EdbgOutputDebugString("<RSET]rn");
  1067.      ReconfigUsbd();
  1068. pUSBCtrlAddr->UIR.reset_int = 1;
  1069.         PrepareEp1Fifo(); 
  1070.     }
  1072.     if(pUSBCtrlAddr->EIR.ep0_int)
  1073.     {
  1074. EdbgOutputDebugString("EP0 Interruptrn");
  1075. pUSBCtrlAddr->EIR.ep0_int=1;
  1076.      Ep0Handler();
  1077.     }
  1078.     if(pUSBCtrlAddr->EIR.ep1_int)
  1079.     {
  1080. EdbgOutputDebugString("<1:TBD]rn");
  1081. pUSBCtrlAddr->EIR.ep1_int=1;
  1082.      Ep1Handler();
  1083.     }
  1085.     if(pUSBCtrlAddr->EIR.ep2_int)
  1086.     {
  1087. pUSBCtrlAddr->EIR.ep2_int=1;
  1088. EdbgOutputDebugString("<2:TBD]rn");
  1089.     }
  1091.     if(pUSBCtrlAddr->EIR.ep3_int)
  1092.     {
  1093.      Ep3Handler();
  1094. pUSBCtrlAddr->EIR.ep3_int=1;
  1095.     }
  1097.     if(pUSBCtrlAddr->EIR.ep4_int)
  1098.     {
  1099. pUSBCtrlAddr->EIR.ep4_int=1;
  1100. EdbgOutputDebugString("<4:TBD]rn");
  1101.     }
  1103. if (s2440INT->rINTPND & BIT_USBD)
  1104. {
  1105. s2440INT->rSRCPND  = BIT_USBD;
  1106. if (s2440INT->rINTPND & BIT_USBD) s2440INT->rINTPND = BIT_USBD;
  1107. }
  1109. Exit:
  1110.     pUSBCtrlAddr->INDEX.index=saveIndexReg;
  1111. }
  1113. void Ep3Handler(void)
  1114. {
  1115.     int fifoCnt;
  1116. volatile INTreg *s2440INT = (INTreg *)INT_BASE;
  1118.     pUSBCtrlAddr->INDEX.index=3;
  1120.     if(pUSBCtrlAddr->OCSR1.out_pkt_rdy)
  1121.     {
  1122. fifoCnt=pUSBCtrlAddr->OFCR1.out_cnt_low;
  1124. downPt = (LPBYTE)(downPtIndex);
  1125. RdPktEp3((U8 *)downPt,fifoCnt);
  1126. downPtIndex += 64;
  1127. s2440INT->rINTMSK |= BIT_USBD; // USB Interrupt disable.
  1128. return;
  1129.     }
  1131.     //I think that EPO_SENT_STALL will not be set to 1.
  1132.     if(pUSBCtrlAddr->OCSR1.sent_stall)
  1133.     {
  1134.     CLR_EP3_SENT_STALL();
  1135.     return;
  1136.     }
  1137. }
  1139. void DMA2Handler(void)
  1140. {
  1141. volatile INTreg *s2440INT = (INTreg *)INT_BASE;
  1142. volatile DMAreg *v_pDMAregs = (DMAreg *)DMA_BASE;
  1144. s2440INT->rSRCPND  = BIT_DMA2;
  1145. if (s2440INT->rINTPND & BIT_DMA2) s2440INT->rINTPND = BIT_DMA2;
  1147. downPtIndex += 0x80000;
  1149. v_pDMAregs->rDIDST2=((U32)downPtIndex+0x80000);
  1150. v_pDMAregs->rDIDSTC2=(1<<2)|(0<<1)|(0<<0);  
  1151. v_pDMAregs->rDCON2=v_pDMAregs->rDCON2&~(0xfffff)|(0x80000); 
  1153. while(rEP3_DMA_TTC<0xfffff)
  1154. {
  1155. pUSBCtrlAddr->EP3DTL.ep3_ttl_l = 0xff;
  1156. pUSBCtrlAddr->EP3DTM.ep3_ttl_m = 0xff;
  1157. pUSBCtrlAddr->EP3DTH.ep3_ttl_h = 0x0f;
  1158. }
  1159. }
  1161. void ConfigEp3DmaMode(U32 bufAddr,U32 count)
  1162. {
  1163. volatile INTreg *s2440INT = (INTreg *)INT_BASE;
  1164. volatile DMAreg *v_pDMAregs = (DMAreg *)DMA_BASE;
  1165. int i;
  1167. pUSBCtrlAddr->INDEX.index=3;
  1168. count=count&0xfffff; //transfer size should be <1MB
  1169. v_pDMAregs->rDISRCC2=(1<<1)|(1<<0);
  1170. v_pDMAregs->rDISRC2=REAL_PHYSICAL_ADDR_EP3_FIFO; //src=APB,fixed,src=EP3_FIFO
  1171. v_pDMAregs->rDIDSTC2=(0<<2)|(0<<1)|(0<<0);
  1172. v_pDMAregs->rDIDST2=bufAddr;       //dst=AHB,increase,dst=bufAddr
  1173. v_pDMAregs->rDCON2=(count)|(1<<31)|(0<<30)|(1<<29)|(0<<28)|(0<<27)|(4<<24)|(1<<23)|(0<<22)|(0<<20); 
  1174. //handshake,requestor=APB,CURR_TC int enable,unit transfer,
  1175. //single service,src=USBD,H/W request,autoreload,byte,CURR_TC
  1177. v_pDMAregs->rDMASKTRIG2 = (1<<1);
  1178. //DMA 2 on
  1180. pUSBCtrlAddr->EP3DTL.ep3_ttl_l = 0xff;
  1181. pUSBCtrlAddr->EP3DTM.ep3_ttl_m = 0xff;
  1182. pUSBCtrlAddr->EP3DTH.ep3_ttl_h = 0x0f;
  1184. pUSBCtrlAddr->OCSR2.auto_clr = 1;
  1185. pUSBCtrlAddr->OCSR2.out_dma_int_en = 1;
  1186. //AUTO_CLR(OUT_PKT_READY is cleared automatically), interrupt_masking.
  1187. pUSBCtrlAddr->EP3DU.ep3_unit_cnt = 1;
  1189. *(volatile BYTE *)&pUSBCtrlAddr->EP3DC=UDMA_OUT_DMA_RUN|UDMA_DMA_MODE_EN;
  1191. // deamnd disable,out_dma_run=run,in_dma_run=stop,DMA mode enable
  1192.     //wait until DMA_CON is effective.
  1193. *(volatile BYTE *)&pUSBCtrlAddr->EP3DC;
  1194. for(i=0;i<10;i++);
  1195. }
  1197. void ConfigEp3IntMode(void)
  1198. {
  1199. volatile DMAreg *v_pDMAregs = (DMAreg *)DMA_BASE;
  1200.     pUSBCtrlAddr->INDEX.index=3;
  1201.     
  1202.     v_pDMAregs->rDMASKTRIG2= (0<<1);  // EP3=DMA ch 2
  1203.         //DMA channel off
  1204. pUSBCtrlAddr->OCSR2.auto_clr = 0;
  1206. //AUTOCLEAR off,interrupt_enabled (???)
  1207. pUSBCtrlAddr->EP3DU.ep3_unit_cnt = 1;
  1208. *(volatile BYTE *)&pUSBCtrlAddr->EP3DC=0x0;
  1209.     //wait until DMA_CON is effective.
  1210.     *(volatile BYTE *)&pUSBCtrlAddr->EP3DC;
  1211. }
  1213. #pragma optimize ("",off)
  1214. BOOL UbootReadData(DWORD cbData, LPBYTE pbData)
  1215. {
  1216. volatile USBD_GLOBALS *usbdShMem = (USBD_GLOBALS *)(DRIVER_GLOBALS_PHYSICAL_MEMORY_START);
  1217. volatile INTreg *s2440INT = (INTreg *)INT_BASE;
  1218. volatile DMAreg *v_pDMAregs = (DMAreg *)DMA_BASE;
  1219. unsigned int temp;
  1220. int i;
  1222. Loop:
  1223. if ( downPtIndex > readPtIndex + cbData )
  1224. {
  1225. memcpy(pbData, readPtIndex, cbData);
  1226. readPtIndex += cbData;
  1227. }
  1228. else if (downPtIndex == DMABUFFER)
  1229. {
  1230. while (downPtIndex == DMABUFFER) {}; // first 64 bytes, get interrupt mode.
  1232. if ( readPtIndex == DMABUFFER )
  1233. {
  1234. memcpy(pbData, readPtIndex, cbData);
  1235. readPtIndex += cbData;
  1236. }
  1238. s2440INT->rSRCPND  = BIT_USBD;
  1239. if (s2440INT->rINTPND & BIT_USBD) s2440INT->rINTPND = BIT_USBD;
  1240. s2440INT->rINTMSK |= BIT_USBD; // USB Interrupt disable.
  1242. // read data with DMA operation.
  1243. s2440INT->rSRCPND  = BIT_DMA2;
  1244. if (s2440INT->rINTPND & BIT_DMA2) s2440INT->rINTPND = BIT_DMA2;
  1245. s2440INT->rINTMSK &= ~BIT_DMA2; // DMA Interrupt enable.
  1247. pUSBCtrlAddr->INDEX.index=3;
  1248. CLR_EP3_OUT_PKT_READY();
  1250. ConfigEp3DmaMode(downPtIndex,0x80000);
  1252. v_pDMAregs->rDIDST2=(downPtIndex+0x80000); //for 1st autoreload.
  1253. v_pDMAregs->rDIDSTC2=(1<<2)|(0<<1)|(0<<0);
  1254. v_pDMAregs->rDCON2=v_pDMAregs->rDCON2&~(0xfffff)|(0x80000);
  1256. while(rEP3_DMA_TTC<0xfffff)
  1257. {
  1258. pUSBCtrlAddr->EP3DTL.ep3_ttl_l = 0xff;
  1259. pUSBCtrlAddr->EP3DTM.ep3_ttl_m = 0xff;
  1260. pUSBCtrlAddr->EP3DTH.ep3_ttl_h = 0x0f;
  1261. }
  1262. }
  1263. else
  1264. {
  1265. temp = rEP3_DMA_TTC;
  1266. for (i = 0; i < 60000; i++ )
  1267. {
  1268. }
  1269. if ( temp == rEP3_DMA_TTC )
  1270. {
  1271. EdbgOutputDebugString("INFO : UbootReadData : downPtIndex(0x%x) - readPtIndex(0x%x) = 0x%xrn", downPtIndex, readPtIndex, downPtIndex - readPtIndex);
  1272. downPtIndex += ((unsigned int)0xfffff - (unsigned int)rEP3_DMA_TTC);
  1273. EdbgOutputDebugString("INFO : UbootReadData : rEP3_DMA_TTC = 0x%xrn", rEP3_DMA_TTC);
  1274. }
  1276. goto Loop;
  1277. }
  1279. return TRUE;
  1280. }
  1281. #pragma optimize ("",on)