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sh4.inc
资源名称：SMDK2440.rar [点击查看]
上传用户：qiulin1960
上传日期：2013-10-16
资源大小：2844k
文件大小：7k
源码类别：
Windows CE
开发平台：
Windows_Unix
- ;*****************************************************************
- ; P2 MP T/M HEADER Ver1.0
- ; SH-4 CPU SIMULATION
- ; Copyright (c) 1999-2000 Microsoft Corporation. All rights reserved.
- ;:****************************************************************
- .list OFF
- ;********************************************
- ; DIFINE CONTROL REGISTER
- ;********************************************
- ;CCN address Sz
- CCN_PTEH .equ h'FF000000 ;32
- CCN_PTEL .equ h'FF000004 ;32
- CCN_TTB .equ h'FF000008 ;32
- CCN_TEA .equ h'FF00000C ;32
- CCN_MMUCR .equ h'FF000010 ;32
- CCN_BASRA .equ h'FF000014 ;8
- CCN_BASRB .equ h'FF000018 ;8
- CCN_TRA .equ h'FF000020 ;32
- CCN_EXPEVT .equ h'FF000024 ;32
- CCN_INTEVT .equ h'FF000028 ;32
- CCN_PTEA .equ h'FF000034 ;32
- CCN_QACR0 .equ h'FF000038 ;32
- CCN_QACR1 .equ h'FF00003C ;32
- CCN_CCR .equ h'FF00001C ;32
- CCN_CCR_IIX .equ h'00008000 ; 1 = Addr (12:5) used as IC index
- ; 0 = Addr (25)(11:5) used as IC index
- CCN_CCR_ICI .equ h'00000800 ; 1 = IC invalidation
- CCN_CCR_ICE .equ h'00000100 ; 1 = IC used; 0 = IC not used
- CCN_CCR_OIX .equ h'00000080 ; 1 = Addr (13:5) used as 0C index
- ; 0 = Addr (25)(12:5) used as 0C index
- CCN_CCR_ORA .equ h'00000020 ; 1 = 8 kbytes used as cache, 8 kbytes as RAM
- ; 0 = 16 kbytes used as cache
- CCN_CCR_OCI .equ h'00000008 ; 1 = OC invalidatiob
- CCN_CCR_CB .equ h'00000004 ; 1 = Copy-Back ; 0 = Write-through mode P1 area cache
- CCN_CCR_WT .equ h'00000002 ; 1 = Write-through ; 0 = Copy-Back mode P0, U0, P1 area cache
- CCN_CCR_OCE .equ h'00000001 ; 1 = OC used ; 0 = OC not used
- ;UBC
- UBC_BARA .equ h'FF200000 ;32
- UBC_BAMRA .equ h'FF200004 ;8
- UBC_BBRA .equ h'FF200008 ;16
- UBC_BARB .equ h'FF20000C ;32
- UBC_BAMRB .equ h'FF200010 ;8
- UBC_BBRB .equ h'FF200014 ;16
- UBC_BDRB .equ h'FF200018 ;32
- UBC_BDMRB .equ h'FF20001C ;32
- UBC_BRCR .equ h'FF200020 ;16
- ;CPG
- CPG_FRQCR .equ h'FFC00000 ;16
- CPG_STBCR .equ h'FFC00004 ;8
- CPG_WTCNT .equ h'FFC00008 ;8
- CPG_WTCSR .equ h'FFC0000C ;8
- ;BCN
- BCN_BCR1 .equ h'FF800000 ;32
- BCN_BCR2 .equ h'FF800004 ;16
- BCN_WCR1 .equ h'FF800008 ;32
- BCN_WCR2 .equ h'FF80000C ;32
- BCN_WCR3 .equ h'FF800010 ;32
- BCN_MCR .equ h'FF800014 ;32
- BCN_PCR .equ h'FF800018 ;16
- BCN_RTCSR .equ h'FF80001C ;16
- BCN_RTCNT .equ h'FF800020 ;16
- BCN_RTCOR .equ h'FF800024 ;16
- BCN_RFCR .equ h'FF800028 ;16
- BCN_PCTR .equ h'FF80002C ;32
- BCN_PDTR .equ h'FF800030 ;16
- BCN_SDMR2 .equ h'FF900000 ;8
- BCN_SDMR3 .equ h'FF940000 ;8
- ;RTC
- RTC_BASE .equ h'FFC80000
- RTC_64CNT .equ h'0000 ;8
- RTC_SECCNT .equ h'0004 ;8
- RTC_MINCNT .equ h'0008 ;8
- RTC_HRCNT .equ h'000C ;8
- RTC_WKCNT .equ h'0010 ;8
- RTC_DAYCNT .equ h'0014 ;8
- RTC_MONCNT .equ h'0018 ;8
- RTC_YRCNT .equ h'001C ;16
- RTC_SECAR .equ h'0020 ;8
- RTC_MINAR .equ h'0024 ;8
- RTC_HRAR .equ h'0028 ;8
- RTC_WKAR .equ h'002C ;8
- RTC_DAYAR .equ h'0030 ;8
- RTC_MONAR .equ h'0034 ;8
- RTC_CR1 .equ h'0038 ;8
- RTC_CR2 .equ h'003C ;8
- ;INTC
- INTC_ICR .equ h'FFD00000 ;16
- INTC_IPRA .equ h'FFD00004 ;16
- INTC_IPRB .equ h'FFD00008 ;16
- INTC_IPRC .equ h'FFD0000C ;16
- ;TMU
- TMU_BASE .equ h'FFD80000
- TMU_OCR .equ h'0000 ;8
- TMU_STR .equ h'0004 ;8
- TMU_COR0 .equ h'0008 ;32
- TMU_CNT0 .equ h'000C ;32
- TMU_CR0 .equ h'0010 ;16
- TMU_COR1 .equ h'0014 ;32
- TMU_CNT1 .equ h'0018 ;32
- TMU_CR1 .equ h'001C ;16
- TMU_COR2 .equ h'0020 ;32
- TMU_CNT2 .equ h'0024 ;32
- TMU_CR2 .equ h'0028 ;16
- TMU_CPR2 .equ h'002C ;32
- TMU_START0: .equ h'01
- TMU_START1: .equ h'02
- TMU_START2: .equ h'04
- TMUCR_UNF: .equ h'100 ; counter underflowed
- TMUCR_UNIE: .equ h'20 ; underflow interrupt enable
- TMUCR_RISE: .equ h'00 ; count on rising edge of clock
- TMUCR_FALL: .equ h'08 ; count on falling edge of clock
- TMUCR_BOTH: .equ h'10 ; count on both edges of clock
- TMUCR_D4: .equ h'00 ; PERIPHERAL clock / 4
- TMUCR_D16: .equ h'01 ; PERIPHERAL clock / 16
- TMUCR_D64: .equ h'02 ; PERIPHERAL clock / 64
- TMUCR_D256: .equ h'03 ; PERIPHERAL clock / 256
- TMUCR_D1024: .equ h'04 ; PERIPHERAL clock / 1024
- TMUCR_RESVD: .equ h'05 ; Reserved (cannot be set)
- TMUCR_RTC: .equ h'06 ; real time clock output (16 kHz)
- TMUCR_EXT: .equ h'07 ; external clock input
- ;DMAC
- DMAC_SAR0 .equ h'FFA00000 ;32
- DMAC_DAR0 .equ h'FFA00004 ;32
- DMAC_DMATCR0 .equ h'FFA00008 ;32
- DMAC_CHCR0 .equ h'FFA0000C ;32
- DMAC_SAR1 .equ h'FFA00010 ;32
- DMAC_DAR1 .equ h'FFA00014 ;32
- DMAC_DMATCR1 .equ h'FFA00018 ;32
- DMAC_CHCR1 .equ h'FFA0001C ;32
- DMAC_SAR2 .equ h'FFA00020 ;32
- DMAC_DAR2 .equ h'FFA00024 ;32
- DMAC_DMATCR2 .equ h'FFA00028 ;32
- DMAC_CHCR2 .equ h'FFA0002C ;32
- DMAC_SAR3 .equ h'FFA00030 ;32
- DMAC_DAR3 .equ h'FFA00034 ;32
- DMAC_DMATCR3 .equ h'FFA00038 ;32
- DMAC_CHCR3 .equ h'FFA0003C ;32
- DMAC_DMAOR .equ h'FFA00040 ;32
- ;SCI
- SCI_SCSMR1 .equ h'FFE00000 ;8
- SCI_SCBRR1 .equ h'FFE00004 ;8
- SCI_SCSCR1 .equ h'FFE00008 ;8
- SCI_SCTDR1 .equ h'FFE0000C ;8
- SCI_SCSSR1 .equ h'FFE00010 ;8
- SCI_SCRDR1 .equ h'FFE00014 ;8
- SCI_SCSCMR1 .equ h'FFE00018 ;8
- SCI_SCSPTR1 .equ h'FFE0001C ;8
- SCI_SCSMR2 .equ h'FFE80000 ;16
- SCI_SCBRR2 .equ h'FFE80004 ;8
- SCI_SCSCR2 .equ h'FFE80008 ;16
- SCI_SCFTDR2 .equ h'FFE8000C ;8
- SCI_SCFSR2 .equ h'FFE80010 ;16
- SCI_SCFRDR2 .equ h'FFE80014 ;8
- SCI_SCFCR2 .equ h'FFE80018 ;16
- SCI_SCFDR2 .equ h'FFE8001C ;16
- SCI_SCSPTR2 .equ h'FFE80020 ;16
- SCI_SCLSR2 .equ h'FFE80024 ;16
- ;EMU
- EMU_SDIR .equ h'FFF00000 ;16
- EMU_SDDR .equ h'FFF00008 ;32
- .list ON
