mmumacro.s
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Windows CE

开发平台:

Windows_Unix

  1. ;
  2. ; Copyright (c) 2001. Samsung Electronics, co. ltd  All rights reserved.
  3. ;
  4. ;
  5. ; Use of this source code is subject to the terms of the Microsoft end-user
  6. ; license agreement (EULA) under which you licensed this SOFTWARE PRODUCT.
  7. ; If you did not accept the terms of the EULA, you are not authorized to use
  8. ; this source code. For a copy of the EULA, please see the LICENSE.RTF on your
  9. ; install media.
  10. ;
  11. ; -*-Asm-*-
  12. ;
  13. ; $Revision: 1.2 $
  14. ;   $Author: kwelton $
  15. ;     $Date: 1999/10/25 21:40:55 $
  16. ;
  17. ; Copyright (c) ARM Limited 1998, 1999.
  18. ; All Rights Reserved.
  19. ;
  20. ; mmumacro.s - Generic aliases for COPROCESSOR access macros for
  21. ;              ARM processors.
  22. ;
  23. ; $Id: mmumacro.s,v 1.2 1999/10/25 21:40:55 kwelton Exp $
  24. ;
  25.  IF :LNOT: :DEF: __mmumacros
  26. __mmumacros             EQU     1
  27. ; Bit definitions are here
  28. INCLUDE mmu_h.s
  29. ; Dummy macros for processors without MMU/MPU etc.
  30. INCLUDE nommu.s
  31. ; NOTE: Most (all?) macros call the NO_* macro first. These macros must
  32. ; be non-destructive on passed parameters, as one (or more) of
  33. ; the processor-specific macros may be called next.
  34.  IF FORCE_TGTCPU = "ARM7"
  35. INCLUDE mmu7T.s
  36.  ENDIF
  37.  IF FORCE_TGTCPU = "ARM720"
  38. INCLUDE mmu720T.s
  39.  ENDIF
  40.  IF FORCE_TGTCPU = "ARM740"
  41. INCLUDE mmu740T.s
  42.  ENDIF
  43.  IF FORCE_TGTCPU = "ARM920"
  44. INCLUDE mmu920T.s
  45.  ENDIF
  46.  IF FORCE_TGTCPU = "ARM940"
  47. INCLUDE mmu940T.s
  48.  ENDIF
  49.  IF FORCE_TGTCPU = "SA110"
  50. INCLUDE mmu110.s
  51.  ENDIF
  52. ;------------------------------------------------------------------
  53. ;Macro to test that the given address has a 1-to-1 mapping between
  54. ;physical and virtual memory
  55. MACRO
  56. TEST_121MAP $addr, $tmp1, $tmp2
  57. RDMMU_TTBase $tmp1
  58. MOV $tmp1, $tmp1, LSR #14 ; Clear bottom 14 bits
  59. MOV $tmp1, $tmp1, LSL #14
  60. ADD $tmp2, $tmp1, $addr, LSR #(20-2) ; page table entry
  61. LDR $tmp1, [$tmp2] ; read the entry
  62. MOV $tmp2, $addr, LSR #20 ; addr in MB
  63. SUBS $tmp2, $tmp2, $tmp1, LSR #20 ; entry in
  64. MEND
  65. ;------------------------------------------------------------------
  66. ; For executables which are linked for a different address to the
  67. ; physically executed address:
  68. ;
  69. ; Need to adjust from the linked address of the table to a relative
  70. ; offset from here. First, work out the offset from the RO$$Base,
  71. ; then find out how far we are from our actual start. Lastly, add
  72. ; the difference to the current pc.
  73. MACRO
  74. FIND_TABLEADDR $tmp3, $tmp4, $addr
  75.         LDR $tmp4, =|Image$$RO$$Base| ; get linked location of code
  76. SUB $addr, $addr, $tmp4   ; A. table offset from start
  77.         LDR $tmp3, =%F79
  78. SUB $tmp3, $tmp3, $tmp4   ; B. Offset to next label
  79. SUB $addr, $addr, $tmp3   ; A-B
  80. ; ----------------------------------------------------
  81. ; Note: no more than 2 instructions between here and
  82. ; the label.  Since pc is here + 8, add A-B to get
  83. ; current table address
  84. MOV $tmp3, pc
  85. ADD $addr, $addr, $tmp3
  86. 79
  87. MEND
  88. ; Macro to read the MPU MappingTable and build the region, cache, buffer
  89. ; and permissions before setting up the MPU as required
  90. ;
  91. MACRO
  92. SETUP_MPU $tmp1, $size, $tmp2, $tmp3, $tmp4, $addr, $offset
  93.  IF :LNOT: :DEF: MPUMaptab
  94. IMPORT MPUMaptab
  95.  ENDIF
  96. ; Flush MPU Map to invalid
  97. LDR $tmp2, =MPUMaptab
  98. ADD $tmp1, $tmp2, $offset ; Real address of Level1 TTB
  99. MOV $tmp3, #0 ; Invalid
  100. LDR $tmp4, =MPU_TABLE_ENTRIES
  101. 70
  102. STR $tmp3, [$tmp1], #4
  103. SUBS $tmp4, $tmp4, #1 ; decrement loop count
  104. BNE %B70
  105. ; If not executing from linked address, adjust $addr
  106. FIND_TABLEADDR $tmp3, $tmp4, $addr
  107. ADD $tmp1, $tmp2, $offset ; Real address of Mapping Table
  108. 71
  109. LDR $offset, [$addr], #4 ; Read the region
  110. LDR $tmp2, [$addr], #4 ; Base address
  111. LDR $tmp3, [$addr], #4 ; Area size
  112. CMP $tmp3, #0 ; All done if size is zero
  113. BEQ %F74
  114. ; Make sure address is correctly aligned (a multiple of size)
  115. MOV $tmp4, #2
  116. MOV $tmp4, $tmp4, LSL $tmp3
  117. SUB $tmp4, $tmp4, #1
  118. ANDS $tmp4, $tmp2, $tmp4
  119. BNE %F80 ; Failed, stop.
  120. ; Build the region value, strip bottom 12 bits
  121. MOV $tmp3, $tmp3, LSL #1 ; Size is used x 2
  122. MOV $tmp2, $tmp2, LSR #12
  123. MOV $tmp2, $tmp2, LSL #12
  124. ADD $tmp2, $tmp2, $tmp3 ; Add in size
  125. ADD $tmp2, $tmp2, #1 ; Enable this region
  126. MOV $tmp3, $offset, LSL #2 ; Sotre in region * 4
  127. STR $tmp2, [$tmp1, $tmp3] ; Save the region base address
  128. ; Now add in access permissions for cache etc.
  129. LDR $tmp4, [$addr], #4 ; Access permissions
  130. MOV $tmp4, $tmp4, LSR #2 ; Access >> 2
  131. AND $tmp3, $tmp4, #1
  132. MOV $tmp2, $tmp3, LSL $offset
  133. LDR $tmp3, [$tmp1, #MPU_BUFFER_OFFSET]
  134. ORR $tmp2, $tmp2, $tmp3
  135. STR $tmp2, [$tmp1, #MPU_BUFFER_OFFSET]
  136. MOV $tmp4, $tmp4, LSR #1 ; Access >> 3
  137. AND $tmp3, $tmp4, #1
  138. MOV $tmp2, $tmp3, LSL $offset
  139. LDR $tmp3, [$tmp1, #MPU_CACHE_OFFSET]
  140. ORR $tmp2, $tmp2, $tmp3
  141. STR $tmp2, [$tmp1, #MPU_CACHE_OFFSET]
  142. MOV $tmp4, $tmp4, LSR #7 ; Access >> 10
  143. AND $tmp3, $tmp4, #3
  144. MOV $tmp3, $tmp3, LSL $offset
  145. MOV $tmp2, $tmp3, LSL $offset ; region x 2
  146. LDR $tmp3, [$tmp1, #MPU_ACCESS_OFFSET]
  147. ORR $tmp2, $tmp2, $tmp3
  148. STR $tmp2, [$tmp1, #MPU_ACCESS_OFFSET]
  149. B %B71 ; Next..
  150. 72 ; MPU Mapping Table failure..
  151. B .
  152. 74
  153. ; The table is built, so now write the values to the MPU
  154. LDR $tmp2, [$tmp1], #4
  155. WRMPU_Region 0, $tmp2
  156. LDR $tmp2, [$tmp1], #4
  157. WRMPU_Region 1, $tmp2
  158. LDR $tmp2, [$tmp1], #4
  159. WRMPU_Region 2, $tmp2
  160. LDR $tmp2, [$tmp1], #4
  161. WRMPU_Region 3, $tmp2
  162. LDR $tmp2, [$tmp1], #4
  163. WRMPU_Region 4, $tmp2
  164. LDR $tmp2, [$tmp1], #4
  165. WRMPU_Region 5, $tmp2
  166. LDR $tmp2, [$tmp1], #4
  167. WRMPU_Region 6, $tmp2
  168. LDR $tmp2, [$tmp1], #4
  169. WRMPU_Region 7, $tmp2
  170. LDR $tmp2, [$tmp1], #4
  171. WRMPU_CacheBits $tmp2
  172. LDR $tmp2, [$tmp1], #4
  173. WRMPU_BufferBits $tmp2
  174. LDR $tmp2, [$tmp1]
  175. WRMPU_AccessBits $tmp2
  176. MEND
  177. ; Simple macro to clear all page table entries.
  178. ;
  179. MACRO
  180. $label  INIT_PGTABLE $count, $val, $ptr, $offset
  181. LDR $ptr, =Level2tab_ROM
  182. ADD $ptr, $ptr, $offset ; Real address of Level2 TTB
  183. LDR $count, =L2_TABLE_ENTRIES
  184. CMP $count, #0 ; Check for no Level2 table
  185. BEQ %F77
  186. LDR $val, =L2_ENTRY_SIZE
  187. MUL $count, $val, $count
  188. MOV $val, #0 ; Invalid
  189. 76
  190. STR $val, [$ptr], #4
  191. SUBS $count, $count, #1 ; decrement loop count
  192. BGE %B76
  193. 77
  194. LDR $ptr, =Level1tab
  195. ADD $ptr, $ptr, $offset ; Real address of Level1 TTB
  196. MOV $val, #0 ; Invalid
  197. LDR $count, =L1_TABLE_ENTRIES
  198. 78
  199. STR $val, [$ptr], #4
  200. SUBS $count, $count, #1 ; decrement loop count
  201. BGE %B78
  202. MEND
  203. ; Build a page table from the supplied address map table.
  204. ;
  205. ; $tmp2 size of memory If this platform supports auto-memory sizing
  206. ; $addr pointer to memory map table
  207. ; $offset offset between physical addr & virtual addr of TTBs
  208. ;
  209. MACRO
  210. $label  BUILD_PGTABLE $tmp1, $tmp2, $tmp3, $tmp4, $tmp5, $addr, $offset
  211. ; ----------------------------------------------------
  212. ; First clear all TT entries - FAULT
  213. ; ----------------------------------------------------
  214. INIT_PGTABLE $tmp3, $tmp4, $tmp5, $offset
  215. ; If not executing from linked address, adjust $addr
  216. FIND_TABLEADDR $tmp3, $tmp4, $addr
  217. ; ----------------------------------------------------
  218. ; Check $size parameter.
  219. ; If non-zero, size of first memory area is taken from
  220. ; target-specific memory sizing code rather than $size
  221. CMP $tmp2, #0
  222. BEQ %F81 ; Not autosizing, read all params
  223. ; ----------------------------------------------------
  224. ; Make sure given memory size is a multiple of 1MB
  225. ; tmp3 is no. of 1MB segments
  226. MOV $tmp3, $tmp2, LSR #20
  227. MOV $tmp4, $tmp3, LSL #20
  228. CMP $tmp4, $tmp2
  229. ADDNE $tmp3, $tmp3, #1
  230. ; Read 1st Entry from MMU table seperately to allow
  231. ; memory sizing.
  232. ; NOTE: 1st entry cannot abort & can't be Level2 !!
  233. LDR $tmp4, =Level1tab
  234. ADD $tmp4, $tmp4, $offset
  235. ; Virtual base address -> Level1 offset in tmp2
  236. LDR $tmp5, [$addr], #4
  237. ADD $tmp2, $tmp4, $tmp5, LSR #(20-2)
  238. ; Physical base address -> tmp4
  239. LDR $tmp1, [$addr], #4
  240. ; Access permissions etc -> tmp3 (NOTE: Size is skipped!)
  241. LDR $tmp5, [$addr], #8
  242. CMP $tmp5, #0
  243. BEQ %F80 ; Halt if access is zero
  244. TST $tmp1, #PT_PAGE
  245. BNE %F80 ; Halt if Level2 table
  246. ADD $tmp1, $tmp1, $tmp5 ; Level1 Table Entry
  247. ; Registers set, so build 1st entry & rest of TLB.
  248. B %F83
  249. ; All causes for error end up here
  250. 80
  251.  IF FORCE_TGTCPU = "ARM7"
  252. B %F90 ; No Page Table if no MMU
  253.  ENDIF
  254. B .
  255. 81
  256. LDR $tmp4, =Level1tab
  257. ADD $tmp4, $tmp4, $offset
  258. 82
  259. ; Calculate offset to virtual base address entry -> tmp2
  260. LDR $tmp1, [$addr], #4 ; Virtual address
  261. ADD $tmp2, $tmp4, $tmp1, LSR #(20-2)
  262. ; Physical base address -> tmp1
  263. LDR $tmp1, [$addr], #4
  264. ; Access permissions etc -> tmp3
  265. LDR $tmp3, [$addr], #4
  266. CMP $tmp3, #0 ; All done if access is zero
  267. BEQ %F90
  268. TST $tmp1, #PT_PAGE ; Check for Level2 table
  269. BNE %F84 ; Yes, do it
  270. ; ----------------------------------------------------
  271. ; Level 1 Entries, calculate size & fill table
  272. ; ----------------------------------------------------
  273. ADD $tmp1, $tmp1, $tmp3 ; Level1 Table Entry
  274. LDR $tmp3, [$addr], #4 ; area size
  275. MOV $tmp3, $tmp3, LSR #20 ; no. of 1MB segments
  276. 83
  277. STR $tmp1, [$tmp2], #4 ; store Table Entry
  278. ADD $tmp1, $tmp1, #SZ_1M ; add section number field
  279. SUBS $tmp3, $tmp3, #1 ; decrement loop count
  280. BGT %B83
  281. B %B82 ; Repeat until done
  282. 84
  283. ; Convert logical addresses to real addresses
  284. ADD $tmp1, $tmp1, $offset ; Pointer to Level2 table
  285. ; ----------------------------------------------------
  286. ; Check for Fine table and process seperately
  287. ; ----------------------------------------------------
  288. TST $tmp3, #(PT_FINE - PT_PAGE)
  289. ; Read size!
  290. LDR $tmp5, [$addr], #4
  291. BIC $tmp4, $tmp1, #0x0ff
  292. BNE %F87
  293. ; ----------------------------------------------------
  294. ; Large Level2: Strip address of Level2 Table -> tmp4
  295. ; ----------------------------------------------------
  296. BIC $tmp4, $tmp4, #0x0300
  297. MOV $tmp5, $tmp5, LSR #16 ; no. of 64KB segments
  298. MOV $tmp5, $tmp5, LSL #4 ; no. of 4KB aliases
  299. 85
  300. STR $tmp1, [$tmp2], #4 ; Level1 points to Level2 entry
  301. 86
  302. ; Add each entry aliased 16 times (64KB/4KB, so $tmp3 & 0xF == 0)
  303. STR $tmp3, [$tmp4], #4 ; store large L2 TT entry
  304. SUB $tmp5, $tmp5, #1 ; decrement page count
  305. TST $tmp5, #0xF
  306. BNE %B86 ; upto 16 L2 entries
  307. ; Add 16 L2 entries per L1 entry  (1MB/64KB, so $tmp3 & 0xF0 == 0)
  308. ADD $tmp3, $tmp3, #SZ_64K ; next page field
  309. TST $tmp5, #0xf0
  310. BNE %B86 ; upto 16 L2 entries
  311. CMP $tmp5, #0 ; All done?
  312. ADD $tmp1, $tmp1, #0x400 ; Next 1MB is 256 entries further down
  313. BNE %B85 ; No, do another L1 entry.
  314. B %B81
  315. 87
  316. ; ----------------------------------------------------
  317. ; Fine Level2: Strip address of Level2 Table -> tmp4
  318. ; ----------------------------------------------------
  319. BIC $tmp4, $tmp4, #0x0f00
  320. MOV $tmp5, $tmp5, LSR #16 ; no. of 64KB segments
  321. MOVEQ $tmp5, $tmp5, LSL #8 ; no. of 1KB aliases
  322. MOVNE $tmp5, $tmp5, LSL #4 ; no. of 4KB aliases
  323. 88
  324. STR $tmp1, [$tmp2], #4 ; Level1 points to Level2 entry
  325. 89
  326. STR $tmp3, [$tmp4], #4 ; store fine L2 TT entry
  327. SUBS $tmp5, $tmp5, #1 ; decrement page count
  328. ADD $tmp3, $tmp3, #SZ_1K ; next page field
  329. TST $tmp5, #0x0ff
  330. BNE %B89 ; 4 x 256 L2 entries
  331. TST $tmp5, #0x300
  332. BNE %B89 ; 3ff won't fit inside an instruction
  333. CMP $tmp5, #0 ; All done?
  334. ADD $tmp1, $tmp1, #0x4000 ; Next 1MB is 1K entries further down
  335. BNE %B88 ; No, do another L1 entry.
  336. B %B81
  337. 90
  338. MEND
  339. ;------------------------------------------------------------------
  340. ; Compulsory Macros:
  341. ;
  342. ; These are the macros which must be defined, even for processors
  343. ; without any memory management capabilities.
  344. ;
  345. ; CHECK_FOR_MMU - return TRUE if CPU has an MMU
  346. ; CHECK_FOR_MPU - return TRUE if CPU has an MPU
  347. ; CHECK_CACHE - return TRUE if CPU has a Cache
  348. ; CHECK_UNIFIED - return TRUE if CPU has a Unified Cache
  349. ; CHECK_CPUID - return TRUE if CPU matches the expected ID
  350. ; CHECK_VENDOR - return TRUE if CPU matches the expected Vendor ID
  351. MACRO
  352. CHECK_FOR_MMU $reg
  353. NO_CHECK_FOR_MMU $reg
  354.  IF FORCE_TGTCPU = "ARM7"
  355. CHECK_FOR_MMU_7T $reg
  356.  ENDIF
  357.  IF FORCE_TGTCPU = "ARM720"
  358. CHECK_FOR_MMU_720T $reg
  359.  ENDIF
  360.  IF FORCE_TGTCPU = "ARM740"
  361. CHECK_FOR_MMU_740T $reg
  362.  ENDIF
  363.  IF FORCE_TGTCPU = "ARM920"
  364. CHECK_FOR_MMU_920T $reg
  365.  ENDIF
  366.  IF FORCE_TGTCPU = "ARM940"
  367. CHECK_FOR_MMU_940T $reg
  368.  ENDIF
  369.  IF FORCE_TGTCPU = "SA110"
  370. CHECK_FOR_MMU_110 $reg
  371.  ENDIF
  372. MEND
  373. ;Macro to signal if this processor has an MPU
  374. ;
  375. MACRO
  376. CHECK_FOR_MPU $reg
  377. NO_CHECK_FOR_MPU $reg
  378.  IF FORCE_TGTCPU = "ARM7"
  379. CHECK_FOR_MPU_7T $reg
  380.  ENDIF
  381.  IF FORCE_TGTCPU = "ARM720"
  382. CHECK_FOR_MPU_720T $reg
  383.  ENDIF
  384.  IF FORCE_TGTCPU = "ARM740"
  385. CHECK_FOR_MPU_740T $reg
  386.  ENDIF
  387.  IF FORCE_TGTCPU = "ARM920"
  388. CHECK_FOR_MPU_920T $reg
  389.  ENDIF
  390.  IF FORCE_TGTCPU = "ARM940"
  391. CHECK_FOR_MPU_940T $reg
  392.  ENDIF
  393.  IF FORCE_TGTCPU = "SA110"
  394. CHECK_FOR_MPU_110 $reg
  395.  ENDIF
  396. MEND
  397. ;Macro to signal if this processor has a Cache
  398. ;
  399. MACRO
  400. CHECK_CACHE $reg
  401. NO_CHECK_CACHE $reg
  402.  IF FORCE_TGTCPU = "ARM7"
  403. CHECK_CACHE_7T $reg
  404.  ENDIF
  405.  IF FORCE_TGTCPU = "ARM720"
  406. CHECK_CACHE_720T $reg
  407.  ENDIF
  408.  IF FORCE_TGTCPU = "ARM740"
  409. CHECK_CACHE_740T $reg
  410.  ENDIF
  411.  IF FORCE_TGTCPU = "ARM920"
  412. CHECK_CACHE_920T $reg
  413.  ENDIF
  414.  IF FORCE_TGTCPU = "ARM940"
  415. CHECK_CACHE_940T $reg
  416.  ENDIF
  417.  IF FORCE_TGTCPU = "SA110"
  418. CHECK_CACHE_110 $reg
  419.  ENDIF
  420. MEND
  421. ;Macro to signal if this processor has a unified cache
  422. ;
  423. MACRO
  424. CHECK_UNIFIED $reg
  425. NO_CHECK_UNIFIED $reg
  426.  IF FORCE_TGTCPU = "ARM7"
  427. CHECK_UNIFIED_7T $reg
  428.  ENDIF
  429.  IF FORCE_TGTCPU = "ARM720"
  430. CHECK_UNIFIED_720T $reg
  431.  ENDIF
  432.  IF FORCE_TGTCPU = "ARM740"
  433. CHECK_UNIFIED_740T $reg
  434.  ENDIF
  435.  IF FORCE_TGTCPU = "ARM920"
  436. CHECK_UNIFIED_920T $reg
  437.  ENDIF
  438.  IF FORCE_TGTCPU = "ARM940"
  439. CHECK_UNIFIED_940T $reg
  440.  ENDIF
  441.  IF FORCE_TGTCPU = "SA110"
  442. CHECK_UNIFIED_110 $reg
  443.  ENDIF
  444. MEND
  445. MACRO
  446. CHECK_CPUID $reg, $ret
  447. NO_CHECK_CPUID $reg, $ret
  448.  IF FORCE_TGTCPU = "ARM7"
  449. CHECK_CPUID_7T $reg, $ret
  450.  ENDIF
  451.  IF FORCE_TGTCPU = "ARM720"
  452. CHECK_CPUID_720T $reg, $ret
  453.  ENDIF
  454.  IF FORCE_TGTCPU = "ARM740"
  455. CHECK_CPUID_740T $reg, $ret
  456.  ENDIF
  457.  IF FORCE_TGTCPU = "ARM920"
  458. CHECK_CPUID_920T $reg, $ret
  459.  ENDIF
  460.  IF FORCE_TGTCPU = "ARM940"
  461. CHECK_CPUID_940T $reg, $ret
  462.  ENDIF
  463.  IF FORCE_TGTCPU = "SA110"
  464. CHECK_CPUID_110 $reg, $ret
  465.  ENDIF
  466. MEND
  467. MACRO
  468. CHECK_VENDOR $reg, $ret
  469. NO_CHECK_VENDOR $reg, $ret
  470.  IF FORCE_TGTCPU = "ARM7"
  471. CHECK_VENDOR_7T $reg, $ret
  472.  ENDIF
  473.  IF FORCE_TGTCPU = "ARM720"
  474. CHECK_VENDOR_720T $reg, $ret
  475.  ENDIF
  476.  IF FORCE_TGTCPU = "ARM740"
  477. CHECK_VENDOR_740T $reg, $ret
  478.  ENDIF
  479.  IF FORCE_TGTCPU = "ARM920"
  480. CHECK_VENDOR_920T $reg, $ret
  481.  ENDIF
  482.  IF FORCE_TGTCPU = "ARM940"
  483. CHECK_VENDOR_940T $reg, $ret
  484.  ENDIF
  485.  IF FORCE_TGTCPU = "SA110"
  486. CHECK_VENDOR_110 $reg, $ret
  487.  ENDIF
  488. MEND
  489. ;------------------------------------------------------------------
  490. ; Macros to hide internals of each processor's cache implementation
  491. ;
  492. ; Never set coprocessor bits directly, use the macros. To use:
  493. ; RDMMU_STATE $reg ; read the flags
  494. ; CLEAR_IDC $reg ; disable I & D caches
  495. ; SET_MMU $reg ; enable MMU
  496. ; WRMMU_STATE $reg ; update the coprocessor
  497. ;
  498. ; CLEAR_IDC Clear Instruction & Data Cache Bits (& Write Buffer)
  499. ; CLEAR_ICACHE Clear (at least) Instruction Cache Bits
  500. ; CLEAR_DCACHE Clear (at least) Data Cache Bits
  501. ; CLEAR_WBUFFER Clear Write Buffer Bits
  502. ; CLEAR_MMU Clear MMU Enable Bits
  503. ; CLEAR_BIGEND Clear Big Endian Enable Bits
  504. ; SET_IDC As above, but Set each mode
  505. ; SET_ICACHE
  506. ; SET_DCACHE
  507. ; SET_WBUFFER
  508. ; SET_MMU
  509. ; SET_BIGEND
  510. ; TEST_MMU Simple tests to see if bits are already set
  511. ; TEST_BIGEND
  512. MACRO
  513. CLEAR_IDC $state
  514. NO_CLEAR_IDC $state
  515.  IF FORCE_TGTCPU = "ARM720"
  516. CLEAR_IDC_720T $state
  517.  ENDIF
  518.  IF FORCE_TGTCPU = "ARM740"
  519. CLEAR_IDC_740T $state
  520.  ENDIF
  521.  IF FORCE_TGTCPU = "ARM920"
  522. CLEAR_IDC_920T $state
  523.  ENDIF
  524.  IF FORCE_TGTCPU = "ARM940"
  525. CLEAR_IDC_940T $state
  526.  ENDIF
  527.  IF FORCE_TGTCPU = "SA110"
  528. CLEAR_IDC_110 $state
  529.  ENDIF
  530. MEND
  531. MACRO
  532. CLEAR_ICACHE $state
  533. NO_CLEAR_ICACHE $state
  534.  IF FORCE_TGTCPU = "ARM720"
  535. CLEAR_ICACHE_720T $state
  536.  ENDIF
  537.  IF FORCE_TGTCPU = "ARM740"
  538. CLEAR_ICACHE_740T $state
  539.  ENDIF
  540.  IF FORCE_TGTCPU = "ARM920"
  541. CLEAR_ICACHE_920T $state
  542.  ENDIF
  543.  IF FORCE_TGTCPU = "ARM940"
  544. CLEAR_ICACHE_940T $state
  545.  ENDIF
  546.  IF FORCE_TGTCPU = "SA110"
  547. CLEAR_ICACHE_110 $state
  548.  ENDIF
  549. MEND
  550. MACRO
  551. CLEAR_DCACHE $state
  552. NO_CLEAR_DCACHE $state
  553.  IF FORCE_TGTCPU = "ARM720"
  554. CLEAR_DCACHE_720T $state
  555.  ENDIF
  556.  IF FORCE_TGTCPU = "ARM740"
  557. CLEAR_DCACHE_740T $state
  558.  ENDIF
  559.  IF FORCE_TGTCPU = "ARM920"
  560. CLEAR_DCACHE_920T $state
  561.  ENDIF
  562.  IF FORCE_TGTCPU = "ARM940"
  563. CLEAR_DCACHE_940T $state
  564.  ENDIF
  565.  IF FORCE_TGTCPU = "SA110"
  566. CLEAR_DCACHE_110 $state
  567.  ENDIF
  568. MEND
  569. MACRO
  570. CLEAR_WBUFFER $state
  571. NO_CLEAR_WBUFFER $state
  572.  IF FORCE_TGTCPU = "ARM720"
  573. CLEAR_WBUFFER_720T $state
  574.  ENDIF
  575.  IF FORCE_TGTCPU = "ARM740"
  576. CLEAR_WBUFFER_740T $state
  577.  ENDIF
  578.  IF FORCE_TGTCPU = "SA110"
  579. CLEAR_WBUFFER_110 $state
  580.  ENDIF
  581. MEND
  582. MACRO
  583. CLEAR_MMU $state
  584. NO_CLEAR_MMU $state
  585.  IF FORCE_TGTCPU = "ARM720"
  586. CLEAR_MMU_720T $state
  587.  ENDIF
  588.  IF FORCE_TGTCPU = "ARM740"
  589. CLEAR_MMU_740T $state
  590.  ENDIF
  591.  IF FORCE_TGTCPU = "ARM920"
  592. CLEAR_MMU_920T $state
  593.  ENDIF
  594.  IF FORCE_TGTCPU = "ARM940"
  595. CLEAR_MMU_940T $state
  596.  ENDIF
  597.  IF FORCE_TGTCPU = "SA110"
  598. CLEAR_MMU_110 $state
  599.  ENDIF
  600. MEND
  601. MACRO
  602. CLEAR_BIGEND $state
  603. NO_CLEAR_BIGEND $state
  604.  IF FORCE_TGTCPU = "ARM720"
  605. CLEAR_BIGEND_720T $state
  606.  ENDIF
  607.  IF FORCE_TGTCPU = "ARM740"
  608. CLEAR_BIGEND_740T $state
  609.  ENDIF
  610.  IF FORCE_TGTCPU = "ARM920"
  611. CLEAR_BIGEND_920T $state
  612.  ENDIF
  613.  IF FORCE_TGTCPU = "ARM940"
  614. CLEAR_BIGEND_940T $state
  615.  ENDIF
  616.  IF FORCE_TGTCPU = "SA110"
  617. CLEAR_BIGEND_110 $state
  618.  ENDIF
  619. MEND
  620. MACRO
  621. SET_IDC $state
  622. NO_SET_IDC $state
  623.  IF FORCE_TGTCPU = "ARM720"
  624. SET_IDC_720T $state
  625.  ENDIF
  626.  IF FORCE_TGTCPU = "ARM740"
  627. SET_IDC_740T $state
  628.  ENDIF
  629.  IF FORCE_TGTCPU = "ARM920"
  630. SET_IDC_920T $state
  631.  ENDIF
  632.  IF FORCE_TGTCPU = "ARM940"
  633. SET_IDC_940T $state
  634.  ENDIF
  635.  IF FORCE_TGTCPU = "SA110"
  636. SET_IDC_110 $state
  637.  ENDIF
  638. MEND
  639. MACRO
  640. SET_ICACHE $state
  641. NO_SET_ICACHE $state
  642.  IF FORCE_TGTCPU = "ARM720"
  643. SET_ICACHE_720T $state
  644.  ENDIF
  645.  IF FORCE_TGTCPU = "ARM740"
  646. SET_ICACHE_740T $state
  647.  ENDIF
  648.  IF FORCE_TGTCPU = "ARM920"
  649. SET_ICACHE_920T $state
  650.  ENDIF
  651.  IF FORCE_TGTCPU = "ARM940"
  652. SET_ICACHE_940T $state
  653.  ENDIF
  654.  IF FORCE_TGTCPU = "SA110"
  655. SET_ICACHE_110 $state
  656.  ENDIF
  657. MEND
  658. MACRO
  659. SET_DCACHE $state
  660. NO_SET_DCACHE $state
  661.  IF FORCE_TGTCPU = "ARM720"
  662. SET_DCACHE_720T $state
  663.  ENDIF
  664.  IF FORCE_TGTCPU = "ARM740"
  665. SET_DCACHE_740T $state
  666.  ENDIF
  667.  IF FORCE_TGTCPU = "ARM920"
  668. SET_DCACHE_920T $state
  669.  ENDIF
  670.  IF FORCE_TGTCPU = "ARM940"
  671. SET_DCACHE_940T $state
  672.  ENDIF
  673.  IF FORCE_TGTCPU = "SA110"
  674. SET_DCACHE_110 $state
  675.  ENDIF
  676. MEND
  677. MACRO
  678. SET_WBUFFER $state
  679. NO_SET_WBUFFER $state
  680.  IF FORCE_TGTCPU = "ARM720"
  681. SET_WBUFFER_720T $state
  682.  ENDIF
  683.  IF FORCE_TGTCPU = "ARM740"
  684. SET_WBUFFER_740T $state
  685.  ENDIF
  686.  IF FORCE_TGTCPU = "SA110"
  687. SET_WBUFFER_110 $state
  688.  ENDIF
  689. MEND
  690. MACRO
  691. SET_MMU $state
  692. NO_SET_MMU $state
  693.  IF FORCE_TGTCPU = "ARM720"
  694. SET_MMU_720T $state
  695.  ENDIF
  696.  IF FORCE_TGTCPU = "ARM920"
  697. SET_MMU_920T $state
  698.  ENDIF
  699.  IF FORCE_TGTCPU = "SA110"
  700. SET_MMU_110 $state
  701.  ENDIF
  702. MEND
  703. MACRO
  704. SET_BIGEND $state
  705. NO_SET_BIGEND $state
  706.  IF FORCE_TGTCPU = "ARM720"
  707. SET_BIGEND_720T $state
  708.  ENDIF
  709.  IF FORCE_TGTCPU = "ARM740"
  710. SET_BIGEND_740T $state
  711.  ENDIF
  712.  IF FORCE_TGTCPU = "ARM920"
  713. SET_BIGEND_920T $state
  714.  ENDIF
  715.  IF FORCE_TGTCPU = "ARM940"
  716. SET_BIGEND_940T $state
  717.  ENDIF
  718.  IF FORCE_TGTCPU = "SA110"
  719. SET_BIGEND_110 $state
  720.  ENDIF
  721. MEND
  722. MACRO
  723. TEST_MMU $state
  724. NO_TEST_MMU $state
  725.  IF FORCE_TGTCPU = "ARM720"
  726. TEST_MMU_720T $state
  727.  ENDIF
  728.  IF FORCE_TGTCPU = "ARM740"
  729. TEST_MMU_740T $state
  730.  ENDIF
  731.  IF FORCE_TGTCPU = "ARM920"
  732. TEST_MMU_920T $state
  733.  ENDIF
  734.  IF FORCE_TGTCPU = "ARM940"
  735. TEST_MMU_940T $state
  736.  ENDIF
  737.  IF FORCE_TGTCPU = "SA110"
  738. TEST_MMU_110 $state
  739.  ENDIF
  740. MEND
  741. MACRO
  742. TEST_BIGEND $state
  743. NO_TEST_BIGEND $state
  744.  IF FORCE_TGTCPU = "ARM720"
  745. TEST_BIGEND_720T $state
  746.  ENDIF
  747.  IF FORCE_TGTCPU = "ARM740"
  748. TEST_BIGEND_740T $state
  749.  ENDIF
  750.  IF FORCE_TGTCPU = "ARM920"
  751. TEST_BIGEND_920T $state
  752.  ENDIF
  753.  IF FORCE_TGTCPU = "ARM940"
  754. TEST_BIGEND_940T $state
  755.  ENDIF
  756.  IF FORCE_TGTCPU = "SA110"
  757. TEST_BIGEND_110 $state
  758.  ENDIF
  759. MEND
  760. ;------------------------------------------------------------------
  761. ;Read CPU Code (ID, Vendor revision etc.) register 
  762. ;
  763. MACRO
  764. REALLY_RDCPU_CODE $val
  765. MRC p15, 0, $val, c0, c0 ,0
  766. MEND
  767. MACRO
  768. RDCPU_CODE $val
  769. NO_RDCPU_CODE $val
  770.  IF FORCE_TGTCPU = "ARM720"
  771. RDCPU_CODE_720T $val
  772.  ENDIF
  773.  IF FORCE_TGTCPU = "ARM740"
  774. RDCPU_CODE_740T $val
  775.  ENDIF
  776.  IF FORCE_TGTCPU = "ARM920"
  777. RDCPU_CODE_920T $val
  778.  ENDIF
  779.  IF FORCE_TGTCPU = "ARM940"
  780. RDCPU_CODE_940T $val
  781.  ENDIF
  782.  IF FORCE_TGTCPU = "ARM940"
  783. RDCPU_CODE_940T $val
  784.  ENDIF
  785.  IF FORCE_TGTCPU = "SA110"
  786. RDCPU_CODE_110 $val
  787.  ENDIF
  788. MEND
  789. ;Extract CPU ID from CPU Code register
  790. ;
  791. MACRO
  792. RDCPU_ID $w1, $val
  793. NO_RDCPU_ID $w1, $val
  794.  IF FORCE_TGTCPU = "ARM720"
  795. RDCPU_ID_720T $w1, $val
  796.  ENDIF
  797.  IF FORCE_TGTCPU = "ARM740"
  798. RDCPU_ID_740T $w1, $val
  799.  ENDIF
  800.  IF FORCE_TGTCPU = "ARM920"
  801. RDCPU_ID_920T $w1, $val
  802.  ENDIF
  803.  IF FORCE_TGTCPU = "ARM940"
  804. RDCPU_ID_940T $w1, $val
  805.  ENDIF
  806.  IF FORCE_TGTCPU = "SA110"
  807. RDCPU_ID_110 $w1, $val
  808.  ENDIF
  809. MEND
  810. ;Extract CPU Vendor from CPU Code register
  811. ;
  812. MACRO
  813. RDCPU_VENDOR $w1, $val
  814. NO_RDCPU_VENDOR $w1, $val
  815.  IF FORCE_TGTCPU = "ARM720"
  816. RDCPU_VENDOR_720T $w1, $val
  817.  ENDIF
  818.  IF FORCE_TGTCPU = "ARM740"
  819. RDCPU_VENDOR_740T $w1, $val
  820.  ENDIF
  821.  IF FORCE_TGTCPU = "ARM920"
  822. RDCPU_VENDOR_920T $w1, $val
  823.  ENDIF
  824.  IF FORCE_TGTCPU = "ARM940"
  825. RDCPU_VENDOR_940T $w1, $val
  826.  ENDIF
  827.  IF FORCE_TGTCPU = "SA110"
  828. RDCPU_VENDOR_110 $w1, $val
  829.  ENDIF
  830. MEND
  831. ;Coprocessor read of ID register (cache line sizes)
  832. ;
  833. MACRO
  834. RDCACHE_SIZES $reg_number
  835. NO_RDCACHE_SIZES $reg_number
  836.  IF FORCE_TGTCPU = "ARM920"
  837. RDCACHE_SIZES_920T $reg_number
  838.  ENDIF
  839.  IF FORCE_TGTCPU = "ARM940"
  840. RDCACHE_SIZES_940T $reg_number
  841.  ENDIF
  842. MEND
  843. ;Coprocessor read of Control register 
  844. ;
  845. MACRO
  846. RDMMU_STATE $reg_number
  847. NO_RDMMU_STATE $reg_number
  848.  IF FORCE_TGTCPU = "ARM720"
  849. RDMMU_STATE_720T $reg_number
  850.  ENDIF
  851.  IF FORCE_TGTCPU = "ARM740"
  852. RDMMU_STATE_740T $reg_number
  853.  ENDIF
  854.  IF FORCE_TGTCPU = "ARM920"
  855. RDMMU_STATE_920T $reg_number
  856.  ENDIF
  857.  IF FORCE_TGTCPU = "ARM940"
  858. RDMMU_STATE_940T $reg_number
  859.  ENDIF
  860.  IF FORCE_TGTCPU = "SA110"
  861. RDMMU_STATE_110 $reg_number
  862.  ENDIF
  863. MEND
  864. ;Coprocessor write of Control register 
  865. ;
  866. MACRO 
  867. WRMMU_STATE $reg_number
  868. NO_WRMMU_STATE $reg_number
  869.  IF FORCE_TGTCPU = "ARM720"
  870. WRMMU_STATE_720T $reg_number
  871.  ENDIF
  872.  IF FORCE_TGTCPU = "ARM740"
  873. WRMMU_STATE_740T $reg_number
  874.  ENDIF
  875.  IF FORCE_TGTCPU = "ARM920"
  876. WRMMU_STATE_920T $reg_number
  877.  ENDIF
  878.  IF FORCE_TGTCPU = "ARM940"
  879. WRMMU_STATE_940T $reg_number
  880.  ENDIF
  881.  IF FORCE_TGTCPU = "SA110"
  882. WRMMU_STATE_110 $reg_number
  883.  ENDIF
  884. MEND
  885. ;------------------------------------------------------------------
  886. ;Coprocessor read of Translation Table Base reg. 
  887. ;
  888. MACRO
  889. RDMMU_TTBase $reg_number
  890. NO_RDMMU_TTBase $reg_number
  891.  IF FORCE_TGTCPU = "ARM720"
  892. RDMMU_TTBase_720T $reg_number
  893.  ENDIF
  894.  IF FORCE_TGTCPU = "ARM920"
  895. RDMMU_TTBase_920T $reg_number
  896.  ENDIF
  897.  IF FORCE_TGTCPU = "SA110"
  898. RDMMU_TTBase_110 $reg_number
  899.  ENDIF
  900. MEND
  901. ;Coprocessor write of Translation Table Base reg. 
  902. ;
  903. MACRO 
  904. WRMMU_TTBase $reg_number
  905. NO_WRMMU_TTBase $reg_number
  906.  IF FORCE_TGTCPU = "ARM720"
  907. WRMMU_TTBase_720T $reg_number
  908.  ENDIF
  909.  IF FORCE_TGTCPU = "ARM920"
  910. WRMMU_TTBase_920T $reg_number
  911.  ENDIF
  912.  IF FORCE_TGTCPU = "SA110"
  913. WRMMU_TTBase_110 $reg_number
  914.  ENDIF
  915. MEND
  916. ;Coprocessor read of Domain Access Control reg. 
  917. ;
  918. MACRO
  919. RDMMU_DAControl $reg_number
  920. NO_RDMMU_DAControl $reg_number
  921.  IF FORCE_TGTCPU = "ARM720"
  922. RDMMU_DAControl_720T $reg_number
  923.  ENDIF
  924.  IF FORCE_TGTCPU = "ARM920"
  925. RDMMU_DAControl_920T $reg_number
  926.  ENDIF
  927.  IF FORCE_TGTCPU = "SA110"
  928. RDMMU_DAControl_110 $reg_number
  929.  ENDIF
  930. MEND
  931. ;Coprocessor write of Domain Access Control reg. 
  932. ;
  933. MACRO 
  934. WRMMU_DAControl $reg_number
  935. NO_WRMMU_DAControl $reg_number
  936.  IF FORCE_TGTCPU = "ARM720"
  937. WRMMU_DAControl_720T $reg_number
  938.  ENDIF
  939.  IF FORCE_TGTCPU = "ARM920"
  940. WRMMU_DAControl_920T $reg_number
  941.  ENDIF
  942.  IF FORCE_TGTCPU = "SA110"
  943. WRMMU_DAControl_110 $reg_number
  944.  ENDIF
  945. MEND
  946. ;Coprocessor read of Fault Status register 
  947. ;
  948.     MACRO
  949.     RDMMU_FaultStatus $reg
  950.     NO_RDMMU_FaultStatus $reg
  951.  IF FORCE_TGTCPU = "SA110"
  952.     RDMMU_FaultStatus_110 $reg
  953.  ENDIF
  954.  IF FORCE_TGTCPU = "SA110"
  955.     RDMMU_FaultStatus_110 $reg
  956.  ENDIF
  957.  IF FORCE_TGTCPU = "SA110"
  958.     RDMMU_FaultStatus_110 $reg
  959.  ENDIF
  960.     MEND
  961. ;Coprocessor write of Fault Status register 
  962. ;
  963.     MACRO 
  964.     WRMMU_FaultStatus $reg
  965.     NO_WRMMU_FaultStatus $reg
  966.  IF FORCE_TGTCPU = "ARM720"
  967.     WRMMU_FaultStatus_720T $reg
  968.  ENDIF
  969.  IF FORCE_TGTCPU = "ARM920"
  970.     WRMMU_FaultStatus_920T $reg
  971.  ENDIF
  972.  IF FORCE_TGTCPU = "SA110"
  973.     WRMMU_FaultStatus_110 $reg
  974.  ENDIF
  975.     MEND
  976. ;Coprocessor read of Fault Address register 
  977. ;
  978.     MACRO
  979.     RDMMU_FaultAddress $reg
  980.     NO_RDMMU_FaultAddress $reg
  981.  IF FORCE_TGTCPU = "ARM720"
  982.     RDMMU_FaultAddress_720T $reg
  983.  ENDIF
  984.  IF FORCE_TGTCPU = "ARM920"
  985.     RDMMU_FaultAddress_920T $reg
  986.  ENDIF
  987.  IF FORCE_TGTCPU = "SA110"
  988.     RDMMU_FaultAddress_110 $reg
  989.  ENDIF
  990.     MEND
  991. ;Coprocessor write of Fault Address register 
  992. ;
  993.     MACRO 
  994.     WRMMU_FaultAddress $reg
  995.     NO_WRMMU_FaultAddress $reg
  996.  IF FORCE_TGTCPU = "ARM720"
  997.     WRMMU_FaultAddress_720T $reg
  998.  ENDIF
  999.  IF FORCE_TGTCPU = "ARM920"
  1000.     WRMMU_FaultAddress_920T $reg
  1001.  ENDIF
  1002.  IF FORCE_TGTCPU = "SA110"
  1003.     WRMMU_FaultAddress_110 $reg
  1004.  ENDIF
  1005.     MEND
  1006. ;Flush TLB 
  1007. ;
  1008. MACRO
  1009. WRMMU_FlushTB $reg_number
  1010. NO_WRMMU_FlushTB $reg_number
  1011.  IF FORCE_TGTCPU = "ARM720"
  1012. WRMMU_FlushTB_720T $reg_number
  1013.  ENDIF
  1014.  IF FORCE_TGTCPU = "ARM920"
  1015. WRMMU_FlushTB_920T $reg_number
  1016.  ENDIF
  1017.  IF FORCE_TGTCPU = "SA110"
  1018. WRMMU_FlushTB_110 $reg_number
  1019.  ENDIF
  1020. MEND
  1021. ;Flush Instruction TLB 
  1022. ;
  1023. MACRO
  1024. WRMMU_FlushITB $reg_number
  1025. NO_WRMMU_FlushITB $reg_number
  1026.  IF FORCE_TGTCPU = "ARM720"
  1027. WRMMU_FlushITB_720T $reg_number
  1028.  ENDIF
  1029.  IF FORCE_TGTCPU = "ARM920"
  1030. WRMMU_FlushITB_920T $reg_number
  1031.  ENDIF
  1032.  IF FORCE_TGTCPU = "SA110"
  1033. WRMMU_FlushITB_110 $reg_number
  1034.  ENDIF
  1035. MEND
  1036. ;Flush Data TLB
  1037. ;
  1038. MACRO
  1039. WRMMU_FlushDTB $reg_number
  1040. NO_WRMMU_FlushDTB $reg_number
  1041.  IF FORCE_TGTCPU = "ARM720"
  1042. WRMMU_FlushDTB_720T $reg_number
  1043.  ENDIF
  1044.  IF FORCE_TGTCPU = "ARM920"
  1045. WRMMU_FlushDTB_920T $reg_number
  1046.  ENDIF
  1047.  IF FORCE_TGTCPU = "SA110"
  1048. WRMMU_FlushDTB_110 $reg_number
  1049.  ENDIF
  1050. MEND
  1051. ;-----------------------------------------------------------
  1052. ; MPU support macros:
  1053. ;Coprocessor write of MPU cache bits 
  1054. ;
  1055. MACRO 
  1056. WRMPU_CacheBits $reg_number
  1057. NO_WRMPU_CacheBits $reg_number
  1058.  IF FORCE_TGTCPU = "ARM740"
  1059. WRMPU_CacheBits_740T $reg_number
  1060.  ENDIF
  1061.  IF FORCE_TGTCPU = "ARM940"
  1062. WRMPU_CacheBits_940T $reg_number
  1063.  ENDIF
  1064. MEND
  1065. ;Coprocessor write of MPU buffer bits 
  1066. ;
  1067. MACRO 
  1068. WRMPU_BufferBits $reg_number
  1069. NO_WRMPU_BufferBits $reg_number
  1070.  IF FORCE_TGTCPU = "ARM740"
  1071. WRMPU_BufferBits_740T $reg_number
  1072.  ENDIF
  1073.  IF FORCE_TGTCPU = "ARM940"
  1074. WRMPU_BufferBits_940T $reg_number
  1075.  ENDIF
  1076. MEND
  1077. ;Coprocessor write of MPU access bits 
  1078. ;
  1079. MACRO 
  1080. WRMPU_AccessBits $reg_number
  1081. NO_WRMPU_AccessBits $reg_number
  1082.  IF FORCE_TGTCPU = "ARM740"
  1083. WRMPU_AccessBits_740T $reg_number
  1084.  ENDIF
  1085.  IF FORCE_TGTCPU = "ARM940"
  1086. WRMPU_AccessBits_940T $reg_number
  1087.  ENDIF
  1088. MEND
  1089. ;Coprocessor write of MPU region registors 
  1090. ;
  1091. MACRO 
  1092. WRMPU_Region $region, $reg_number
  1093. NO_WRMPU_Region $region, $reg_number
  1094.  IF FORCE_TGTCPU = "ARM740"
  1095. WRMPU_Region_740T $region, $reg_number
  1096.  ENDIF
  1097.  IF FORCE_TGTCPU = "ARM940"
  1098. WRMPU_Region_940T $region, $reg_number
  1099.  ENDIF
  1100. MEND
  1101. ;-----------------------------------------------------------
  1102. ;Coprocessor cache control 
  1103. ;Flush I & D Caches
  1104. ;
  1105. MACRO 
  1106. WRCACHE_FlushIDC $reg_number
  1107. NO_WRCACHE_FlushIDC $reg_number
  1108.  IF FORCE_TGTCPU = "ARM720"
  1109. WRCACHE_FlushIDC_720T $reg_number
  1110.  ENDIF
  1111.  IF FORCE_TGTCPU = "ARM740"
  1112. WRCACHE_FlushIDC_740T $reg_number
  1113.  ENDIF
  1114.  IF FORCE_TGTCPU = "ARM920"
  1115. WRCACHE_FlushIDC_920T $reg_number
  1116.  ENDIF
  1117.  IF FORCE_TGTCPU = "ARM940"
  1118. WRCACHE_FlushIDC_940T $reg_number
  1119.  ENDIF
  1120.  IF FORCE_TGTCPU = "SA110"
  1121. WRCACHE_FlushIDC_110 $reg_number
  1122.  ENDIF
  1123. MEND
  1124. ;Coprocessor cache control 
  1125. ;Flush ICache
  1126. ;
  1127. MACRO 
  1128. WRCACHE_FlushIC $reg_number
  1129. NO_WRCACHE_FlushIC $reg_number
  1130.  IF FORCE_TGTCPU = "ARM720"
  1131. WRCACHE_FlushIC_720T $reg_number
  1132.  ENDIF
  1133.  IF FORCE_TGTCPU = "ARM740"
  1134. WRCACHE_FlushIC_740T $reg_number
  1135.  ENDIF
  1136.  IF FORCE_TGTCPU = "ARM920"
  1137. WRCACHE_FlushIC_920T $reg_number
  1138.  ENDIF
  1139.  IF FORCE_TGTCPU = "ARM940"
  1140. WRCACHE_FlushIC_940T $reg_number
  1141.  ENDIF
  1142.  IF FORCE_TGTCPU = "SA110"
  1143. WRCACHE_FlushIC_110 $reg_number
  1144.  ENDIF
  1145. MEND
  1146. ;Coprocessor cache control 
  1147. ;Flush DCache
  1148. ;
  1149. MACRO 
  1150. WRCACHE_FlushDC $reg_number
  1151. NO_WRCACHE_FlushDC $reg_number
  1152.  IF FORCE_TGTCPU = "ARM720"
  1153. WRCACHE_FlushDC_720T $reg_number
  1154.  ENDIF
  1155.  IF FORCE_TGTCPU = "ARM740"
  1156. WRCACHE_FlushDC_740T $reg_number
  1157.  ENDIF
  1158.  IF FORCE_TGTCPU = "ARM920"
  1159. WRCACHE_FlushDC_920T $reg_number
  1160.  ENDIF
  1161.  IF FORCE_TGTCPU = "ARM940"
  1162. WRCACHE_FlushDC_940T $reg_number
  1163.  ENDIF
  1164.  IF FORCE_TGTCPU = "SA110"
  1165. WRCACHE_FlushDC_110 $reg_number
  1166.  ENDIF
  1167. MEND
  1168. ;Coprocessor cache control 
  1169. ;Flush DCache entry
  1170. ;
  1171. MACRO 
  1172. WRCACHE_CacheFlushDentry $reg_number
  1173. NO_WRCACHE_CacheFlushDentry $reg_number
  1174.  IF FORCE_TGTCPU = "ARM720"
  1175. WRCACHE_CacheFlushDentry_720T $reg_number
  1176.  ENDIF
  1177.  IF FORCE_TGTCPU = "ARM740"
  1178. WRCACHE_CacheFlushDentry_740T $reg_number
  1179.  ENDIF
  1180.  IF FORCE_TGTCPU = "ARM920"
  1181. WRCACHE_CacheFlushDentry_920T $reg_number
  1182.  ENDIF
  1183.  IF FORCE_TGTCPU = "ARM940"
  1184. WRCACHE_CacheFlushDentry_940T $reg_number
  1185.  ENDIF
  1186.  IF FORCE_TGTCPU = "SA110"
  1187. WRCACHE_CacheFlushDentry_110 $reg_number
  1188.  ENDIF
  1189. MEND
  1190. ;Coprocessor cache control 
  1191. ;Clean DCache entry
  1192. ;
  1193. MACRO 
  1194. WRCACHE_CleanDCentry $reg_number
  1195. NO_WRCACHE_CleanDCentry $reg_number
  1196.  IF FORCE_TGTCPU = "ARM720"
  1197. WRCACHE_CleanDCentry_720T $reg_number
  1198.  ENDIF
  1199.  IF FORCE_TGTCPU = "ARM740"
  1200. WRCACHE_CleanDCentry_740T $reg_number
  1201.  ENDIF
  1202.  IF FORCE_TGTCPU = "ARM920"
  1203. WRCACHE_CleanDCentry_920T $reg_number
  1204.  ENDIF
  1205.  IF FORCE_TGTCPU = "ARM940"
  1206. WRCACHE_CleanDCentry_940T $reg_number
  1207.  ENDIF
  1208.  IF FORCE_TGTCPU = "SA110"
  1209. WRCACHE_CleanDCentry_110 $reg_number
  1210.  ENDIF
  1211. MEND
  1212. ;Coprocessor cache control 
  1213. ;Clean + Flush DCache entry
  1214. ;
  1215. MACRO 
  1216. WRCACHE_Clean_FlushDCentry $reg_number
  1217. NO_WRCACHE_Clean_FlushDCentry $reg_number
  1218.  IF FORCE_TGTCPU = "ARM720"
  1219. WRCACHE_Clean_FlushDCentry_720T $reg_number
  1220.  ENDIF
  1221.  IF FORCE_TGTCPU = "ARM740"
  1222. WRCACHE_Clean_FlushDCentry_740T $reg_number
  1223.  ENDIF
  1224.  IF FORCE_TGTCPU = "ARM920"
  1225. WRCACHE_Clean_FlushDCentry_920T $reg_number
  1226.  ENDIF
  1227.  IF FORCE_TGTCPU = "ARM940"
  1228. WRCACHE_Clean_FlushDCentry_940T $reg_number
  1229.  ENDIF
  1230.  IF FORCE_TGTCPU = "SA110"
  1231. WRCACHE_Clean_FlushDCentry_110 $reg_number
  1232.  ENDIF
  1233. MEND
  1234. ;Drain Write Buffer.
  1235. ;
  1236. MACRO
  1237. WRCACHE_DrainWriteBuffer $reg_number
  1238. NO_WRCACHE_DrainWriteBuffer $reg_number
  1239.  IF FORCE_TGTCPU = "ARM720"
  1240. WRCACHE_DrainWriteBuffer_720T $reg_number
  1241.  ENDIF
  1242.  IF FORCE_TGTCPU = "ARM740"
  1243. WRCACHE_DrainWriteBuffer_740T $reg_number
  1244.  ENDIF
  1245.  IF FORCE_TGTCPU = "ARM920"
  1246. WRCACHE_DrainWriteBuffer_920T $reg_number
  1247.  ENDIF
  1248.  IF FORCE_TGTCPU = "ARM940"
  1249. WRCACHE_DrainWriteBuffer_940T $reg_number
  1250.  ENDIF
  1251.  IF FORCE_TGTCPU = "SA110"
  1252. WRCACHE_DrainWriteBuffer_110 $reg_number
  1253.  ENDIF
  1254. MEND
  1255. ;Clean DCache (only) from address in $reg1 to (excl) addr in $reg2
  1256. ;
  1257. MACRO
  1258. WRCACHE_CleanDrange $reg1, $reg2
  1259. NO_WRCACHE_CleanDrange $reg1, $reg2
  1260.  IF FORCE_TGTCPU = "ARM720"
  1261. WRCACHE_CleanDrange_720T $reg1, $reg2
  1262.  ENDIF
  1263.  IF FORCE_TGTCPU = "ARM740"
  1264. WRCACHE_CleanDrange_740T $reg1, $reg2
  1265.  ENDIF
  1266.  IF FORCE_TGTCPU = "ARM920"
  1267. WRCACHE_CleanDrange_920T $reg1, $reg2
  1268.  ENDIF
  1269.  IF FORCE_TGTCPU = "ARM940"
  1270. WRCACHE_CleanDrange_940T $reg1, $reg2
  1271.  ENDIF
  1272.  IF FORCE_TGTCPU = "SA110"
  1273. WRCACHE_CleanDrange_110 $reg1, $reg2
  1274.  ENDIF
  1275. MEND
  1276. ;Clean all DCache 
  1277. ;
  1278. MACRO
  1279. WRCACHE_CleanDCache $w1, $w2, $w3, $w4, $w5, $w6
  1280. NO_WRCACHE_CleanDCache $w1, $w2, $w3, $w4, $w5, $w6
  1281.  IF FORCE_TGTCPU = "ARM720"
  1282. WRCACHE_CleanDCache_720T $w1, $w2, $w3, $w4, $w5, $w6
  1283.  ENDIF
  1284.  IF FORCE_TGTCPU = "ARM740"
  1285. WRCACHE_CleanDCache_740T $w1, $w2, $w3, $w4, $w5, $w6
  1286.  ENDIF
  1287.  IF FORCE_TGTCPU = "ARM920"
  1288. WRCACHE_CleanDCache_920T $w1, $w2, $w3, $w4, $w5, $w6
  1289.  ENDIF
  1290.  IF FORCE_TGTCPU = "ARM940"
  1291. WRCACHE_CleanDCache_940T $w1, $w2, $w3, $w4, $w5, $w6
  1292.  ENDIF
  1293.  IF FORCE_TGTCPU = "SA110"
  1294. WRCACHE_CleanDCache_110 $w1, $w2, $w3, $w4, $w5, $w6
  1295.  ENDIF
  1296. MEND
  1297. ;------------------------------------------------------------------
  1298. ;Coprocessor test/clock/idle control 
  1299. ;Enable Clock Switching
  1300. ;
  1301. MACRO
  1302. WRCLK_EnableClockSW $reg_number
  1303. NO_WRCLK_EnableClockSW $reg_number
  1304.  IF FORCE_TGTCPU = "ARM920"
  1305. WRCLK_EnableClockSW_920T $reg_number
  1306.  ENDIF
  1307.  IF FORCE_TGTCPU = "ARM940"
  1308. WRCLK_EnableClockSW_940T $reg_number
  1309.  ENDIF
  1310.  IF FORCE_TGTCPU = "SA110"
  1311. WRCLK_EnableClockSW_110 $reg_number
  1312.  ENDIF
  1313. MEND
  1314. ;Coprocessor test/clock/idle control 
  1315. ;Disable Clock Switching
  1316. ;
  1317. MACRO
  1318. WRCLK_DisableClockSW $reg_number
  1319. NO_WRCLK_DisableClockSW $reg_number
  1320.  IF FORCE_TGTCPU = "ARM920"
  1321. WRCLK_DisableClockSW_920T $reg_number
  1322.  ENDIF
  1323.  IF FORCE_TGTCPU = "ARM940"
  1324. WRCLK_DisableClockSW_940T $reg_number
  1325.  ENDIF
  1326.  IF FORCE_TGTCPU = "SA110"
  1327. WRCLK_DisableClockSW_110 $reg_number
  1328.  ENDIF
  1329. MEND
  1330. ;Coprocessor test/clock/idle control 
  1331. ;Disable nMCLK output
  1332. ;
  1333. MACRO
  1334. WRCLK_DisablenMCLK $reg_number
  1335. NO_WRCLK_DisablenMCLK $reg_number
  1336.  IF FORCE_TGTCPU = "ARM920"
  1337. WRCLK_DisablenMCLK_920T $reg_number
  1338.  ENDIF
  1339.  IF FORCE_TGTCPU = "SA110"
  1340. WRCLK_DisablenMCLK_110 $reg_number
  1341.  ENDIF
  1342. MEND
  1343. ;Coprocessor test/clock/idle control 
  1344. ;Wait for Interrupt
  1345. ;
  1346. MACRO
  1347. WRTEST_WaitInt $reg_number
  1348. NO_WRTEST_WaitInt $reg_number
  1349.  IF FORCE_TGTCPU = "ARM720"
  1350. WRTEST_WaitInt_720T $reg_number
  1351.  ENDIF
  1352.  IF FORCE_TGTCPU = "ARM740"
  1353. WRTEST_WaitInt_740T $reg_number
  1354.  ENDIF
  1355.  IF FORCE_TGTCPU = "ARM920"
  1356. WRTEST_WaitInt_920T $reg_number
  1357.  ENDIF
  1358.  IF FORCE_TGTCPU = "ARM940"
  1359. WRTEST_WaitInt_940T $reg_number
  1360.  ENDIF
  1361.  IF FORCE_TGTCPU = "SA110"
  1362. WRTEST_WaitInt_110 $reg_number
  1363.  ENDIF
  1364. MEND
  1365. ;-----------------------------------------------------------
  1366. ; MPU setup macro and variables
  1367. ;
  1368. MACRO
  1369. SET_MPU_REGION $num, $address, $size, $access
  1370. NO_SET_MPU_REGION $num, $address, $size, $access
  1371.  IF FORCE_TGTCPU = "ARM740"
  1372. SET_MPU_REGION_740T $num, $address, $size, $access
  1373.  ENDIF
  1374.  IF FORCE_TGTCPU = "ARM940"
  1375. SET_MPU_REGION_940T $num, $address, $size, $access
  1376.  ENDIF
  1377. MEND
  1378.  ENDIF
  1379. END
  1380. ; EOF mmumacros.s