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crt0.S
资源名称：8202s_8281s_050405_dvd_622.rar　[点击查看]
上传用户：caisangzi8
上传日期：2013-10-25
资源大小：15756k
文件大小：9k
源码类别：

DVD

开发平台：

C/C++

crt0.S：源码内容
  1. //
  2. // FILE
  3. // crt0.S
  4. // 
  5. // DESCRIPTION
  6. // initialize system and jump to C program
  7. //
  8. #include "regdef.h"
  9. #include "gpio.h"
  10. #include "config.h"
  11. #include "regmapa.h"
  12. #include "user_init.h"
  15. #define PROBE_SDRAM
  16. #define CLEAR_STACK
  17. //#define SDRAM_DBG
  18. //#define BOOTSTRAP_STAMP
  19. //#define BOOTSTRAP_SETUP_UART
  20. //#define BOOTSTRAP_WRITE_UART
  23. #define STATUS_ENDIAN_LITTLE    (0<<25)
  25. #define STATUS_SETUP            STATUS_COP0|STATUS_ENDIAN_LITTLE|STATUS_BEV
  26.                                 // | STATUS_COP3        
  27.                                 // | STATUS_BEV         
  28.                                 // | STATUS_ENDIAN_BIG
  30. //
  31. // Debug
  32. // terry,2005/1/31 09:56AM
  33. #ifdef SDRAM_DBG
  34. #define BOOTSTRAP_SETUP_UART
  35. #define BOOTSTRAP_WRITE_UART
  36. #endif
  39. //
  40. // HWCFG
  41. //
  42. #ifdef  SPHE8202
  43. #ifdef  SPHE8202_NONSHARED
  44. #ifdef  SDRAM_BUS_32BITS
  45. #define HWCFG_SET   0x3f       // 32-bit SDRAM 8-bit ROM mode f (non-shared)
  46. #else
  47. #define HWCFG_SET   0x1f       // 16-bit SDRAM 8-bit ROM mode f (non-shared)
  48. #endif
  49. #else
  50. #ifdef  SDRAM_BUS_32BITS
  51. #define HWCFG_SET   0x31       // 32-bit SDRAM 8-bit ROM mode 1 (shared)
  52. #else
  53. #define HWCFG_SET   0x11       // 16-bit SDRAM 8-bit ROM mode 1 (shared)
  54. #endif
  55. #endif
  56. #else
  57. // ORIGINAL 8200
  58. #ifdef  SDRAM_BUS_32BITS
  59. #define HWCFG_SET   1          // hw config fig.1 MPEG+servo+32b
  60. #else
  61. #define HWCFG_SET   2          // hw config fig.2 MPEG+servo+16b
  62. #endif
  63. #endif
  66. //
  67. // STAMPS
  68. //
  69. #define STAMP_STARTUP           (0<<8)
  70. #define STAMP_SDRAM_MRS         (1<<8)
  71. #define STAMP_SDRAM_PROBE       (2<<8)
  72. #define STAMP_SDRAM_PROBE_ERROR (STAMP_SDRAM_PROBE|0xf0)
  73. #define STAMP_CLEAR_STACK       (5<<8)
  74. #define STAMP_SETUP_GP          (6<<8)
  75. #define STAMP_ROMINIT           (7<<8)
  76. #define STAMP_MAIN              (9<<8)
  79. #ifdef BOOTSRAP_STAMP
  80. #define WRITESTAMP(n) 
  81.         .set noat; 
  82.         li AT,(n); 
  83.         sw AT,RF_STAMP(s6); 
  84.         .set at
  85. #else
  86. #define WRITESTAMP(n)
  87. #endif
  90. #define WAIT(n)     
  91.         .set noat; li AT,(n); 100: addiu AT,-1; bnez AT,100b; .set at
  93. #define TX_EMPTY    (1<<6)
  94. #define WAITUART()  
  95.         .set noat; 100: lw AT,RF_UART0_LSR(s6); andi AT,TX_EMPTY; beqz AT,100b; .set at
  97. #define PUTC(c)     
  98.         WAITUART(); 
  99.         .set noat; li AT,(c); sw AT,RF_UART0_DATA(s6); .set at
  101. #define PUTCR(c)     
  102.         WAITUART(); 
  103.         sw c,RF_UART0_DATA(s6)
  106. // PUTA0_0
  107. // write v0(v1) to UART (v1 should be radix-table)
  108. #define PUTA0_0 
  109.         andi v1,0x0f; add v1,v0; lbu v1,(v1); PUTCR(v1)
  112. // PUTA0
  113. // write a0 to UART
  114.         .extern radix_table
  115. #define PUTA0  
  116.         la  v0,radix_table;     
  117.         srl v1,a0,28; PUTA0_0; 
  118.         srl v1,a0,24; PUTA0_0; 
  119.         srl v1,a0,20; PUTA0_0; 
  120.         srl v1,a0,16; PUTA0_0; 
  121.         srl v1,a0,12; PUTA0_0; 
  122.         srl v1,a0,8; PUTA0_0;  
  123.         srl v1,a0,4; PUTA0_0;  
  124.         srl v1,a0,0; PUTA0_0;  
  125.         PUTC(0x0d); PUTC(0x0a)
  129.                 .text
  130.                 .global     start
  131.                 .global     __main
  132.                 .global     s_gp
  133.                 .global     set_sdram_timing
  134.                 .global     set_sdram_timing_low
  136.                 .extern     _stkbtm
  138.                 .rdata    
  139. s_gp:           .word    _gp
  140. s_rominit:      .word    rominit
  142.                 .text
  144. #ifdef SPHE1000
  145. //
  146. // Definition for sunplus's processors
  147. //
  148. #define PRID_SUNPLUS_LX4189 (0x9B407286)
  149. #define PRID_SUNPLUS_MIPZ (0x97350120)
  151. //
  152. // void start_4189
  153. //
  154. .ent start_4189
  155. start_4189:
  156. li s0, 0x10101010
  157. bne t8, s0, start_4189
  158. jr t9
  159. .end start_4189
  160. #endif
  162. //
  163. // void start(void)
  164. //
  165. // *no-return*
  166. //
  167.                 .ent     start
  168. start:
  169.                 // ENABLE COP0/3
  170.                 mfc0    t1, C0_STATUS
  171.                 li      t0, STATUS_SETUP
  172.                 mtc0    t0, C0_STATUS
  173.                 nop
  174.                 nop
  175.                 
  176.                 // setup register-file pointer
  177.                 li      s6, RGST_OFFSET
  179.                 //
  180.                 // Setup hardware configuration
  181.                 //
  182. #ifdef SPHE1000
  183.                 mfc0 t1, C0_PRID
  184.                 li      t2, PRID_SUNPLUS_LX4189
  185.                 beq     t1, t2, start_4189
  187.                 // write HWCFG
  188.                 lw      a0, RF_HW_CFG(s6)
  189.                 ori     a0, a0, (0x8000)
  190.                 sw      a0, RF_HW_CFG_CHG(s6)
  191. 1:              lw      t2, RF_HW_CFG_CHG(s6)           // wait update HWCFG
  192.                 andi    t2, (1<<11)
  193.                 bnez    t2, 1b
  194. #else
  195.                 // write HWCFG
  196.                 li      t1, ('X'<<8)|HWCFG_SET
  197.                 sw      t1, RF_HW_CFG_CHG(s6)           // write HWCFG
  198. 1:              lw      t2, RF_HW_CFG_CHG(s6)           // wait update HWCFG
  199.                 andi    t2, (1<<11)
  200.                 bnez    t2, 1b
  202. #ifdef  BOOT_HALF
  203.                 // change sysclk back to 114.75*2
  204.                 li      t1, 4
  205.                 li      t2, 2
  206.                 sw      t1, RF_SYSCLK_DIV_SEL(s6)
  207.                 sw      t2, RF_SYSCLK_SEL(s6)
  208.                 li      t3, 1000
  209. 1:              addiu   t3, -1
  210.                 bnez    t3, 1b
  211.                 sw      zero, RF_SYSCLK_DIV_SEL(s6)     // (2,0) (229.5, 114.75*2)
  212. #else
  213.                 // change sysclk back to 108mhz
  214.                 li      t1, 4
  215.                 li      t2, 1
  216.                 sw      t1, RF_SYSCLK_DIV_SEL(s6)
  217.                 sw      t2, RF_SYSCLK_SEL(s6)
  218.                 li      t3, 1000
  219. 1:              addiu   t3, -1
  220.                 bnez    t3, 1b
  221.                 sw      zero, RF_SYSCLK_DIV_SEL(s6)     // (1,0)
  222. #endif
  223. #endif
  226.                 // reset sub-systems
  227.                 li      t1, 0xffe0
  228.                 li      t2, 0xffff
  229.                 sw      t1, RF_RESET(s6)                // reset #1 
  230.                 sw      t2, RF_RESET2(s6)               // reset #2
  232.                 sw      zero, RF_RESET(s6)              // freerun #1
  233.                 sw      zero, RF_RESET2(s6)             // freerun #2
  235.                 nop; nop; nop; nop;                     // must delay??
  237.                 WRITESTAMP(STAMP_STARTUP)
  239. #if 0
  240.                 li      t1, ROM_CFG_VAL
  241.                 sw      t1, ROM_CONFIG(s6)
  242. #endif
  244. #ifdef  BOOTSTRAP_SETUP_UART
  245.                 // init uart
  246.                 li      t1, 0
  247.                 li      t2, 58                          // 115200@108MHz
  248.                 sw      t1, RF_UART0_DIV_H(s6)
  249.                 sw      t2, RF_UART0_DIV_L(s6)
  250.                 sw      t1, RF_UART1_DIV_H(s6)
  251.                 sw      t2, RF_UART1_DIV_L(s6)
  252. #endif
  254. #ifdef  BOOTSTRAP_WRITE_UART
  255.                 PUTC('T'); PUTC('S'); PUTC('T');
  256.                 lw a0,RF_HW_CFG(s6); PUTA0
  257.                 PUTC(0x0d); PUTC(0x0a)
  258. #endif
  260.                 //
  261.                 // Setup SDRAM controller
  262.                 //
  264.                 // setup SDRAM interface timing
  265.                 move    a0, zero
  266.                 jal     set_sdram_timing
  268.                 // setup SDRAM controller
  269.                 jal     setup_sdctrl
  271.                 // probe external SDRAM type
  272.                 WRITESTAMP(STAMP_SDRAM_PROBE)
  273.                 jal     probe_sdram_type
  275.                 // reset STK buffer 
  276.                 WRITESTAMP(STAMP_CLEAR_STACK)
  277.                 la      sp, _stkptr                     // set up stack pointer
  278. #ifdef CLEAR_STACK
  279.                 la      t0, _stkbtm        
  280.                 lui     v0, 0xfade
  281.                 ori     v0, 0xfade
  282. 1:              sw      v0, 0(t0)                        // writing initial value
  283.                 addiu   t0, 4
  284.                 bne     t0, sp, 1b
  285. #endif
  287.                 // setup others variables.
  288.                 WRITESTAMP(STAMP_SETUP_GP)
  289.                 lw      gp, s_gp                        // set up GP
  291.                 // setup
  292.                 WRITESTAMP(STAMP_ROMINIT)
  293.                 lw      t0, s_rominit                    // init ROM image of data section
  294.                 jalr    t0
  296.                 // setup others
  297.                 jal     setup_systems
  299.                 WRITESTAMP(STAMP_MAIN)
  301. #ifdef  BOOTSTRAP_WRITE_UART
  302.                 PUTC('A'); PUTC(0x0d); PUTC(0x0a)
  303. #endif
  305. #ifdef  BOOTSTRAP_TEST_SDRAM
  306.                 .extern test_sdram
  307.                 j       test_sdram
  308. #endif
  310.                 j       dvd_main                        // jump to main routine
  311.                 .end    start
  313. //
  315.                 .ent    setup_systems
  316. setup_systems:
  317.                 jr      ra
  318.                 .end    setup_systems
  320. //
  321. // INCLUDE "sdctrl.inc"
  322. // SDRAM related routines
  323. //
  324. #include "sdctrl.inc"
  326. //
  327. // __main
  328. //
  329.                 .ent    __main
  330. __main:
  331.                 lw    gp, s_gp
  332.                 jr    ra
  333.                 .end    __main