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reset.c
资源名称：8202s_8281s_050405_dvd_622.rar　[点击查看]
上传用户：caisangzi8
上传日期：2013-10-25
资源大小：15756k
文件大小：56k
源码类别：

DVD

开发平台：

C/C++

reset.c：源码内容
  1. /**************************************************************************
  2.  *                                                                        *
  3.  *         Copyright (c) 2002 by Sunplus Technology Co., Ltd.             *
  4.  *                                                                        *
  5.  *  This software is copyrighted by and is the property of Sunplus        *
  6.  *  Technology Co., Ltd. All rights are reserved by Sunplus Technology    *
  7.  *  Co., Ltd. This software may only be used in accordance with the       *
  8.  *  corresponding license agreement. Any unauthorized use, duplication,   *
  9.  *  distribution, or disclosure of this software is expressly forbidden.  *
  10.  *                                                                        *
  11.  *  This Copyright notice MUST not be removed or modified without prior   *
  12.  *  written consent of Sunplus Technology Co., Ltd.                       *
  13.  *                                                                        *
  14.  *  Sunplus Technology Co., Ltd. reserves the right to modify this        *
  15.  *  software without notice.                                              *
  16.  *                                                                        *
  17.  *  Sunplus Technology Co., Ltd.                                          *
  18.  *  19, Innovation First Road, Science-Based Industrial Park,             *
  19.  *  Hsin-Chu, Taiwan, R.O.C.                                              *
  20.  **************************************************************************/
  21. /*--------------------------------------------------------------------------
  22. |  File Name   :  reset.c
  23. |
  24. |  Description :   .... reset system
  25. |                 when system need reset,it will goto the file.
  26. |
  27. |
  28. |  Version    :  0.1  
  29. |  
  30. |  Rev    Date              Author(s)      Status & Comments
  31. |-----------------------------------------------------------------------------------------
  32. |  0.1  2004/2/7            Terry          Add DVD Preview function and re-structure code
  33. |  0.1  2004/12/31          caoh           Add Comments
  34. |-----------------------------------------------------------------------------------------*/
  36. #include "config.h"
  37. #include "regmap.h"
  38. #include "global.h"
  40. #include "syscfg.h"
  41. #include "sysclk.h"
  43. #include "load.h"
  44. #include "macro.h"
  45. #include "dma.h"
  46. #include "memcfg.h"
  47. #include "stc.h"
  48. #include "func.h"
  49. #include "cpu.h"
  50. #include "intdef.h"
  52. #include "gpio.h"
  53. #include "uart.h"
  54. #include "uartfifo.h"
  55. #include "viddec.h"
  57. #include "kernel.h"
  58. #include "supfunc.h"
  60. #include "hwif.h"
  61. #include "framebuf.h"   //Jeff 20010717
  62. #include "task.h"
  63. #include "audio.h"
  64. #include "lbaif.h"
  65. #include "cs8403a.h"    //kenny
  66. #include "dvdpe.h"
  67. #include "preview.h"
  68. #include "tvif.h"
  70. #include "test.h"
  71. #include "sio.h"
  72. #include "emuio.h"
  73. #include "user_init.h"
  75. //#define SHOW_SYSTEM_CLOCK
  77. //#ifdef   DVDRELEASE
  78. #ifndef SDRAM_BUS_32BITS
  79. #ifndef SDRAM_16Mb_Mode//terry,2003/11/18 02:04PM
  80. #define  UART0_SHARE_WITH_UART1
  81. #endif
  82. #endif
  83. //#endif
  85. #ifdef QSI_SHOW_ERR_RATE   
  86.     #undef  UART0_SHARE_WITH_UART1
  87. #endif          
  89. #include "reset.h"
  90. #if defined(PT2322)||defined(PT2320)
  91. #include "audctrl.h"
  92. #endif
  93. #ifdef TAS3001_AMP    //
  94. #include "ti3001.h"
  95. #endif
  97. #ifdef TAS5026_AMP    //
  98. #include "ti5026.h"
  99. #endif
  101. #ifndef EMULATION
  102. //#define SETUP_DAC
  103. #endif
  105. #ifndef DVDRELEASE
  106. //#define RESET_DBG 1
  107. //#define DRAM_TEST 1
  108. //#define TASK_GBG  1//??
  109. #endif
  111. #define DRAM_TEST_16MB
  112. //#define DRAM_TEST_64MB
  114. #ifdef  RESET_DBG   /* alan 02-05-24 */
  115. //#define MONE_CHKSUM
  116. #define MONE_CONFIG
  117. #define reset_status_puts(s)        io_write_wait(s)
  118. #define reset_status_puts_direct(s) io_write(s)
  119. #endif
  121. #ifndef reset_status_puts
  122. #define reset_status_puts(s)        ((void)(s))
  123. #endif
  125. #ifndef reset_status_puts_direct
  126. #define reset_status_puts_direct(s) ((void)(s))
  127. #endif
  130. #ifdef CS8403_ENABLE
  131. //extern void init_cs8403a__(void);
  132. #include "cs8403a.c"
  133. #endif
  136. //
  137. // SPHE8202 tuning
  138. //
  139. #ifdef  SPHE8202
  140. #if 0
  141. #undef  F121_5
  142. #undef  F114_75
  143. #undef  F108
  144. #undef  F94_5
  145. #undef  F81
  146. //#define F81
  147. //#define F108
  148. #define F114_75
  149. //#define F121_5
  150. //#define F128_25
  151. //#define F135
  152. #endif
  153. #endif
  155. #ifdef  SPHE8202
  156. #define ROM_SDRAM_SHARE_BUS
  157. //#define SUPPORT_USB
  158. #endif
  160. #ifdef  SUPPORT_USB
  161. #define USB_CONFIG_PLL
  162. #define CLK54_USE_USBPLL
  163. #endif
  165. #include "sbar.inc"
  168. //
  169. // EPROM_WAIT_STATE
  170. // *NOTE* ROM access time will be n+1 cycles.
  171. //
  172. //  value   cycle   108 94.5    81  67.5    54
  173. //  --------------- ------------------------------- -----
  174. //  3   4   36.8    42.33   48  59.2    74
  175. //  4   5   46  52.91   60  74  92.5
  176. //  5   6   55.2    63.49   72  88.8    111
  177. //  6   7   64.4    74.07   84  103.6   129.5
  178. //  7   8   73.6    84.66   96  118.4   148
  179. //  8   9   82.8    95.24   108 133.2   166.5
  180. //  9   10  92.6    105.82  123.5
  181. //  10  11  101.9   116.40  135.8
  182. //  11  12  111.1   126.98  148.1
  183. //  12  13  120.37  137.57  160.49
  184. //  13  14  129.63  148.15  172.84
  185. //  14  15  138.89  158.73  185.19
  186. //  15  16  148.18  169.31  197.53
  187. //
  189. #define ROM_TACC_DEFAULT    85
  191. #define SYSCLK_CYCLE    ((unsigned)(1.0E9/SYSCLK))      // in ns unit
  192. #define ROM0_TACC       ROM_TACC_DEFAULT
  193. #define ROM1_TACC       ROM_TACC_DEFAULT
  194. #define ROM2_TACC       ROM_TACC_DEFAULT
  195. #define ROM3_TACC       ROM_TACC_DEFAULT
  197. #define ROM0_WAITST     (SYSCLK_CYCLE/ROM0_TACC)
  198. #define ROM1_WAITST     (SYSCLK_CYCLE/ROM1_TACC)
  199. #define ROM2_WAITST     (SYSCLK_CYCLE/ROM2_TACC)
  200. #define ROM3_WAITST     (SYSCLK_CYCLE/ROM3_TACC)
  202. /*
  203. #ifdef BBK_DVD//zhoayanhua add 2003-11-24 14:24
  204. //ircmd_video.c
  205. extern void tv_init_output(void);
  206. #endif
  207. */
  208. extern void dac_setup();
  209. extern void reset_iop();
  210. extern void reset_vfd(void);
  212. // sysmain.c
  213. extern void LoadModual(UINT16 iModuleIndex);
  215. // crt0.S
  216. extern void set_sdram_timing_low(void);
  217. extern void set_sdram_timing(void);
  219. // current file
  220. UINT32 rom_checksum(void);
  221. int reset_change_sysclk(void);
  222. int reset_change_sysclk_27M(void);
  223. int change_system_clock(int);
  225. /**************************************************************************
  226.  *  Function Name: reset_system                                           *
  227.  *  Purposes:                                                             *
  228.  *   1. setup register file pointer (regs0 / s6)                          *
  229.  *   2. reset/enable hardware modules                                     *
  230.  *   3. setup watchdog/scrambling                                         *
  231.  *   4. setup rom1/2/3 bases                                              *
  232.  *   5. setup ROM/FLASH interface                                         *
  233.  *   6. setup system-bus arbitrator                                       *
  234.  *   7. reset audio                                                       *
  235.  *  Descriptions:                                                         *
  236.  *    reset following subsystems to a known state                         *
  237.  *  Arguments:  None                                                      *
  238.  *  Returns: None                                                         *
  239.  *  See also: None                                                        *
  240.  **************************************************************************/
  241. void
  242. reset_system(void)
  243. {
  244.     // setup register file pointer (regs0 / s6)
  245.     InitRegFile();
  247.     regs0->emulation    = 0;        // disable emulation functions
  248.     regs0->reset        = 0x0000;   //
  249. #ifdef SPHE1000
  250.     regs0->reset2       |= 0x2080;   // (boot-strap / tdm / cddsp)
  251. #else
  252.     regs0->reset2       = 0x3080;   // (boot-strap / tdm / cddsp)
  253. #endif
  254.     regs0->clken0       = 0xff7f;   // (grfx)
  255.     regs0->clken1       = 0xffff;   // ()
  256.     regs0->gclken0      = 0xffff;
  257.     regs0->gclken1      = 0xffff;
  259.     // [15:13] atg
  260.     // [7:6] dtg
  261.     // [1:0] watchdog
  262.     regs0->lbc_watchdog   = 0x03;     // disable watchdog/tog
  264.     // setup rom1/2/3 bases
  265. #ifdef SPHE1000 //MIKEY 2004.05.25
  266.     regs0->rom1_base      = 0x00800000 >> 16;       // rom1 m*64k-base  8MB
  267.     regs0->rom2_base      = 0x01000000 >> 16;       // rom2 n*64k-base 16MB
  268.     regs0->rom3_base      = 0x02000000 >> 16;       // rom3 n*64k-base 32MB
  269. #else
  270.     regs0->rom1_base      = 32;       // rom1 m*64k-base
  271.     regs0->rom2_base      = 32;       // rom2 n*64k-base
  272.     regs0->rom3_base      = 32;       // rom2 n*64k-base
  273. #endif
  275. #define VPP_CONFIG1_URGE_EN     (1<<4)//terry,2->4
  276. #define VPP_CONFIG1_URGE_DIS    (0<<4)
  277. #define VPP_CONFIG1_MB45        0       // 720
  278. #define VPP_CONFIG1_MB64        1       // 1024
  279. #define VPP_CONFIG1_MB22        2       // 352
  280. #define VPP_CONFIG1_MB30        3       // 480
  282. #if 1
  283.     regs0->mc_mbwidth       = 45;
  284.     regs0->vpp_config1  = VPP_CONFIG1_URGE_DIS|VPP_CONFIG1_MB45;
  285. #else
  286.     regs0->mc_mbwidth       = 64;
  287.     regs0->vpp_config1  = VPP_CONFIG1_URGE_DIS|VPP_CONFIG1_MB64;
  288. #endif
  290.     vpp_zoom_max    = VPP_ZOOM_MAX;
  292.     //
  293.     // setup ROM/FLASH interface
  294.     regs0->rom_config = 0xf000;     // always no pre-fetch
  295. #if 0
  296. #ifdef ROM_SDRAM_SHARE_BUS
  297.     regs0->rom_config = 0xf000;     // no pre-fetch
  298. #else
  299.     regs0->rom_config = 0xf00f;     // with pre-fetch
  300. #endif
  301. #endif
  303.     {
  304.         unsigned u;
  305.         u = (ROM0_TACC/SYSCLK_CYCLE) | ((ROM1_TACC/SYSCLK_CYCLE)<<8);
  306.         regs0->wait_cyc1_0 = u;
  307.         u = (ROM2_TACC/SYSCLK_CYCLE) | ((ROM3_TACC/SYSCLK_CYCLE)<<8);
  308.         regs0->wait_cyc3_2 = u;
  309.     }
  311.     //
  312.     // setup system-bus arbitrator
  313.     {
  314.         unsigned i;
  315.         for (i=0;i<sizeof(sbar_prr)/sizeof(sbar_prr[0]);i++)
  316.             regs0->sbar_prr[i] = sbar_prr[i];
  317.     }
  319. #ifndef NO_AUDIO_DSP
  320.     // audio
  321.     regs0->aud_reset = 1;
  322.     regs0->aud_reset = 0;
  323. #endif
  324. }
  327. #ifdef  MONE_CHKSUM
  328. /**************************************************************************
  329.  *  Function Name: rom_checksum                                           *
  330.  *  Purposes:                                                             *
  331.  *    At present, the funtion don't used                                  *
  332.  *  Descriptions:                                                         *
  333.  *    calculate rom check-sum (of first 512kbyte)                         *
  334.  *  Arguments:  None                                                      *
  335.  *  Returns: None                                                         *
  336.  *  See also: None                                                        *
  337.  **************************************************************************/
  338. UINT32
  339. rom_checksum(void)
  340. {
  341.     int i;
  342.     UINT32 chksum=0;
  343.     UINT32 *p = (UINT32 *)(ROM_BASE_CACHED);
  344.     for (i=0;i<(512*1024/4); i++)
  345.     {
  346.         chksum += *p++;
  347.     }
  348.     return chksum;
  349. }
  350. #endif
  353. #ifdef BOOT_LOAD//terry,2005/1/30 09:21PM
  354. #include "rommap_romb.h"
  355. /**************************************************************************
  356.  *  Function Name: rom_checksum                                           *
  357.  *  Purposes:                                                             *
  358.  *    At present, the funtion don't used                                  *
  359.  *  Descriptions:                                                         *
  360.  *    calculate rom check-sum (of first 512kbyte)                         *
  361.  *  Arguments:  None                                                      *
  362.  *  Returns: None                                                         *
  363.  *  See also: None                                                        *
  364.  **************************************************************************/
  365. UINT32 rom_checksum_per_kbyte(int st,int end)
  366. {
  367.     int i;
  368.     UINT32 chksum=0;    
  369.     UINT32 *p1;
  370.     UINT32 *q= (UINT32 *)(ROM_BASE_UNCACHED+ORG_BOOT_ROM_CHK_SUM);
  371.     
  372.     for (i=st;i<end; i++)
  373.     {
  374.         p1=(UINT32 *)( ROM_BASE_UNCACHED+(i*1024) );
  375.         //printf("-%x: %x-n",p1,*p1 );
  376.         chksum += *p1;
  377.         // delay_1ms(1000);
  378.     }
  379.     
  380.     //printf("nn == chksum:%x q:%x==nn\n",chksum,*q);
  381.     
  382.     if(*q==chksum) return 1;//goto boot rom
  383.     else return 0;
  384. }
  385. #endif
  387. /**************************************************************************
  388.  *  Function Name: init_timer                                             *
  389.  *  Purposes:                                                             *
  390.  *   1. setup STC 90kHz                                                   *
  391.  *   2. setup RTC 100Hz                                                   *
  392.  *   3. setup regs0->timer0_ctrl                                          *
  393.  *   4. setup timer2                                                      *
  394.  *   5. setup timer3                                                      *
  395.  *  Descriptions:                                                         *
  396.  *    reset following subsystems to a known state                         *
  397.  *  Arguments:  None                                                      *
  398.  *  Returns: None                                                         *
  399.  *  See also: None                                                        *
  400.  **************************************************************************/
  401. void    init_timer(void)
  402. {
  403.   // setup STC 90kHz
  404. #if defined(SPHE8202) || defined(SPHE1000)
  405.   regs0->stc_divisor    = (1<<15) | (150-1);
  406. #else
  407.   regs0->stc_divisor    = STC_DIVISOR;
  408. #endif
  410.   // setup RTC 100Hz
  411.   regs0->rtc_divisor    = 900-1;
  412. //terry,2004/2/17 06:08PM
  413. //if defined "SHOW_STANDBY_TIMER",timer0 would be used.suqiaoli modified 2004-2-26
  414. #if (defined(DVDRELEASE)|| !defined(TASK_GBG))&&!defined(SHOW_STANDBY_TIMER)
  415.   regs0->timer0_ctrl    = TIMER_CONFIG_STOP;
  417. #else
  419. #ifdef DVD_SERVO
  420. #ifdef EMU_MODE
  421.   regs0->timer0_ctrl    = TIMER_CONFIG_1ms;
  422. #else
  423.   regs0->timer0_ctrl    = TIMER_CONFIG_10ms;
  424. #endif
  425. #else
  426.   regs0->timer0_ctrl    = TIMER_CONFIG_4ms;
  427. #endif
  430. #endif
  434.   regs0->timer1_ctrl    = TIMER_CONFIG_STOP;
  437. #if 1
  438.   regs0->timer2_reload  = 0x4;
  439.   regs0->timer2_divisor = 0xffff;
  440.   regs0->timer2_ctrl    = 0;                // stop: this timer is used in performance meter
  441. #endif
  443. #ifdef SPHE1000
  444. #define TIMER3_PERIOD   0.01       // in second
  445. #define TIMER3_PRES     (SYSCLK/1000000)
  446. #else
  447. #define TIMER3_PERIOD   0.002       // in second
  448. #define TIMER3_PRES     2000
  449. #endif
  451.   regs0->timer3_reload  = (unsigned)((TIMER3_PERIOD*SYSCLK)/TIMER3_PRES) - 1;
  452.   regs0->timer3_divisor = TIMER3_PRES-1;
  453.   regs0->timer3_ctrl    = 3;                // go and reload
  454. }
  457. #ifdef DVD_SERVO
  458. void ServoDecInit(void);
  459. void ResetInterfaceProc(void);
  460. #endif
  463. #ifndef DVDRELEASE
  464. #define SUPPORT_UART0_INTR
  465. //#define SUPPORT_UART1_INTR
  466. #define write_stamp(n)  (regs0->stamp = (n))
  467. #endif
  469. #ifndef write_stamp
  470. #define write_stamp(n)  ((void)0)
  471. #endif
  473. enum    {
  474.     STAMP_RESET_START           = 0x01,
  475.     STAMP_RESET_SYSTEM,
  476.     STAMP_CHANGE_SYSCLK,
  477.     STAMP_LOAD_MODULE_OTHER,
  478.     STAMP_LOAD_MODULE_CDROM,
  479.     STAMP_DISABLE_VIDEO,
  480.     STAMP_ENABLE_INTR_0,
  481.     STAMP_RESET_WATCHDOG,
  482.     STAMP_LOAD_MODULE_MPEG,
  483.     STAMP_LOAD_MODULE_AP,
  484.     STAMP_LOAD_MODULE_AP2,
  485.     STAMP_LOAD_MODULE_FREE,
  486.     STAMP_RESET_OSD,
  487.     STAMP_CONFIG_MEMORY,
  488.     STAMP_ENABLE_INTR_1,
  489.     STAMP_RESET_FINISHED,
  490. };
  493. //
  494. // FUNCTION
  495. // reset_all
  496. //
  497. // DESCRIPTION
  498. // reset all, including some interface.
  499. //
  500. // *DISABLE INTR
  501. // *REGF + ROMIF setup
  502. // *EMUIO/UART setup (interrupt not yet enabled)
  503. // *APLL setup (before GPIO for correct XCK)
  504. // *GPIO setup
  505. // *SDRAM size setup
  506. // *TIMER setup
  507. // *SDRAM memory mapping configuration
  508. // *VIDDEC
  509. // *SUP
  510. // *MULTI-TASK
  511. // *ENABLE INTR
  512. // *IOP
  513. // *IR      (iop)
  514. // *VFD     (iop)
  515. // *TV-encoder  (iop)
  516. // *DAC     (iop)
  517. //
  518. //
  519. /**************************************************************************
  520.  *  Function Name: reset_all_enter                                        *
  521.  *  Purposes:                                                             *
  522.  *   1. disable CPU-level intr_enable                                     *
  523.  *   2. disable watchdog                                                  *
  524.  *   3. write stamp Start                                                 *
  525.  *  Descriptions:                                                         *
  526.  *    reset Start                                                         *
  527.  *  Arguments:  None                                                      *
  528.  *  Returns: None                                                         *
  529.  *  See also: None                                                        *
  530.  **************************************************************************/
  532. static void
  533. reset_all_enter(void)
  534. {
  535.     // disable CPU-level intr_enable
  536.     cpu_intr_disable();
  538.     // disable watchdog, we are about to reset all sub-systems
  539.     watchdog_onoff(0);
  541. #ifdef  UART0_SHARE_WITH_UART1
  542.     sft_uart0_share_uart1_pins();
  543. #endif
  545. #ifdef  UART_SWAP //axel swap uart0 and uar1 2004/10/29
  546.     sft_uart_swap();
  547. #endif
  551.     write_stamp(STAMP_RESET_START);
  552. }
  554. /**************************************************************************
  555.  *  Function Name: reset_all_exit                                         *
  556.  *  Purposes:                                                             *
  557.  *   1. report fpga/sdram/rom/anchors                                     *
  558.  *   2. test sdram                                                        *
  559.  *   3. write stamp finished                                              *
  560.  *  Descriptions:                                                         *
  561.  *      reset Finished                                                    *
  562.  *  Arguments:  None                                                      *
  563.  *  Returns: None                                                         *
  564.  *  See also: None                                                        *
  565.  **************************************************************************/
  566. static void
  567. reset_all_exit()
  568. {
  569.     //
  570.     // report/testing
  571.     //
  572. #ifndef DVDRELEASE
  573. //    report_fpga_status();
  574. //    report_sdram_parameter();
  575. //    report_rom_parameter();
  576. //    report_anchors();
  577. #endif
  579. #ifdef  DRAM_TEST
  580. #include "tstsdram.c"//4-3-30 21:40
  582.     test_sdram();
  583. #endif
  585.     //
  586.     // finished
  587.     //
  588.     write_stamp(STAMP_RESET_FINISHED);
  590.     if (check_chipinfo(4)==0) return -1;
  591. }
  592. /**************************************************************************
  593.  *  Function Name: reset_all_enable_intr_only_uart                        *
  594.  *  Purposes:                                                             *
  595.  *   1. reset interrupt flags                                             *
  596.  *   2. INTERRUPT for bootstrap is initialized                            *
  597.  *   3. enable CPU-level intr_mask (IP2/IP3)                              *
  598.  *   4. enable CPU-level intr_enable                                      *
  599.  *  Descriptions:                                                         *
  600.  *      Currently only UART is enabled during bootstrap (if required).    *
  601.  *  Arguments:  None                                                      *
  602.  *  Returns: None                                                         *
  603.  *  See also: None                                                        *
  604.  **************************************************************************/
  605. static void
  606. reset_all_enable_intr_only_uart()
  607. {
  608.     //
  609.     // reset interrupt flags
  610.     regs0->intr_flag        = -1;
  611.     regs0->intr1_flag       = -1;
  613.     //
  614.     // INTERRUPT for bootstrap is initialized here.
  615.     // Currently only UART is enabled during bootstrap (if required).
  616.     //
  617.     regs0->intr_mask = 0
  618. #ifdef  SUPPORT_UART0_INTR
  619.         | INTR_UART0_INT
  620. #endif
  621. #ifdef  SUPPORT_UART1_INTR
  622.         | INTR_UART1_INT
  623. #endif
  624.         ;
  626.     regs0->intr1_mask = 0
  627.         ;
  629.     cpu_set_intr_mask((1<<2)|(1<<3));       // enable CPU-level intr_mask (IP2/IP3)
  630.     cpu_intr_enable();                      // enable CPU-level intr_enable
  631. }
  633. /**************************************************************************
  634.  *  Function Name: reset_all_enable_intr_all                              *
  635.  *  Purposes:                                                             *
  636.  *   1. reset intr_flag (bitwise-clear-upon-write-1)                      *
  637.  *   2. reset intr_mask                                                   *
  638.  *  Descriptions:                                                         *
  639.  *      enable normal interrupt processing                                *
  640.  *  Arguments:  None                                                      *
  641.  *  Returns: None                                                         *
  642.  *  See also: None                                                        *
  643.  **************************************************************************/
  644. static void
  645. reset_all_enable_intr_all(void)
  646. {
  647.     //
  648.     // reset intr_flag (bitwise-clear-upon-write-1)
  649.     regs0->intr_flag        = -1;
  650.     regs0->intr1_flag       = -1;
  652. #ifndef DVDRELEASE
  653.     regs0->sdctrl_int       = 0;
  654.     regs0->sdctrl_int_mask  = 0x80; // sdram over-range
  655. #endif
  657.     // reset intr_mask
  658.     regs0->intr_mask  = 0
  659.         | INTR_FIELD_END | INTR_FIELD_START | INTR_PIC_END
  660.         | INTR_RI_WATCHDOG
  661.         | INTR_DECERR
  662.         | INTR_TIMER0
  663.         | INTR_TIMER1
  664. #if defined(SPHE1000) && defined(SUPPORT_USB)
  665.         | INTR_USB
  666. #endif
  667. #ifdef  SUPPORT_UART0_INTR
  668.         | INTR_UART0_INT
  669. #endif
  670. #ifdef  SUPPORT_UART1_INTR
  671.         | INTR_UART1_INT
  672. #endif
  673. #ifdef SUPPORT_UART_UPGRADE
  674.         | INTR_UART1_INT // for performing flash upgrading via UART
  675. #endif
  676. #ifdef SUPPORT_UART_COMMAND //kenny support uart to communicate with external MCU
  677.         | INTR_UART1_INT // for uart command
  678. #endif
  679. #ifdef DVD_SERVO
  680.         | INTR_H_PIO_INT
  681. #endif
  682. #ifdef STB_2_0
  683.         | INTR_RISC_INT3
  684. #endif
  686. #ifdef DVD_SERVO
  687.         | INTR_SRV_INT3
  688.         | INTR_SRV_INT2
  689.         | INTR_SRV_INT1
  690.         | INTR_SRV_INT0
  691. #endif
  692.             ;
  694.   regs0->intr1_mask  = 0
  695.         | INTR1_LSWITCH_INTR_FLAG   // lswitch watchdog
  696. #ifdef DVD_SERVO
  697.         | INTR1_TIMER3B             // timer for servo use
  698. #endif
  699.         | INTR1_TIMERW              // timer of watchdog
  700. #ifndef DVDRELEASE
  701. #ifdef ENABLE_SDRAM_OV_RANGE_INTR
  702.         | INTR1_SD                  // sdram-controller out-of-range
  703. #endif
  704. #endif
  705. #ifdef SPHE8202
  706.         | INTR1_USB                 // USB
  707. #endif
  708. #if 0
  709.         // not-used
  710.         | INTR1_TIMER2A
  711.         | INTR1_TIMER2B
  712.         | INTR1_TIMER3A
  713. #endif
  714.             ;
  715. }
  718. #ifdef CS4360  //huziqin 2004-2-26
  719. #define CS4360_ADDR   0x20
  720. /*
  721. mode control 1:
  722. addr 01h
  723. AMUTE  7
  724. DIF  4-6
  725. DEM 2-3
  726. FM  0-1
  728. mode control 2:
  729. addr 0ch
  730. SZC  6-7
  731. CPEN 5
  732. PDN  4
  733. POPG 3
  734. FREEZE  2
  735. MCLKDIV  1
  736. SNGLVOL  0
  737. */
  738. /**************************************************************************
  739.  *  Function Name: config_cs4360                                          *
  740.  *  Purposes:                                                             *
  741.  *     cofig cs4360 mode                                                  *
  742.  *  Descriptions:                                                         *
  743.  *     config_cs4360                                                      *
  744.  *  Arguments:                                                            * 
  745.  *    mode control 1:                                                     * 
  746.  *    addr 01h                                                            * 
  747.  *    AMUTE  7                                                            * 
  748.  *    DIF  4-6                                                            * 
  749.  *    DEM 2-3                                                             * 
  750.  *    FM  0-1                                                             * 
  751.  *                                                                        * 
  752.  *    mode control 2:                                                     * 
  753.  *    addr 0ch                                                            * 
  754.  *    SZC  6-7                                                            * 
  755.  *    CPEN 5                                                              * 
  756.  *    PDN  4                                                              * 
  757.  *    POPG 3                                                              * 
  758.  *    FREEZE  2                                                           * 
  759.  *    MCLKDIV  1                                                          * 
  760.  *    SNGLVOL  0                                                          * 
  761.  *  Returns: None                                                         *
  762.  *  See also: None                                                        *
  763.  **************************************************************************/
  764. void config_cs4360(void)
  765. {
  766.     BYTE data;
  767.     int res;
  768.     /*mode ctrl 2*/
  769.     data = 0xa8;
  770.     res = WriteToI2c(CS4360_ADDR, 0x0c, &data, 1);
  771.     /*mode ctrl 1*/
  772.     data = 0x90;
  773.     res = WriteToI2c(CS4360_ADDR, 0x01, &data, 1);
  774.     //printf("config 4360 res == %dn ",res);
  775. }
  776. #endif //cs4360
  778. /**************************************************************************
  779.  *  Function Name: reset_tvdac                                            *
  780.  *  Purposes:                                                             *
  781.  *   1. disable video dac                                                 *
  782.  *   2. enable osd                                                        *
  783.  *   3. enable tv-encoder                                                 *
  784.  *  Descriptions:                                                         *
  785.  *      reset TV dac                                                      *
  786.  *  Arguments:  None                                                      *
  787.  *  Returns: None                                                         *
  788.  *  See also: None                                                        *
  789.  **************************************************************************/
  790. static inline void
  791. reset_tvdac(void)
  792. {
  793. #if 0
  794.     regs0->tv_mode[5] = 0x60bf;
  795.     regs0->tv_mode[5] = 0x003f;
  796.     delay_1ms(1000);
  797. #endif
  799.     //
  800.     regs0->vpp_bg_y     = 0x00;
  801.     regs0->vpp_bg_cb_cr = 0x8080;
  802.     regs0->dis_x_size = 0;
  803.     regs0->dis_y_size = 0;
  805.     // enable osd
  806.     regs0->osd_mode[0]  = 0x8000;
  807.     regs0->osd_tv_std   = 0;
  809.     // enable tv-encoder
  810.     regs0->tv_mode[0]   = 0x0400;
  811.     regs0->tv_mode[2]   = 0x0000;
  812.     regs0->tv_mode[5]   &= ~0x6080;     // enable tv-encoder
  814.     regs0->tv_mode[5]   &= ~0x003f;     // enable DAC
  815. #ifdef  SPHE8202
  816.     regs0->tv_dac[0]    = (6<<6) | (6<<3) | (0<<0);
  817.     regs0->tv_dac[1]    = (6<<6) | (6<<3) | (6<<0);
  818. #endif
  819. }
  820. /**************************************************************************
  821.  *  Function Name: reset_vpp_par                                          *
  822.  *  Purposes:                                                             *
  823.  *      change vpp_par_mode                                               *
  824.  *  Descriptions:                                                         *
  825.  *      VPP Pixel Aspect Ratio                                            *
  826.  *  Arguments:  None                                                      *
  827.  *  Returns: None                                                         *
  828.  *  See also: None                                                        *
  829.  **************************************************************************/
  830. void reset_vpp_par()
  831. {
  832.     int flag=0;
  834. #ifdef PAR_MP_FORCE_SQUARE
  835.     flag |= VPP_PAR_MP_FORCE_SQUARE;
  836. #endif
  837. #ifdef PAR_MP4_FORCE_SQUARE
  838.     flag |= VPP_PAR_MP4_FORCE_SQUARE;
  839. #endif
  840. #ifdef PAR_MP4_GUESS_43TV
  841.     flag |= VPP_PAR_MP4_GUESS_43TV;
  842. #endif
  843. #ifdef PAR_MP4_REVERSE_169TV
  844.     flag |= VPP_PAR_MP4_REVERSE_169TV;
  845. #endif
  847.     setup_vpp_par_mode(flag);
  848. }
  851. #if defined(DVB1000_NON_OS) && defined(SUPPORT_USB)
  852. void reset_usb()
  853. {
  854. UINT32 *iptr;
  856. iptr = (UINT32*)0xbc030004;
  857. *iptr = 0x1;  //??
  859. iptr = (UINT32*) 0xbc030020;
  860. *iptr = 0x1c020000;
  861. delay_1ms(1);
  863. iptr = (UINT32*)0xbc020014;
  864. *iptr = 0x27777;
  866. iptr = (UINT32*)0xbc030004;
  867. *iptr = 0x0;
  868. }
  869. #endif //#if defined(DVB1000_NON_OS) && defined(SUPPORT_USB)
  871. #ifdef  SPHE8202 //nono
  872. UINT16 gpGPIOini;
  873. #endif
  875. /**************************************************************************
  876.  *  Function Name: reset_all                                              *
  877.  *  Purposes:                                                             *
  878.  *   1. DISABLE INTR                                                      *
  879.  *   2. REGF + ROMIF setup                                                *
  880.  *   3. EMUIO/UART setup (interrupt not yet enabled)                      *
  881.  *   4. APLL setup (before GPIO for correct XCK)                          *
  882.  *   5. GPIO setup                                                        *
  883.  *   6. SDRAM size setup                                                  *
  884.  *   7. TIMER setup                                                       *
  885.  *   8. SDRAM memory mapping configuration                                *
  886.  *   9. VIDDEC                                                            *
  887.  *   10. SUP                                                              *
  888.  *   11. MULTI-TASK                                                       *
  889.  *   12. ENABLE INTR                                                      *
  890.  *   13. IOP include IR 、VFD、TV-encoder、DAC                            *
  891.  *  Descriptions:                                                         *
  892.  *      reset all, including some interface.                              *
  893.  *  Arguments:  None                                                      *
  894.  *  Returns: None                                                         *
  895.  *  See also: None                                                        *
  896.  **************************************************************************/
  897. void reset_all(void)
  898. {
  900.     #ifdef  SPHE8202            // longson 2004.02.16
  901.     regs0->sft_cfg4 = 0x6073;   // disable  SC1_OUT and TRAY_OUT
  902.     regs0->gpio_oe[0] = 0x0c;   // enable GPIO[2] and GPIO[3] output
  903.     #endif
  905.     //
  906.     // at this time only reset.c/crt0.S/lexra.S/sysmain.c are assumed to
  907.     // be in memory
  908.     //
  910.     //
  911.     // load code to sdram if required
  912.     //
  913. #ifdef SPHE1000
  914. #if defined(LOAD_OTHER) || defined(ROM_SDRAM_SHARE_BUS)
  915.     LoadModual(MODUAL_OTHER);           write_stamp(STAMP_LOAD_MODULE_OTHER);
  916. #endif
  918.     msg_init();
  920. #endif
  921.     //
  922.     // prolog
  923.     reset_all_enter();
  925.     //
  926.     // reset basic system (again)
  927.     reset_system();
  928.     write_stamp(STAMP_RESET_SYSTEM);
  929.     #ifndef START_NO_VPP_DELAY //linrc add for nintaus 2004-7-12 19:51
  930.     reset_tvdac();
  931.     #endif
  932. #ifdef POWER_ON_VIDEO_DAC_OFF
  933.     tv_dacoff( (0x01<<0)|(0x01<<1)|(0x01<<2)|(0x01<<3)|(0x01<<4)|(0x01<<5) );
  934. #endif//POWER_ON_VIDEO_DAC_OFF
  936.     //
  937.     // change system clock from 108MHz to required frequency
  938. #ifndef USE_DEFAULT_CLOCK //2004/10/21 wjzhang , sphe1000B(stb-dvd): use default clock
  939. #ifdef SPHE1000
  940.     {
  941.       UINT32 CFG_board_config = regs0->hw_cfg;
  942.       if (CFG_board_config == 9) regs0->sft_cfg2 |= (3<<14);
  943.       reset_change_sysclk();              write_stamp(STAMP_CHANGE_SYSCLK);
  944.       if (CFG_board_config == 9) regs0->sft_cfg2 &= ~(3<<14);
  945.     }
  946. #else
  947.     reset_change_sysclk();              write_stamp(STAMP_CHANGE_SYSCLK);
  948. #endif
  949. #endif
  950.     //
  951.     // load code to sdram if required
  952.     //
  953. #ifndef SPHE1000
  954. #if defined(LOAD_OTHER) || defined(ROM_SDRAM_SHARE_BUS)
  955.     LoadModual(MODUAL_OTHER);           write_stamp(STAMP_LOAD_MODULE_OTHER);
  956. #endif
  957. #endif
  958. #ifdef TCL_STANDBY
  959.     regs0->sft_cfg1 &= ~(0x1 << 3);//gpio 3 enable
  960.     regs0->gpio_master[ 3/16 ] |= 0x1 << (3%16);//gpio 3 for mips
  961.     regs0->gpio_oe[ 3/16 ] |= 0x1 << (3%16);//output
  962.     regs0->gpio_out[3/16 ] |= (0x1 << (3%16));
  963.     //delay_1ms(500);
  965.     regs0->gpio_master[ 2/16 ] |= 0x1 << (2%16);//gpio 2 for mips
  966.     regs0->gpio_oe[ 2/16 ] &= ~(0x1 << (2%16));//input
  967.     //delay_1ms(500);
  968. #endif
  969.     LoadModual(MODUAL_AP);              write_stamp(STAMP_LOAD_MODULE_AP);
  970.     LoadModual(MODUAL_FREE);            write_stamp(STAMP_LOAD_MODULE_FREE);
  971.     LoadModual(MODUAL_CDROM);           write_stamp(STAMP_LOAD_MODULE_CDROM);
  973.     //
  974.     // at this time all essential code is decompressed and loaded.
  975.     // OTHER/AP/FREE/CDROM code are loaded
  976.     //
  978.     //
  979.     // blank display
  980.     disable_video();
  981.     write_stamp(STAMP_DISABLE_VIDEO);
  984. #ifdef SUPPORT_AUDIO_RESET
  985.     GpioResetAudio();
  986. #endif
  989.     //720 generate DAC clock first, Jeff 20020712
  990. #ifndef DVD728
  991.     // setup audio clockgen (to correct format and XCK)
  992.     hwsetup_audio_clkgen_init();
  993. #endif
  996. #ifdef  SUPPORT_EPP
  997.     // reset emuio fifo
  998.     reset_io();
  999. #endif
  1001. #ifdef  SPHE8202
  1002. //    UART0_set_baudrate(BAUDCC(115200, 135000000));
  1003. //    UART0_set_baudrate(BAUDCC(115200, 128250000));
  1004. //    UART0_set_baudrate(BAUDCC(115200, 121500000));
  1005. //    UART0_set_baudrate(BAUDCC(115200, 114750000));
  1006. //    UART0_set_baudrate(BAUDCC(115200, 108000000));
  1007. #endif
  1009. #ifdef SUPPORT_UART_COMMAND //kenny support uart to communicate with external MCU
  1010.     reset_uart();
  1011. #endif
  1014. #if defined(DVDRELEASE) && !defined(SPHE1000)
  1015.     #if defined(QSI_SHOW_ERR_RATE)
  1016.         UART0_set_baudrate(BAUDCC(115200, 121500000));
  1017.         psprintf(linebuf,"------------Release UART------------n");         
  1018.         UART0_puts(linebuf);
  1019.     #elif defined(UART_WITHOUT_DEBUG_MODE)//axel 2004/10/19 for the communication with external MCU
  1020.         UART0_set_baudrate(BAUDCC(9600, 121500000));
  1021.         //psprintf(linebuf,"------------Release UART------------n");         
  1022.         //UART0_puts(linebuf);
  1023.     #else
  1024.     extern void sft_hvsync();//4-4-6 0:43
  1025.     //sft_hvsync(1);
  1026.     sft_hvsync();       //freyman 2004-2-27 12:01
  1027. #endif
  1028. #endif
  1029. #ifdef UART_SWAP //axel swap uart0 and uar1 2004/10/29
  1031. UART1_set_baudrate(BAUDCC(115200, 121500000));                   
  1032. psprintf(linebuf,"------------Release UART------------n");    
  1033. UART1_puts(linebuf);                                           
  1035. #endif
  1037. #if 0
  1038.     regs0->sft_cfg2 |= 1<<15;
  1039.     UART0_set_baudrate(BAUDCC(115200, 121500000));
  1040.     UART1_set_baudrate(BAUDCC(115200, 121500000));
  1041.     UART0_puts("enable UART0n");
  1042.     UART1_puts("enable UART1n");
  1043. #endif
  1045.     //
  1046.     // Enable UART interrupt here (to enable emuio access)
  1047.     reset_all_enable_intr_only_uart();  write_stamp(STAMP_ENABLE_INTR_0);
  1049. #if defined(SPHE8202)//nono
  1051.     #ifdef MP_BOARD_256_PIN_NON_SHARE
  1052.     gpGPIOini = 0xff;
  1053.     #else
  1054.     gpGPIOini = 0;
  1055.     #endif
  1057. #endif//SPHE8202
  1058.     //
  1059.     // hardware initialization
  1060. #ifdef SPHE1000
  1061.     reset_gpio_1000();
  1062. #else
  1063.     reset_gpio();         // setup GPIO directions
  1064. #endif
  1066. #if 0//def SUPPORT_UART_COMMAND    //inform external MCU Power is ok and releas vfd and ir
  1067.     Inform_MCUOK();
  1068. #endif
  1070. #ifdef SYS_TEST_REG_00
  1071.     sys_test_reg_00=0x7;
  1072. #endif
  1074. #ifdef SUPPORT_POWER_STB //jinping for power standby 2002-7-6 17:56
  1075.     POWER_STB_SET( STANDBY ); // power on;
  1076. #endif
  1078. #ifdef SUPPORT_AMP // for SVA DVD solution
  1079.     AMP_MUTE_SET(1);  // tripth amp. high mute; mute amp.
  1080.     amp_onoff_flag = 0;//default is 0. 0:amp off,out to TV; 1:amp on, out to amp
  1081. #endif
  1084.     //
  1085.     // Load other code modules
  1086.     LoadModual(MODUAL_MPEG);            write_stamp(STAMP_LOAD_MODULE_MPEG);
  1087.     LoadModual(MODUAL_AP2);             write_stamp(STAMP_LOAD_MODULE_AP2);
  1089.     //
  1090.     // setup framebuffer/memory initial configuration
  1091.     enable_portable_bonding(0);
  1093.     #ifdef PORTABLE_DVD//jhuang 2003/12/3
  1094.         memory_config_saved = IOP_CONFIG_PDVD;
  1095.         is_iop_ready();
  1097.     #endif
  1099.     memory_config_saved = 0xff;
  1100.     config_memory(MEMORY_DVD_NTSC);
  1101.     write_stamp(STAMP_CONFIG_MEMORY);
  1103.     //
  1104.     // setup timer
  1105.     init_timer();
  1107.     //
  1108.     // initialize audio/video/sup decoder
  1109.     // init_audio();  //terry mark it on 2002/2/24 02:40PM ,avoid A/D to be turned on at startup
  1110.     init_video_decoder();
  1111.     init_sup();
  1112.     pe_init();
  1114.     //
  1115.     // Abort previous decoding tasks
  1116.     MacroAbort();
  1118.     //
  1119.     // Reset interrupt routines
  1120.     // atapi: (not used now)
  1121.     // task: task-switching
  1122.     reset_atapi_intr();
  1123. #ifndef DVDRELEASE
  1124.     reset_task();
  1125. #endif
  1127.     //
  1128.     // Reset watchdog
  1129.     watchdog_renew(0xffff);     // n*16/90k, first time we set to maximum (about 12-second)
  1130.     watchdog_onoff(1);
  1131.     write_stamp(STAMP_RESET_WATCHDOG);
  1133.     //
  1134.     // Enable all used interrupts
  1135.     reset_all_enable_intr_all();            write_stamp(STAMP_ENABLE_INTR_1);
  1137.     //
  1138.     // Initialize OSD (before enable TV-encoder)
  1139.     reset_osd();                            write_stamp(STAMP_RESET_OSD);
  1141.     //
  1142.     // basic service on
  1143.     // interrupt has been on
  1144.     //
  1146.     //
  1147.     //  IOP     IOP     IOP     IOP     IOP     IOP
  1148.     //
  1150.     // setup iop
  1151.     reset_status_puts("setup iop.n");
  1152.     reset_iop();
  1154.     // iop service #1
  1155.     reset_status_puts("setup ir inf.n");
  1156.     reset_ir();
  1158.     // iop service #2
  1159. #if defined(SUPPORT_VFD)&&defined(SUPPORT_VFD_PANEL) //lijd 2004-12-4 11:39
  1160.     reset_status_puts("setup vfd inf.n");
  1161.     reset_vfd();
  1162. #endif
  1164. #if defined(GPIO_KEY_LIGHT)
  1165.     init_keylight_io();
  1166. #endif
  1168.     // iop service #3 (if 721/725)
  1169.     reset_status_puts("setup tv inf.n");
  1171. #ifdef DVD728
  1172.     #define NO_SYNC_ON_G
  1173.     
  1174.     #ifdef NO_SYNC_ON_G
  1175.     setup_sync_on_G(0);     // support SCART TV, no sync signal on G channel
  1176.     #endif
  1178.     setup_display(0,1);     // FIX: this is for osd/tv-encoder to keep coherent.
  1179. //    delay_1ms(200); //terry,2003/8/11 11:44AM
  1180.     /*
  1181.     #ifdef BBK_DVD//zhaoyanhua add 2003-11-24 14:23
  1182.         tv_init_output();
  1183.     #endif
  1184.     */
  1185. #else
  1186.     tv_setup();
  1187. #endif
  1189. #ifdef DIGITAL_VIDEO_OUT
  1190. #ifdef SPHE8202
  1191. #ifdef MP_BOARD_256_PIN_NON_SHARE
  1192. #ifdef CCIR656_TYPE1
  1193. regs0->sdc_data_cnt[6][0] |= (0x0e);//Disable ROM_A20(Pin225),ROM_A21(Pin226),ROM_A22(Pin227) as GPIO92,93,94
  1194. regs0->sdc_data_cnt[6][0] |= (0x1 <<4);  //CCIR656 ENABLE on Pin225~233
  1195. #elif defined(CCIR656_TYPE2) 
  1196. regs0->sft_cfg7 |= (0x1 << 4);    //rbhung Only for TEST
  1197. regs0->sft_cfg3 &= ~(0x1 << 5);   //Disable AUD4 as GPIO50 for TV_CLK ,pin 193
  1198. #endif
  1199. #endif //MP_BOARD_256_PIN_NON_SHARE
  1200. #else //8210
  1201. regs0->sft_cfg6 |= (0x1 << 14); //CCIR656 ENABLE
  1202. regs0->sft_cfg3 |= (0x7 << 9);  //CCIR SYNC FROM PIN185,186
  1203. regs0->sft_cfg2 &= ~(0xf << 5);     //UART1 SELECT
  1204. //regs0->osd_tv_out |=(0x1 << 1);   //CbCr SWAP
  1205. regs0->osd_tv_out |=(0x1 << 3); //CCIR EDGE SELECT
  1206. //regs0->sft_cfg2 |= (0x7 << 9);    //TV_LCD RGB ENABLE
  1207. //regs0->ri_misc_b0 |= (0x3<<11);   //VIDEO CLK SELECT
  1208. #endif
  1209. #endif
  1211.   // iop service #4
  1212. #ifdef  SETUP_DAC
  1213.     reset_status_puts("setup dac.n");
  1214.     dac_setup();
  1215. #endif
  1217.     // iop service #5
  1218. #if defined(PT2322)||defined(PT2320)
  1219.     reset_status_puts("setup pt2322.n");
  1220.     init_pt_audio();
  1221. #endif
  1223. #if defined(TAS3001_AMP)||defined(NO_AMP_ONLY_TUNER)     //use TI 3001  amplifier  2-8-22 12:58
  1224.     {
  1225.   //    extern int AudioIOControl(UINT16 wCode, BYTE cType, UINT16 wParam); //kenny mark it
  1226.    //    AudioIOControl(2, 15, 0);  //set 720 pcm volume 2==VOLUME,15=max volume
  1227.         regs0->gpio_sel |= GPIOSEL_10_GPIOS;   //use gpio22,23 communicate with MCU// jason 2-11-4 19:05
  1228.         regs0->gpio_out[23/16]&=(~(3<<(22%16)));
  1229.         regs0->gpio_oe[23/16] |=(3<<(22%16));
  1230.     #ifndef NO_AMP_ONLY_TUNER
  1231.        tas3001_reset();
  1232. #endif
  1233.     }
  1234. #endif
  1235. #if defined(TAS5026_AMP)     //use TI 3001  amplifier  2-8-22 12:58
  1236.     {
  1237.   //    extern int AudioIOControl(UINT16 wCode, BYTE cType, UINT16 wParam); //kenny mark it
  1238.    //    AudioIOControl(2, 15, 0);  //set 720 pcm volume 2==VOLUME,15=max volume
  1239.        tas5026_reset();
  1240.     }
  1241. #endif
  1243.     // setup dsp port
  1244.     {
  1245.         int i;
  1246.         for (i=0;i<16;i++) regs0->dsp24_port[i] = 0; //Jeff 20011029
  1247.     }
  1250. #ifdef  SETUP_UART1
  1251.     // enable UART1
  1252.     {
  1253.         UINT32 u;
  1255.         // setup baudrate
  1256.         UART1_set_baudrate(UART_BAUD_57600);
  1258.         // change pinmux
  1259.         u = regs0->sft_cfg2;
  1260.         u = (u & ~(0x0f<<5)) | (0x09<<5);
  1261.         regs0->sft_cfg2 = u;
  1262.         while (1) UART1_puts("test uart #1n");
  1263.     }
  1264. #endif
  1266. /*
  1267.     // servo testing code
  1268. #ifdef DVD_SERVO
  1269. #ifndef SOFT_ATAPI //DVD_SERVO
  1270.     ServoDecInit(); // barry add for init servo
  1271.     ResetInterfaceProc();
  1272. #endif
  1273.     regs0->emu_cfg[16] = 0x00;              // ROM-pattern disable
  1274.     regs0->rf_servo_band_en = 0x00;         //
  1275. #endif
  1276. */
  1278. #ifdef VOLUME_RECODE        //gerry add it before init audio,2004-7-6 9:36
  1279.     volume_init();
  1280. #endif//VOLUME_RECODE
  1282.     //
  1283.     // initialize audio, put it here to avoid CS4334 noise
  1284.     AUDIF_Init_Audio();//2004AUDDRV init_audio();
  1286.     //
  1287.     // ???
  1288. #ifdef CS8403_ENABLE
  1289.    #ifdef SPHE8202
  1290.    init_cs8403a__();
  1291.    #else
  1292.     regs0->gpio_master[55 / 16] |= (0x1 << (55 % 16));  //pin155, GPIO[55]
  1293.     regs0->gpio_oe[55 / 16] |= (0x1 << (55 % 16));
  1294.     regs0->gpio_out[55 / 16] |= (0x1 << (55 % 16));
  1295.     init_cs8403a__();
  1296.    #endif
  1297. #endif
  1299. #ifdef PCM1742 //Jeff 20030917
  1300.     dac_turn_on();
  1301. #endif
  1303. #ifdef CS4360 //huziqin
  1304.     //printf("config 4360n");
  1305.     config_cs4360();
  1306. #endif
  1308.     // VPP Pixel Aspect Ratio
  1309.     reset_vpp_par();
  1311.     //
  1312.     // postlog
  1313. #ifdef PMP_MCU810        ////////add to wirte IR head H/L and keycode --yangli   2004-11-11
  1314.       
  1315.        SendIRIDPowerKeyToMCU();       
  1316. #endif 
  1317. #ifdef PMP_Video_Onlycvbs    ///yangli 2004-11-29.add to pmp video out only cvbs
  1318.     tv_dacoff(TV_DAC_B|TV_DAC_C|TV_DAC_D|TV_DAC_E|TV_DAC_F);//only cvb is on
  1319.  #endif
  1321. #ifdef IC_8202E
  1322. regs0->tv_mode[4] = 0x1000;    // turn off 54Mhz upsampling
  1323. regs0->g21_reserved[4] = 0x0; // turn off 108Mhz upsampling
  1324. tv_setup_TV8202E(1); // setup TV kernel for 9992
  1325. #else
  1326. tv_setup_TV8202E(0);
  1327. #endif // IC_8202E
  1329. #ifdef SPHE1000
  1330. #ifdef HE1001_TUNER //yarco 20041202
  1331. regs0->sft_cfg3 &= 0xffcf; //disable ATAPI
  1332. regs0->sft_cfg2 = (regs0->sft_cfg2 & 0xfff1) | 0x06; //select TS interface
  1333. #endif
  1334. #endif
  1336.     reset_all_exit();
  1338.     #if defined(DVB1000_NON_OS) && defined(SUPPORT_USB)
  1339.     reset_usb();
  1340.     #endif
  1341. }
  1343. /**************************************************************************
  1344.  *  Function Name: reset_set_uart0_baudrate                               *
  1345.  *  Purposes:                                                             *
  1346.  *      reset baudrate of uart0                                           *
  1347.  *  Descriptions:                                                         *
  1348.  *      there are 9 type baudrate of uart0                                *
  1349.  *  Arguments:  None                                                      *
  1350.  *  Returns: 0                                                            *
  1351.  *  See also: None                                                        *
  1352.  **************************************************************************/
  1353. static  inline  void    reset_set_uart0_baudrate(void)
  1354. {
  1355. #if     defined(F135)
  1356.     UART0_set_baudrate(BAUDCC(115200, 135000000));
  1357. #elif   defined(F128_25)
  1358.     UART0_set_baudrate(BAUDCC(115200, 128250000));
  1359. #elif   defined(F121_5)
  1360.     UART0_set_baudrate(BAUDCC(115200, 121500000));
  1361. #elif   defined(F114_75)
  1362.     UART0_set_baudrate(BAUDCC(115200, 114750000));
  1363. #elif   defined(F108)
  1364.     UART0_set_baudrate(BAUDCC(115200, 108000000));
  1365. #elif   defined(F101_25)
  1366.     UART0_set_baudrate(BAUDCC(115200, 101250000));
  1367. #elif   defined(F94_5)
  1368.     UART0_set_baudrate(BAUDCC(115200,  94500000));
  1369. #elif   defined(F87_75)
  1370.     UART0_set_baudrate(BAUDCC(115200,  87750000));
  1371. #elif   defined(F81)
  1372.     UART0_set_baudrate(BAUDCC(115200,  81000000));
  1373. #endif
  1374. }
  1376. /**************************************************************************
  1377.  *  Function Name: reset_change_sysclk                                    *
  1378.  *  Purposes:                                                             *
  1379.  *      change system clock                                               *
  1380.  *  Descriptions:                                                         *
  1381.  *       there are 19 type of system clock                                *
  1382.  *  Arguments:  None                                                      *
  1383.  *  Returns: 0                                                            *
  1384.  *  See also: None                                                        *
  1385.  **************************************************************************/
  1386. int
  1387. reset_change_sysclk(void)
  1388. {
  1389. #if     defined(F168_75) //wrwu, 2005-01-21, for over-clock
  1390.     change_system_clock(25);
  1391. #elif     defined(F162)
  1392.     change_system_clock(24);
  1393. #elif     defined(F155_25)
  1394.     change_system_clock(23);
  1395. #elif     defined(F148_5)
  1396.     change_system_clock(22);
  1397. #elif     defined(F141_75)
  1398.     change_system_clock(21);
  1399. #elif     defined(F135)
  1400.     change_system_clock(20);
  1401. #elif   defined(F128_25)
  1402.     change_system_clock(19);
  1403. #elif   defined(F121_5)
  1404.     change_system_clock(18);
  1405. #elif   defined(F114_75)
  1406.     change_system_clock(17);
  1407. #elif   defined(F108)
  1408.     change_system_clock(16);
  1409. #elif   defined(F101_25)
  1410.     change_system_clock(15);
  1411. #elif   defined(F94_5)
  1412.     change_system_clock(14);
  1413. #elif   defined(F87_75)
  1414.     change_system_clock(13);
  1415. #elif   defined(F81)
  1416.     change_system_clock(12);
  1417. #elif   defined(F74_25)
  1418.     change_system_clock(11);
  1419. #elif   defined(F67_5)
  1420.     change_system_clock(10);
  1421. #elif   defined(F60_75)
  1422.     change_system_clock(9);
  1423. #elif   defined(F54)
  1424.     change_system_clock(8);
  1425. #elif   defined(F47_25)
  1426.     change_system_clock(7);
  1427. #elif   defined(F40_5)
  1428.     change_system_clock(6);
  1429. #elif   defined(F33_75)
  1430.     change_system_clock(5);
  1431. #elif   defined(F27)
  1432.     change_system_clock(4);
  1433. #elif   defined(F13_5)
  1434.     change_system_clock(2);
  1435. #elif   defined(F6_75)
  1436.     change_system_clock(1);
  1437. #endif
  1438.     //reset_set_uart0_baudrate();
  1439.     return 0;
  1440. }
  1442. /**************************************************************************
  1443.  *  Function Name: reset_change_sysclk_27M                                *
  1444.  *  Purposes:                                                             *
  1445.  *      change system clock to 27M                                        *
  1446.  *  Descriptions:                                                         *
  1447.  *      change system clock                                               *
  1448.  *  Arguments:  None                                                      *
  1449.  *  Returns: 0                                                            *
  1450.  *  See also: None                                                        *
  1451.  **************************************************************************/
  1452. int
  1453. reset_change_sysclk_27M(void)
  1454. {
  1455.     change_system_clock(4);    UART0_set_baudrate(BAUDCC(115200, 27000000));
  1456. //  change_system_clock(10);    UART0_set_baudrate(BAUDCC(115200, 67500000));
  1457.     return 0;
  1458. }
  1461. #ifdef  SUPPORT_USB
  1462. /**************************************************************************
  1463.  *  Function Name: set_usbpll_reg                                         *
  1464.  *  Purposes:                                                             *
  1465.  *      setup regs0->sft_cfg9                                             *
  1466.  *  Descriptions:                                                         *
  1467.  *      setup USB clock                                                     *
  1468.  *  Arguments:  None                                                      *
  1469.  *  Returns: None                                                         *
  1470.  *  See also: None                                                        *
  1471.  **************************************************************************/
  1472. static inline void set_usbpll_reg(unsigned s, unsigned ns)
  1473. {
  1474. #ifdef SPHE1000
  1475.     unsigned cfg7;
  1476.     cfg7 = regs0->sft_cfg7;
  1477.     regs0->sft_cfg7 = (cfg7 & ~0xfff) | ((ns<<6)|(s));
  1478. #else
  1479.     unsigned cfg9;
  1480.     cfg9 = regs0->sft_cfg9;
  1481.     regs0->sft_cfg9 = (cfg9 & ~0xfff) | ((ns<<6)|(s));
  1482. #endif
  1483. }
  1485. #endif
  1487. //
  1488. // SYSTEM CLOCK
  1489. //
  1491. #ifdef SPHE1000
  1492. #define LX_F256
  1493. static inline void set_lx4189_overclock()
  1494. {
  1495. // change lx4189 sysclk->270Mhz
  1496. volatile UINT32 *ptr=(volatile UINT32*)0xbc010ce0;
  1497. BYTE NR=0, NF=0;
  1498. BYTE OD=0;
  1500. #if defined(LX_F251)
  1501. NR=5; NF=93;
  1502. #elif defined(LX_F253)
  1503. NR=5; NF=94;
  1504. #elif defined(LX_F256)
  1505. NR=2; NF=38;
  1506. #elif defined(LX_F263)
  1507. NR=2; NF=39;
  1508. #elif defined(LX_F270)
  1509. NR=2; NF=40;
  1510. #elif defined(LX_F276)
  1511. NR=2; NF=41;
  1512. #elif defined(LX_F283)
  1513. NR=2; NF=42;
  1514. #elif defined(LX_F290)
  1515. NR=2; NF=43;
  1516. #elif defined(LX_F297)
  1517. NR=2; NF=44;
  1518. #elif defined(LX_F303)
  1519. NR=2; NF=45;
  1520. #elif defined(LX_F310)
  1521. NR=2; NF=46;
  1522. #else // F270
  1523. NR=2; NF=40;
  1524. #endif
  1526. regs0->pllc_cfg = (OD<<14)|((NR-2)<<9)|(NF-2);
  1527. *ptr = 1;
  1528. delay_1us(500);
  1529. }
  1530. #endif // SPHE1000
  1532. /**************************************************************************
  1533.  *  Function Name: set_syspll_reg                                         *
  1534.  *  Purposes:                                                             *
  1535.  *     setup regs0->sysclk_div_sel and regs0->sysclk_sel                  *
  1536.  *  Descriptions:                                                         *
  1537.  *      setup system clock                                                *
  1538.  *  Arguments:  None                                                      *
  1539.  *  Returns: None                                                         *
  1540.  *  See also: None                                                        *
  1541.  **************************************************************************/
  1542. static inline void set_syspll_reg(unsigned a, unsigned b)
  1543. {
  1544.     int i;
  1545. #ifdef SPHE1000
  1546.     regs0->sysclk_div_sel= 0x0404;       // slow it down
  1547.     regs0->sysclk_sel=((a)|(10<<4));
  1548.     for (i=0;i<1000 && (regs0->sysclk_sel&((1<<8)|(1<<11)|(1<<12))); i++) ;
  1549.     regs0->sysclk_div_sel= ((b)|(0<<8));
  1550.   #if 0
  1551. set_lx4189_overclock();
  1552.   #endif
  1553. #else
  1554.     regs0->sysclk_div_sel= 4;       // slow it down
  1555.     regs0->sysclk_sel=a;
  1556.     for (i=0;i<1000 && (regs0->sysclk_sel&((1<<11)|(1<<12))); i++) ;
  1557. #ifdef  CLK54_USE_USBPLL
  1558.     b |= (2<<6);        // CLK54 select USB OSCx2
  1559.     //b |= (3<<6);        // CLK54 select USB OSC
  1560. #endif
  1561.     regs0->sysclk_div_sel= b;
  1562. #endif
  1563. }
  1565. /**************************************************************************
  1566.  *  Function Name: reset_delayX                                           *
  1567.  *  Purposes: delay time                                                  *
  1568.  *  Descriptions: delay time                                              *
  1569.  *  Arguments:  None                                                      *
  1570.  *  Returns: None                                                         *
  1571.  *  See also: None                                                        *
  1572.  **************************************************************************/
  1573. static void reset_delayX(int n)
  1574. {
  1575.     while (n-->0) {
  1576.         asm volatile ("nop");
  1577.     }
  1578. }
  1582. #define     CLKUV(u,v)  (((u)<<4)|(v))
  1583. #define     CLKUV_U(uv)  ((uv)>>4)
  1584. #define     CLKUV_V(uv)  ((uv)&0x0f)
  1586. static  const   UINT8   sysclk_table[26] = //wrwu, 2005-01-21, for over-clock
  1587. {
  1588.     CLKUV(1,0),     // 00: -----
  1589.     CLKUV(1,4),     // 01: 0.25x      6.75
  1590.     CLKUV(1,3),     // 02: 0.50x     13.5
  1591.     CLKUV(9,3),     // 03: 0.75x     20.25
  1592.     CLKUV(1,2),     // 04: 1.00x     27
  1593.     CLKUV(5,2),     // 05: 1.25x     33.75
  1594.     CLKUV(9,2),     // 06: 1.50x     40.5
  1595.     CLKUV(13,2),    // 07: 1.75x     47.25
  1596.     CLKUV(1,1),     // 08: 2.00x     54
  1597.     CLKUV(3,2),     // 09: 2.25x     60.75
  1598.     CLKUV(5,1),     // 10: 2.50x     67.5
  1599.     CLKUV(7,1),     // 11: 2.75x     74.25
  1600.     CLKUV(9,1),     // 12: 3.00x     81
  1601.     CLKUV(11,1),    // 13: 3.25x     87.75
  1602.     CLKUV(13,1),    // 14: 3.50x     94.5
  1603.     CLKUV(0,1),     // 15: 3.75x    101.25
  1604.     CLKUV(1,0),     // 16: 4.00x    108         xx
  1605.     CLKUV(2,1),     // 17: 4.25x    114.75
  1606.     CLKUV(3,1),     // 18: 4.50x    121.50
  1607.     CLKUV(4,0),     // 19: 4.75x    128.25      xx
  1608.     CLKUV(5,0),     // 20: 5.00x    135
  1609.     CLKUV(6,0),     // 21: 5.25x    141.75
  1610.     CLKUV(7,0),     // 22: 5.50x    148.5
  1611.     CLKUV(8,0),     // 23: 5.75x    155.25
  1612.     CLKUV(9,0),     // 24: 6.00x    162
  1613.     CLKUV(10,0),    // 25: 6.25x    168.75
  1614. #if 0
  1615.     CLKUV(11,0),    // 26: 6.50x    175.5
  1616.     CLKUV(12,0),    // 27: 6.75x    181.25
  1617.     CLKUV(13,0),    // 28: 7.00x    189
  1618. #endif
  1619. };
  1622. static  const   UINT8   baudrate_table[26] = { //wrwu, 2005-01-21, for over-clock
  1623.     BAUDCC(115200,6750000*0),
  1624.     BAUDCC(115200,6750000*1),
  1625.     BAUDCC(115200,6750000*2),
  1626.     BAUDCC(115200,6750000*3),
  1627.     BAUDCC(115200,6750000*4),
  1628.     BAUDCC(115200,6750000*5),
  1629.     BAUDCC(115200,6750000*6),
  1630.     BAUDCC(115200,6750000*7),
  1631.     BAUDCC(115200,6750000*8),
  1632.     BAUDCC(115200,6750000*9),
  1633.     BAUDCC(115200,6750000*10),
  1634.     BAUDCC(115200,6750000*11),
  1635.     BAUDCC(115200,6750000*12),
  1636.     BAUDCC(115200,6750000*13),
  1637.     BAUDCC(115200,6750000*14),
  1638.     BAUDCC(115200,6750000*15),
  1639.     BAUDCC(115200,6750000*16),
  1640.     BAUDCC(115200,6750000*17),
  1641.     BAUDCC(115200,6750000*18),
  1642.     BAUDCC(115200,6750000*19),
  1643.     BAUDCC(115200,6750000*20),
  1644.     BAUDCC(115200,6750000*21),
  1645.     BAUDCC(115200,6750000*22),
  1646.     BAUDCC(115200,6750000*23),
  1647.     BAUDCC(115200,6750000*24),
  1648.     BAUDCC(115200,6750000*25)
  1649. };
  1652. #ifdef SHOW_SYSTEM_CLOCK//nono 4-4-6 0:29
  1653. int get_sysclk;
  1654. #endif//SHOW_SYSTEM_CLOCK
  1655. /**************************************************************************
  1656.  *  Function Name: change_system_clock                                    *
  1657.  *  Purposes:                                                             *
  1658.  *   1. disable interrupt                                                 *
  1659.  *   2. get idx                                                           *
  1660.  *   3. set syspll                                                        *
  1661.  *   4. set sdram-timing                                                  *
  1662.  *   5. restore interrupt setting                                         *
  1663.  *  Descriptions:                                                         *
  1664.  *      change system clock                                               *
  1665.  *  Arguments:  None                                                      *
  1666.  *  Returns: 0                                                            *
  1667.  *  See also: None                                                        *
  1668.  **************************************************************************/
  1669. int
  1670. change_system_clock(int uvidx)
  1671. {
  1672.     unsigned uv, u, v, IEc;
  1674. #ifdef SHOW_SYSTEM_CLOCK//nono 4-4-6 0:29
  1675.     //get get_sysclk;print on cus_menu
  1676.     get_sysclk = uvidx;
  1677. #endif//#ifdef SHOW_SYSTEM_CLOCK
  1679.     // disable interrupt
  1680.     IEc = cpu_intr_disable();
  1682.     //
  1683.     reset_delayX(100);
  1685.     // get idx
  1686.     uv = sysclk_table[uvidx];
  1687.     u = CLKUV_U(uv);
  1688.     v = CLKUV_V(uv);
  1690. #if defined(BOOT_HALF) || defined(IC_8202E)
  1691.     if (v!=0) v--;
  1692. #endif
  1694.     // set syspll
  1695.     set_syspll_reg(u,v);
  1697. #ifdef  SUPPORT_USB
  1698.     //set_usbpll_reg(0x12,0x1b);        // 96mhz/48mhz
  1699.     //set_usbpll_reg(0x1b,0x1b);          // 54mhz/27mhz
  1700.     //regs0->sft_cfg7 |= (0xf<<8);        // clk27 select clk54/2
  1701.     //regs0->sft_cfg7 |= (3<<12);       // output clk54 to pin 65
  1702. #endif
  1704.     // set sdram-timing
  1705.     if (uvidx<10)
  1706.         set_sdram_timing_low();
  1707.     else
  1708.         set_sdram_timing();
  1710.     // restore interrupt setting
  1711.     cpu_intr_config(IEc);
  1713. #if !defined(SPHE8202) && !defined(SPHE1000)
  1714.     // initialize stc-divisor
  1715.     regs0->stc_divisor    = uvidx*75-1;
  1716.     UART0_set_baudrate(baudrate_table[uvidx]);
  1717. #endif
  1718.     return 0;
  1719. }
  1721. /**************************************************************************
  1722.  *  Function Name: slowdown_test                                          *
  1723.  *  Purposes:                                                             *
  1724.  *  Descriptions:                                                         *
  1725.  *  Arguments:  None                                                      *
  1726.  *  Returns: None                                                         *
  1727.  *  See also: None                                                        *
  1728.  **************************************************************************/
  1729. #if 0
  1730. void
  1731. slowdown_test(void)
  1732. {
  1733.     reset_change_sysclk_27M();
  1734.     UART0_set_baudrate(BAUDCC(115200, 27000000));
  1735.     delay_1ms(200);
  1736.     reset_change_sysclk();
  1737.     UART0_set_baudrate(BAUDCC(115200, 121500000));
  1738. }
  1739. #endif