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pci_wbw_fifo_control(1).v
资源名称：pci_core_verilog.rar　[点击查看]
上传用户：quan1896
上传日期：2014-05-14
资源大小：211k
文件大小：32k
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pci_wbw_fifo_control(1).v：源码内容
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  516. <a href="./pci_wbw_fifo_control.v#rev1.5"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_wbw_fifo_control.v#rev1.5">pci_wbw_fifo_control.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td>  <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td>
  517.  </tr>
  518. </table>
  519. <hr />
  520. <div class="log-markup">
  521. File:&nbsp;
  522.  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_wbw_fifo_control.v">pci_wbw_fifo_control.v</a><br />
  523. <a name="rev1.5"></a><a name="HEAD"></a>
  524.  Revision <b>1.5</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_wbw_fifo_control.v?rev=1.5;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_wbw_fifo_control.v?rev=1.5;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_wbw_fifo_control.v?annotate=1.5">annotated</a> - <a href="pci_wbw_fifo_control.v?r1=1.5#rev1.5">select&nbsp;for&nbsp;diffs</a><br />
  525. <i>Tue Jul  4 13:16:19 2006 UTC</i> (10 months, 2 weeks ago) by <i>mihad</i><br />
  526. Branches: <a href="./pci_wbw_fifo_control.v?only_with_tag=MAIN">MAIN</a><br />
  527. CVS tags: <a href="./pci_wbw_fifo_control.v?only_with_tag=HEAD">HEAD</a><br />
  528. <pre class="log">
  529. Write burst performance patch applied.
  530. Not tested. Everything should be backwards
  531. compatible, since functional code is ifdefed.
  532. </pre>
  533. </div>
  534. <hr /><pre>
  535. //////////////////////////////////////////////////////////////////////
  536. ////                                                              ////
  537. ////  File name &quot;wbw_fifo_control.v&quot;                              ////
  538. ////                                                              ////
  539. ////  This file is part of the &quot;PCI bridge&quot; project               ////
  540. ////  http://www.opencores.org/cores/pci/                         ////
  541. ////                                                              ////
  542. ////  Author(s):                                                  ////
  543. ////      - Miha Dolenc (mihad@opencores.org)                     ////
  544. ////                                                              ////
  545. ////  All additional information is avaliable in the README       ////
  546. ////  file.                                                       ////
  547. ////                                                              ////
  548. ////                                                              ////
  549. //////////////////////////////////////////////////////////////////////
  550. ////                                                              ////
  551. //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
  552. ////                                                              ////
  553. //// This source file may be used and distributed without         ////
  554. //// restriction provided that this copyright statement is not    ////
  555. //// removed from the file and that any derivative work contains  ////
  556. //// the original copyright notice and the associated disclaimer. ////
  557. ////                                                              ////
  558. //// This source file is free software; you can redistribute it   ////
  559. //// and/or modify it under the terms of the GNU Lesser General   ////
  560. //// Public License as published by the Free Software Foundation; ////
  561. //// either version 2.1 of the License, or (at your option) any   ////
  562. //// later version.                                               ////
  563. ////                                                              ////
  564. //// This source is distributed in the hope that it will be       ////
  565. //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  566. //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  567. //// PURPOSE.  See the GNU Lesser General Public License for more ////
  568. //// details.                                                     ////
  569. ////                                                              ////
  570. //// You should have received a copy of the GNU Lesser General    ////
  571. //// Public License along with this source; if not, download it   ////
  572. //// from http://www.opencores.org/lgpl.shtml                     ////
  573. ////                                                              ////
  574. //////////////////////////////////////////////////////////////////////
  575. //
  576. // CVS Revision History
  577. //
  578. // $Log: pci_wbw_fifo_control.v,v $
  579. // Revision 1.5  2006/07/04 13:16:19  mihad
  580. // Write burst performance patch applied.
  581. // Not tested. Everything should be backwards
  582. // compatible, since functional code is ifdefed.
  583. //
  584. // Revision 1.4  2003/08/14 13:06:03  simons
  585. // synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
  586. //
  587. // Revision 1.3  2003/07/29 08:20:11  mihad
  588. // Found and simulated the problem in the synchronization logic.
  589. // Repaired the synchronization logic in the FIFOs.
  590. //
  591. // Revision 1.2  2003/03/26 13:16:18  mihad
  592. // Added the reset value parameter to the synchronizer flop module.
  593. // Added resets to all synchronizer flop instances.
  594. // Repaired initial sync value in fifos.
  595. //
  596. // Revision 1.1  2003/01/27 16:49:31  mihad
  597. // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  598. //
  599. // Revision 1.6  2002/11/27 20:36:13  mihad
  600. // Changed the code a bit to make it more readable.
  601. // Functionality not changed in any way.
  602. // More robust synchronization in fifos is still pending.
  603. //
  604. // Revision 1.5  2002/09/30 16:03:04  mihad
  605. // Added meta flop module for easier meta stable FF identification during synthesis
  606. //
  607. // Revision 1.4  2002/09/25 15:53:52  mihad
  608. // Removed all logic from asynchronous reset network
  609. //
  610. // Revision 1.3  2002/02/01 15:25:14  mihad
  611. // Repaired a few bugs, updated specification, added test bench files and design document
  612. //
  613. // Revision 1.2  2001/10/05 08:14:30  mihad
  614. // Updated all files with inclusion of timescale file for simulation purposes.
  615. //
  616. // Revision 1.1.1.1  2001/10/02 15:33:47  mihad
  617. // New project directory structure
  618. //
  619. //
  621. /* FIFO_CONTROL module provides read/write address and status generation for
  622.    FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
  623. `include &quot;pci_constants.v&quot;
  624. // synopsys translate_off
  625. `include &quot;timescale.v&quot;
  626. // synopsys translate_on
  628. module pci_wbw_fifo_control
  629. (
  630.     rclock_in,
  631.     wclock_in,
  632.     renable_in,
  633.     wenable_in,
  634.     reset_in,
  635.     almost_full_out,
  636.     full_out,
  637.     empty_out,
  638.     waddr_out,
  639.     raddr_out,
  640.     rallow_out,
  641.     wallow_out,
  642. half_full_out ////Robert, burst issue
  643. );
  645. parameter ADDR_LENGTH = 7;
  647. // independent clock inputs - rclock_in = read clock, wclock_in = write clock
  648. input  rclock_in, wclock_in;
  650. // enable inputs - read address changes on rising edge of rclock_in when reads are allowed
  651. //                 write address changes on rising edge of wclock_in when writes are allowed
  652. input  renable_in, wenable_in ;
  654. // reset input
  655. input  reset_in;
  657. // flush input
  658. // input flush_in ; // not used
  660. // almost full and empy status outputs
  661. output almost_full_out ;
  663. // full and empty status outputs
  664. output full_out, empty_out;
  666. // read and write addresses outputs
  667. output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
  669. // read and write allow outputs
  670. output rallow_out, wallow_out ;
  672. output half_full_out;
  674. // read address register
  675. reg [(ADDR_LENGTH - 1):0] raddr ;
  677. // write address register
  678. reg [(ADDR_LENGTH - 1):0] waddr;
  679. assign waddr_out = waddr ;
  681. // grey code registers
  682. reg [(ADDR_LENGTH - 1):0] wgrey_addr ; // current
  683. // grey code register for next write address
  684. reg [(ADDR_LENGTH - 1):0] wgrey_next ; // next
  686. // next write gray address calculation - bitwise xor between address and shifted address
  687. wire [(ADDR_LENGTH - 2):0] calc_wgrey_next  = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
  689. // grey code pipeline for read address
  690. reg [(ADDR_LENGTH - 1):0] rgrey_minus1 ; // one before current
  691. reg [(ADDR_LENGTH - 1):0] rgrey_addr ; // current
  692. reg [(ADDR_LENGTH - 1):0] rgrey_next ; // next
  694. // next read gray address calculation - bitwise xor between address and shifted address
  695. wire [(ADDR_LENGTH - 2):0] calc_rgrey_next  = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
  697. // write allow wire - writes are allowed when fifo is not full
  698. assign wallow_out = wenable_in &amp; ~full_out ;
  700. // clear generation for FFs and registers
  701. wire clear = reset_in ;
  703. //rallow generation
  704. assign rallow_out = renable_in &amp; ~empty_out ; // reads allowed if read enable is high and FIFO is not empty
  706. // at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
  707. // when FIFO is empty, this register provides actual read address, so first location can be read
  708. reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
  711. wire [ADDR_LENGTH :0] fifo_fullness; //Robert, burst issue
  713. //Robert, burst issue
  714. assign fifo_fullness = (waddr &gt; raddr) ? ({1'b0, waddr} - {1'b0, raddr}) : ({1'b1, waddr} - {1'b0, raddr});
  715. assign half_full_out   = fifo_fullness[(ADDR_LENGTH - 1)] ;
  716. //Robert, burst issue
  719. // address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
  720. // done for zero wait state burst
  721. assign raddr_out = rallow_out ? raddr_plus_one : raddr ;
  723. always@(posedge rclock_in or posedge clear)
  724. begin
  725.     if (clear)
  726.     begin
  727.         raddr_plus_one &lt;= #`FF_DELAY 4 ;
  728.         raddr          &lt;= #`FF_DELAY 3 ;
  729.     end
  730.     else if (rallow_out)
  731.     begin
  732.         raddr_plus_one &lt;= #`FF_DELAY raddr_plus_one + 1'b1 ;
  733.         raddr          &lt;= #`FF_DELAY raddr_plus_one ;
  734.     end
  735. end
  737. /*-----------------------------------------------------------------------------------------------
  738. Read address control consists of Read address counter and Grey Address pipeline
  739. There are 3 Grey addresses:
  740.     - rgrey_minus1 is Grey Code of address one before current address
  741.     - rgrey_addr is Grey Code of current read address
  742.     - rgrey_next is Grey Code of next read address
  743. --------------------------------------------------------------------------------------------------*/
  744. // grey coded address pipeline for status generation in read clock domain
  745. always@(posedge rclock_in or posedge clear)
  746. begin
  747. if (clear)
  748.     begin
  749.         // initial value is 0
  750.         rgrey_minus1 &lt;= #1 0 ;
  751.         rgrey_addr   &lt;= #1 1 ;
  752.         rgrey_next   &lt;= #`FF_DELAY 3 ;
  753.     end
  754.     else
  755.     if (rallow_out)
  756.     begin
  757.         rgrey_minus1 &lt;= #1 rgrey_addr ;
  758.         rgrey_addr   &lt;= #1 rgrey_next ;
  759.         rgrey_next   &lt;= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
  760.     end
  761. end
  763. /*--------------------------------------------------------------------------------------------
  764. Write address control consists of write address counter and Grey Code Register
  765. ----------------------------------------------------------------------------------------------*/
  766. // grey coded address pipeline for status generation in write clock domain
  767. always@(posedge wclock_in or posedge clear)
  768. begin
  769.     if (clear)
  770.     begin
  771.         wgrey_addr &lt;= #`FF_DELAY 1 ;
  772.         wgrey_next &lt;= #1 3         ;
  773.     end
  774.     else
  775.     if (wallow_out)
  776.     begin
  777.         wgrey_addr &lt;= #`FF_DELAY wgrey_next ;
  778.         wgrey_next &lt;= #1 {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
  779.     end
  780. end
  782. // write address counter - nothing special - initial value is important though
  783. always@(posedge wclock_in or posedge clear)
  784. begin
  785.     if (clear)
  786.         // initial value 4
  787.     waddr &lt;= #`FF_DELAY 3 ;
  788.     else
  789.     if (wallow_out)
  790.         waddr &lt;= #`FF_DELAY waddr + 1'b1 ;
  791. end
  793. /*------------------------------------------------------------------------------------------------------------------------------
  794. Gray coded address of read address decremented by 1 is synchronized to write clock domain and compared to:
  796. - Gray coded write address. If they are equal, fifo is full.
  798. - Gray coded next write address. If they are equal, fifo is almost full.
  799. --------------------------------------------------------------------------------------------------------------------------------*/
  800. wire [(ADDR_LENGTH - 1):0] wclk_sync_rgrey_minus1 ;
  801. reg  [(ADDR_LENGTH - 1):0] wclk_rgrey_minus1 ;
  803. pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_rgrey_minus1
  804. (
  805.     .data_in        (rgrey_minus1),
  806.     .clk_out        (wclock_in),
  807.     .sync_data_out  (wclk_sync_rgrey_minus1),
  808.     .async_reset    (clear)
  809. ) ;
  811. always@(posedge wclock_in or posedge clear)
  812. begin
  813.     if (clear)
  814.     begin
  815.         wclk_rgrey_minus1 &lt;= #`FF_DELAY 0 ;
  816.     end
  817.     else
  818.     begin
  819.         wclk_rgrey_minus1 &lt;= #`FF_DELAY wclk_sync_rgrey_minus1 ;
  820.     end
  821. end
  823. assign full_out        = (wgrey_addr == wclk_rgrey_minus1) ;
  824. assign almost_full_out = (wgrey_next == wclk_rgrey_minus1) ;
  826. /*------------------------------------------------------------------------------------------------------------------------------
  827. Empty control:
  828. Gray coded address of next write address is synchronized to read clock domain and compared to Gray coded next read address.
  829. If they are equal, fifo is empty.
  830. --------------------------------------------------------------------------------------------------------------------------------*/
  831. wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_next ;
  832. reg  [(ADDR_LENGTH - 1):0] rclk_wgrey_next ;
  833. pci_synchronizer_flop #(ADDR_LENGTH, 3) i_synchronizer_reg_wgrey_next
  834. (
  835.     .data_in        (wgrey_next),
  836.     .clk_out        (rclock_in),
  837.     .sync_data_out  (rclk_sync_wgrey_next),
  838.     .async_reset    (clear)
  839. ) ;
  841. always@(posedge rclock_in or posedge clear)
  842. begin
  843.     if (clear)
  844.         rclk_wgrey_next &lt;= #`FF_DELAY 3 ;
  845.     else
  846.         rclk_wgrey_next &lt;= #`FF_DELAY rclk_sync_wgrey_next ;
  847. end
  849. assign empty_out = (rgrey_next == rclk_wgrey_next) ;
  851. endmodule
  852. </pre>
  853. <hr />
  854. <address><span style="font-size: smaller">FreeBSD-CVSweb &lt;<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>&gt;</span></address>
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