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pci_wb_tpram.v
资源名称：pci_core_verilog.rar　[点击查看]
上传用户：quan1896
上传日期：2014-05-14
资源大小：211k
文件大小：33k
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并行计算

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pci_wb_tpram.v：源码内容
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  516. <a href="./pci_wb_tpram.v#rev1.4"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_wb_tpram.v#rev1.4">pci_wb_tpram.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td>  <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td>
  517.  </tr>
  518. </table>
  519. <hr />
  520. <div class="log-markup">
  521. File:&nbsp;
  522.  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_wb_tpram.v">pci_wb_tpram.v</a><br />
  523. <a name="rev1.4"></a><a name="HEAD"></a>
  524.  Revision <b>1.4</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_wb_tpram.v?rev=1.4;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_wb_tpram.v?rev=1.4;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_wb_tpram.v?annotate=1.4">annotated</a> - <a href="pci_wb_tpram.v?r1=1.4#rev1.4">select&nbsp;for&nbsp;diffs</a><br />
  525. <i>Thu Aug 19 15:27:34 2004 UTC</i> (2 years, 8 months ago) by <i>mihad</i><br />
  526. Branches: <a href="./pci_wb_tpram.v?only_with_tag=MAIN">MAIN</a><br />
  527. CVS tags: <a href="./pci_wb_tpram.v?only_with_tag=HEAD">HEAD</a><br />
  528. <pre class="log">
  529. Changed minimum pci image size to 256 bytes because
  530. of some PC system problems with size of IO images.
  531. </pre>
  532. </div>
  533. <hr /><pre>
  534. //////////////////////////////////////////////////////////////////////
  535. ////                                                              ////
  536. ////  Generic Two-Port Synchronous RAM                            ////
  537. ////                                                              ////
  538. ////  This file is part of pci bridge project                     ////
  539. ////  http://www.opencores.org/cvsweb.shtml/pci/                  ////
  540. ////                                                              ////
  541. ////  Description                                                 ////
  542. ////  This block is a wrapper with common two-port                ////
  543. ////  synchronous memory interface for different                  ////
  544. ////  types of ASIC and FPGA RAMs. Beside universal memory        ////
  545. ////  interface it also provides behavioral model of generic      ////
  546. ////  two-port synchronous RAM.                                   ////
  547. ////  It should be used in all OPENCORES designs that want to be  ////
  548. ////  portable accross different target technologies and          ////
  549. ////  independent of target memory.                               ////
  550. ////                                                              ////
  551. ////  Supported ASIC RAMs are:                                    ////
  552. ////  - Artisan Double-Port Sync RAM                              ////
  553. ////  - Avant! Two-Port Sync RAM (*)                              ////
  554. ////  - Virage 2-port Sync RAM                                    ////
  555. ////                                                              ////
  556. ////  Supported FPGA RAMs are:                                    ////
  557. ////  - Xilinx Virtex RAMB4_S16_S16                               ////
  558. ////                                                              ////
  559. ////  To Do:                                                      ////
  560. ////   - fix Avant!                                               ////
  561. ////   - xilinx rams need external tri-state logic                ////
  562. ////   - add additional RAMs (Altera, VS etc)                     ////
  563. ////                                                              ////
  564. ////  Author(s):                                                  ////
  565. ////      - Damjan Lampret, lampret@opencores.org                 ////
  566. ////      - Miha Dolenc, mihad@opencores.org                      ////
  567. ////                                                              ////
  568. //////////////////////////////////////////////////////////////////////
  569. ////                                                              ////
  570. //// Copyright (C) 2000 Authors and OPENCORES.ORG                 ////
  571. ////                                                              ////
  572. //// This source file may be used and distributed without         ////
  573. //// restriction provided that this copyright statement is not    ////
  574. //// removed from the file and that any derivative work contains  ////
  575. //// the original copyright notice and the associated disclaimer. ////
  576. ////                                                              ////
  577. //// This source file is free software; you can redistribute it   ////
  578. //// and/or modify it under the terms of the GNU Lesser General   ////
  579. //// Public License as published by the Free Software Foundation; ////
  580. //// either version 2.1 of the License, or (at your option) any   ////
  581. //// later version.                                               ////
  582. ////                                                              ////
  583. //// This source is distributed in the hope that it will be       ////
  584. //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  585. //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  586. //// PURPOSE.  See the GNU Lesser General Public License for more ////
  587. //// details.                                                     ////
  588. ////                                                              ////
  589. //// You should have received a copy of the GNU Lesser General    ////
  590. //// Public License along with this source; if not, download it   ////
  591. //// from http://www.opencores.org/lgpl.shtml                     ////
  592. ////                                                              ////
  593. //////////////////////////////////////////////////////////////////////
  594. //
  595. // CVS Revision History
  596. //
  597. // $Log: pci_wb_tpram.v,v $
  598. // Revision 1.4  2004/08/19 15:27:34  mihad
  599. // Changed minimum pci image size to 256 bytes because
  600. // of some PC system problems with size of IO images.
  601. //
  602. // Revision 1.3  2003/10/17 09:11:52  markom
  603. // mbist signals updated according to newest convention
  604. //
  605. // Revision 1.2  2003/08/14 13:06:03  simons
  606. // synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
  607. //
  608. // Revision 1.1  2003/01/27 16:49:31  mihad
  609. // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  610. //
  611. // Revision 1.7  2002/10/18 03:36:37  tadejm
  612. // Changed wrong signal name mbist_sen into mbist_ctrl_i.
  613. //
  614. // Revision 1.6  2002/10/17 22:49:22  tadejm
  615. // Changed BIST signals for RAMs.
  616. //
  617. // Revision 1.5  2002/10/11 10:09:01  mihad
  618. // Added additional testcase and changed rst name in BIST to trst
  619. //
  620. // Revision 1.4  2002/10/08 17:17:06  mihad
  621. // Added BIST signals for RAMs.
  622. //
  623. // Revision 1.3  2002/09/30 17:22:27  mihad
  624. // Added support for Virtual Silicon two port RAM. Didn't run regression on it yet!
  625. //
  626. // Revision 1.2  2002/08/19 16:51:36  mihad
  627. // Extracted distributed RAM module from wb/pci_tpram.v to its own file, got rid of undef directives
  628. //
  629. // Revision 1.1  2002/02/01 14:43:31  mihad
  630. // *** empty log message ***
  631. //
  632. //
  634. // synopsys translate_off
  635. `include &quot;timescale.v&quot;
  636. // synopsys translate_on
  637. `include &quot;pci_constants.v&quot;
  639. module pci_wb_tpram
  640. (
  641. // Generic synchronous two-port RAM interface
  642. clk_a,
  643.     rst_a,
  644.     ce_a,
  645.     we_a,
  646.     oe_a,
  647.     addr_a,
  648.     di_a,
  649.     do_a,
  650. clk_b,
  651.     rst_b,
  652.     ce_b,
  653.     we_b,
  654.     oe_b,
  655.     addr_b,
  656.     di_b,
  657.     do_b
  658. `ifdef PCI_BIST
  659.     ,
  660.     // debug chain signals
  661.     mbist_si_i,       // bist scan serial in
  662.     mbist_so_o,       // bist scan serial out
  663.     mbist_ctrl_i        // bist chain shift control
  664. `endif
  665. );
  667. //
  668. // Default address and data buses width
  669. //
  670. parameter aw = 8;
  671. parameter dw = 40;
  673. //
  674. // Generic synchronous two-port RAM interface
  675. //
  676. input clk_a; // Clock
  677. input rst_a; // Reset
  678. input ce_a; // Chip enable input
  679. input we_a; // Write enable input
  680. input oe_a; // Output enable input
  681. input  [aw-1:0] addr_a; // address bus inputs
  682. input [dw-1:0] di_a; // input data bus
  683. output [dw-1:0] do_a; // output data bus
  684. input clk_b; // Clock
  685. input rst_b; // Reset
  686. input ce_b; // Chip enable input
  687. input we_b; // Write enable input
  688. input oe_b; // Output enable input
  689. input  [aw-1:0] addr_b; // address bus inputs
  690. input [dw-1:0] di_b; // input data bus
  691. output [dw-1:0] do_b; // output data bus
  693. `ifdef PCI_BIST
  694. // debug chain signals
  695. input   mbist_si_i;       // bist scan serial in
  696. output  mbist_so_o;       // bist scan serial out
  697. input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
  698. `endif
  700. //
  701. // Internal wires and registers
  702. //
  704. `ifdef WB_VS_STP
  705.     `define PCI_WB_RAM_SELECTED
  706.     `ifdef PCI_BIST
  707.         vs_hdtp_64x40_bist i_vs_hdtp_64x40_bist
  708.     `else
  709.         vs_hdtp_64x40 i_vs_hdtp_64x40
  710.     `endif
  711.         (
  712.             .RCK        (clk_b),
  713.             .WCK        (clk_a),
  714.             .RADR       (addr_b),
  715.             .WADR       (addr_a),
  716.             .DI         (di_a),
  717.             .DOUT       (do_b),
  718.             .REN        (1'b0),
  719.             .WEN        (!we_a)
  720.         `ifdef PCI_BIST
  721.             ,
  722.             // debug chain signals
  723.             .mbist_si_i   (mbist_si_i),
  724.             .mbist_so_o   (mbist_so_o),
  725.             .mbist_ctrl_i   (mbist_ctrl_i)
  726.         `endif
  727.         );
  728.     
  729.     assign do_a = 0 ;
  730. `endif
  732. `ifdef WB_ARTISAN_SDP
  733.     `define PCI_WB_RAM_SELECTED
  734.     //
  735.     // Instantiation of ASIC memory:
  736.     //
  737.     // Artisan Synchronous Double-Port RAM (ra2sh)
  738.     //
  739.     `ifdef PCI_BIST
  740.         art_hsdp_64x40_bist /*#(dw, 1&lt;&lt;aw, aw) */ artisan_sdp
  741.         (
  742.          .QA(do_a),
  743.          .CLKA(clk_a),
  744.          .CENA(~ce_a),
  745.          .WENA(~we_a),
  746.          .AA(addr_a),
  747.          .DA(di_a),
  748.          .OENA(~oe_a),
  749.          .QB(do_b),
  750.          .CLKB(clk_b),
  751.          .CENB(~ce_b),
  752.          .WENB(~we_b),
  753.          .AB(addr_b),
  754.          .DB(di_b),
  755.          .OENB(~oe_b),
  756.           .mbist_si_i   (mbist_si_i),
  757.           .mbist_so_o   (mbist_so_o),
  758.           .mbist_ctrl_i   (mbist_ctrl_i)
  759.         );
  760.     `else
  761.         art_hsdp_64x40 /*#(dw, 1&lt;&lt;aw, aw) */ artisan_sdp
  762.         (
  763.          .QA(do_a),
  764.          .CLKA(clk_a),
  765.          .CENA(~ce_a),
  766.          .WENA(~we_a),
  767.          .AA(addr_a),
  768.          .DA(di_a),
  769.          .OENA(~oe_a),
  770.          .QB(do_b),
  771.          .CLKB(clk_b),
  772.          .CENB(~ce_b),
  773.          .WENB(~we_b),
  774.          .AB(addr_b),
  775.          .DB(di_b),
  776.          .OENB(~oe_b)
  777.         );
  778.     `endif
  779. `endif
  781. `ifdef AVANT_ATP
  782.     `define PCI_WB_RAM_SELECTED
  783.     //
  784.     // Instantiation of ASIC memory:
  785.     //
  786.     // Avant! Asynchronous Two-Port RAM
  787.     //
  788.     avant_atp avant_atp(
  789.      .web(~we),
  790.      .reb(),
  791.      .oeb(~oe),
  792.      .rcsb(),
  793.      .wcsb(),
  794.      .ra(addr),
  795.      .wa(addr),
  796.      .di(di),
  797.      .do(do)
  798.     );
  800. `endif
  802. `ifdef VIRAGE_STP
  803.     `define PCI_WB_RAM_SELECTED
  804.     //
  805.     // Instantiation of ASIC memory:
  806.     //
  807.     // Virage Synchronous 2-port R/W RAM
  808.     //
  809.     virage_stp virage_stp(
  810.      .QA(do_a),
  811.      .QB(do_b),
  813.      .ADRA(addr_a),
  814.      .DA(di_a),
  815.      .WEA(we_a),
  816.      .OEA(oe_a),
  817.      .MEA(ce_a),
  818.      .CLKA(clk_a),
  820.      .ADRB(adr_b),
  821.      .DB(di_b),
  822.      .WEB(we_b),
  823.      .OEB(oe_b),
  824.      .MEB(ce_b),
  825.      .CLKB(clk_b)
  826.     );
  828. `endif
  830. `ifdef WB_XILINX_DIST_RAM
  831.     `define PCI_WB_RAM_SELECTED
  833.     reg [(aw-1):0] out_address ;
  834.     always@(posedge clk_b or posedge rst_b)
  835.     begin
  836.         if ( rst_b )
  837.             out_address &lt;= #1 0 ;
  838.         else if (ce_b)
  839.             out_address &lt;= #1 addr_b ;
  840.     end
  842.     pci_ram_16x40d #(aw) wb_distributed_ram
  843.     (
  844.         .data_out       (do_b),
  845.         .we             (we_a),
  846.         .data_in        (di_a),
  847.         .read_address   (out_address),
  848.         .write_address  (addr_a),
  849.         .wclk           (clk_a)
  850.     );
  851.     assign do_a = 0 ;
  852. `endif
  853. `ifdef WB_XILINX_RAMB4
  854.     `define PCI_WB_RAM_SELECTED
  855.     //
  856.     // Instantiation of FPGA memory:
  857.     //
  858.     // Virtex/Spartan2
  859.     //
  861.     //
  862.     // Block 0
  863.     //
  865.     RAMB4_S16_S16 ramb4_s16_s16_0(
  866.      .CLKA(clk_a),
  867.      .RSTA(rst_a),
  868.      .ADDRA(addr_a),
  869.      .DIA(di_a[15:0]),
  870.      .ENA(ce_a),
  871.      .WEA(we_a),
  872.      .DOA(do_a[15:0]),
  874.      .CLKB(clk_b),
  875.      .RSTB(rst_b),
  876.      .ADDRB(addr_b),
  877.      .DIB(di_b[15:0]),
  878.      .ENB(ce_b),
  879.      .WEB(we_b),
  880.      .DOB(do_b[15:0])
  881.     );
  883.     //
  884.     // Block 1
  885.     //
  887.     RAMB4_S16_S16 ramb4_s16_s16_1(
  888.      .CLKA(clk_a),
  889.      .RSTA(rst_a),
  890.      .ADDRA(addr_a),
  891.      .DIA(di_a[31:16]),
  892.      .ENA(ce_a),
  893.      .WEA(we_a),
  894.      .DOA(do_a[31:16]),
  896.      .CLKB(clk_b),
  897.      .RSTB(rst_b),
  898.      .ADDRB(addr_b),
  899.      .DIB(di_b[31:16]),
  900.      .ENB(ce_b),
  901.      .WEB(we_b),
  902.      .DOB(do_b[31:16])
  903.     );
  905.     //
  906.     // Block 2
  907.     //
  908.     // block ram2 wires - non generic width of block rams
  909.     wire [15:0] blk2_di_a = {8'h00, di_a[39:32]} ;
  910.     wire [15:0] blk2_di_b = {8'h00, di_b[39:32]} ;
  912.     wire [15:0] blk2_do_a ;
  913.     wire [15:0] blk2_do_b ;
  915.     assign do_a[39:32] = blk2_do_a[7:0] ;
  916.     assign do_b[39:32] = blk2_do_b[7:0] ;
  918.     RAMB4_S16_S16 ramb4_s16_s16_2(
  919.             .CLKA(clk_a),
  920.             .RSTA(rst_a),
  921.             .ADDRA(addr_a),
  922.             .DIA(blk2_di_a),
  923.             .ENA(ce_a),
  924.             .WEA(we_a),
  925.             .DOA(blk2_do_a),
  927.             .CLKB(clk_b),
  928.             .RSTB(rst_b),
  929.             .ADDRB(addr_b),
  930.             .DIB(blk2_di_b),
  931.             .ENB(ce_b),
  932.             .WEB(we_b),
  933.             .DOB(blk2_do_b)
  934.     );
  936. `endif
  938. `ifdef PCI_WB_RAM_SELECTED
  939. `else
  940.     //
  941.     // Generic two-port synchronous RAM model
  942.     //
  944.     //
  945.     // Generic RAM's registers and wires
  946.     //
  947.     reg [dw-1:0] mem [(1&lt;&lt;aw)-1:0]; // RAM content
  948.     reg [dw-1:0] do_reg_b; // RAM data output register
  950.     //
  951.     // Data output drivers
  952.     //
  953.     assign do_a = {dw{1'b0}}    ;
  954.     assign do_b = do_reg_b      ;
  956.     //
  957.     // RAM read and write
  958.     //
  959.     always @(posedge clk_a)
  960.      if (ce_a &amp;&amp; we_a)
  961.      mem[addr_a] &lt;= #1 di_a;
  963.     //
  964.     // RAM read and write
  965.     //
  966.     always @(posedge clk_b)
  967.      if (ce_b)
  968.      do_reg_b &lt;= #1 mem[addr_b];
  969. `endif
  971. // synopsys translate_off
  972. initial
  973. begin
  974.     if (dw !== 40)
  975.     begin
  976.         $display(&quot;RAM instantiation error! Expected RAM width %d, actual %h!&quot;, 40, dw) ;
  977.         $finish ;
  978.     end
  979.     `ifdef XILINX_RAMB4
  980.         if (aw !== 8)
  981.         begin
  982.             $display(&quot;RAM instantiation error! Expected RAM address width %d, actual %h!&quot;, 40, aw) ;
  983.             $finish ;
  984.         end
  985.     `endif
  986.     // currenlty only artisan ram of depth 256 is supported - they don't provide generic ram models
  987.     `ifdef ARTISAN_SDP
  988.         if (aw !== 8)
  989.         begin
  990.             $display(&quot;RAM instantiation error! Expected RAM address width %d, actual %h!&quot;, 40, aw) ;
  991.             $finish ;
  992.         end
  993.     `endif
  994. end
  995. // synopsys translate_on
  997. endmodule
  999. </pre>
  1000. <hr />
  1001. <address><span style="font-size: smaller">FreeBSD-CVSweb &lt;<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>&gt;</span></address>
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