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pci_wbs_wbb3_2_wbb2.v
资源名称：pci_core_verilog.rar　[点击查看]
上传用户：quan1896
上传日期：2014-05-14
资源大小：211k
文件大小：30k
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pci_wbs_wbb3_2_wbb2.v：源码内容
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  345.               
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  352.             
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  357.               
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  385.            <font class=menu_section>Tools</font>
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  516. <a href="./pci_wbs_wbb3_2_wbb2.v#rev1.5"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_wbs_wbb3_2_wbb2.v#rev1.5">pci_wbs_wbb3_2_wbb2.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td>  <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td>
  517.  </tr>
  518. </table>
  519. <hr />
  520. <div class="log-markup">
  521. File:&nbsp;
  522.  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_wbs_wbb3_2_wbb2.v">pci_wbs_wbb3_2_wbb2.v</a><br />
  523. <a name="rev1.5"></a><a name="HEAD"></a>
  524.  Revision <b>1.5</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_wbs_wbb3_2_wbb2.v?rev=1.5;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_wbs_wbb3_2_wbb2.v?rev=1.5;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_wbs_wbb3_2_wbb2.v?annotate=1.5">annotated</a> - <a href="pci_wbs_wbb3_2_wbb2.v?r1=1.5#rev1.5">select&nbsp;for&nbsp;diffs</a><br />
  525. <i>Mon Aug 16 09:12:01 2004 UTC</i> (2 years, 9 months ago) by <i>mihad</i><br />
  526. Branches: <a href="./pci_wbs_wbb3_2_wbb2.v?only_with_tag=MAIN">MAIN</a><br />
  527. CVS tags: <a href="./pci_wbs_wbb3_2_wbb2.v?only_with_tag=HEAD">HEAD</a><br />
  528. <pre class="log">
  529. Removed unsinthesizable !== comparation.
  530. </pre>
  531. </div>
  532. <hr /><pre>
  533. //////////////////////////////////////////////////////////////////////
  534. ////                                                              ////
  535. ////  File name &quot;pci_wbs_wbb3_2_wbb2.v&quot;                           ////
  536. ////                                                              ////
  537. ////  This file is part of the &quot;PCI bridge&quot; project               ////
  538. ////  http://www.opencores.org/cores/pci/                         ////
  539. ////                                                              ////
  540. ////  Author(s):                                                  ////
  541. ////      - Miha Dolenc (mihad@opencores.org)                     ////
  542. ////                                                              ////
  543. ////                                                              ////
  544. ////                                                              ////
  545. //////////////////////////////////////////////////////////////////////
  546. ////                                                              ////
  547. //// Copyright (C) 2003 Miha Dolenc, mihad@opencores.org          ////
  548. ////                                                              ////
  549. //// This source file may be used and distributed without         ////
  550. //// restriction provided that this copyright statement is not    ////
  551. //// removed from the file and that any derivative work contains  ////
  552. //// the original copyright notice and the associated disclaimer. ////
  553. ////                                                              ////
  554. //// This source file is free software; you can redistribute it   ////
  555. //// and/or modify it under the terms of the GNU Lesser General   ////
  556. //// Public License as published by the Free Software Foundation; ////
  557. //// either version 2.1 of the License, or (at your option) any   ////
  558. //// later version.                                               ////
  559. ////                                                              ////
  560. //// This source is distributed in the hope that it will be       ////
  561. //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  562. //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  563. //// PURPOSE.  See the GNU Lesser General Public License for more ////
  564. //// details.                                                     ////
  565. ////                                                              ////
  566. //// You should have received a copy of the GNU Lesser General    ////
  567. //// Public License along with this source; if not, download it   ////
  568. //// from http://www.opencores.org/lgpl.shtml                     ////
  569. ////                                                              ////
  570. //////////////////////////////////////////////////////////////////////
  571. //
  572. // CVS Revision History
  573. //
  574. // $Log: pci_wbs_wbb3_2_wbb2.v,v $
  575. // Revision 1.5  2004/08/16 09:12:01  mihad
  576. // Removed unsinthesizable !== comparation.
  577. //
  578. // Revision 1.4  2004/01/24 11:54:18  mihad
  579. // Update! SPOCI Implemented!
  580. //
  581. // Revision 1.3  2003/12/19 11:11:30  mihad
  582. // Compact PCI Hot Swap support added.
  583. // New testcases added.
  584. // Specification updated.
  585. // Test application changed to support WB B3 cycles.
  586. //
  587. // Revision 1.2  2003/12/01 16:20:56  simons
  588. // ifdef - endif statements put in separate lines for flint compatibility.
  589. //
  590. // Revision 1.1  2003/08/12 13:58:19  mihad
  591. // Module that converts slave WISHBONE B3 accesses to
  592. // WISHBONE B2 accesses with CAB.
  593. //
  594. //
  596. module pci_wbs_wbb3_2_wbb2
  597. (
  598.     wb_clk_i,
  599.     wb_rst_i,
  601.     wbs_cyc_i,
  602.     wbs_cyc_o,
  603.     wbs_stb_i,
  604.     wbs_stb_o,
  605.     wbs_adr_i,
  606.     wbs_adr_o,
  607.     wbs_dat_i_i,
  608.     wbs_dat_i_o,
  609.     wbs_dat_o_i,
  610.     wbs_dat_o_o,
  611.     wbs_we_i,
  612.     wbs_we_o,
  613.     wbs_sel_i,
  614.     wbs_sel_o,
  615.     wbs_ack_i,
  616.     wbs_ack_o,
  617.     wbs_err_i,
  618.     wbs_err_o,
  619.     wbs_rty_i,
  620.     wbs_rty_o,
  621.     wbs_cti_i,
  622.     wbs_bte_i,
  623.     wbs_cab_o,
  624.     wb_init_complete_i
  625. ) ;
  627. input       wb_clk_i    ;
  628. input       wb_rst_i    ;
  630. input           wbs_cyc_i           ;
  631. output          wbs_cyc_o           ;
  632. input           wbs_stb_i           ;
  633. output          wbs_stb_o           ;
  634. input   [31:0]  wbs_adr_i           ;
  635. output  [31:0]  wbs_adr_o           ;
  636. input   [31:0]  wbs_dat_i_i         ;
  637. output  [31:0]  wbs_dat_i_o         ;
  638. input   [31:0]  wbs_dat_o_i         ;
  639. output  [31:0]  wbs_dat_o_o         ;
  640. input           wbs_we_i            ;
  641. output          wbs_we_o            ;
  642. input   [ 3:0]  wbs_sel_i           ;
  643. output  [ 3:0]  wbs_sel_o           ;
  644. input           wbs_ack_i           ;
  645. output          wbs_ack_o           ;
  646. input           wbs_err_i           ;
  647. output          wbs_err_o           ;
  648. input           wbs_rty_i           ;
  649. output          wbs_rty_o           ;
  650. input   [ 2:0]  wbs_cti_i           ;
  651. input   [ 1:0]  wbs_bte_i           ;
  652. output          wbs_cab_o           ;
  653. input           wb_init_complete_i  ;
  655. reg             wbs_cyc_o           ;
  656. reg     [31:0]  wbs_adr_o           ;
  657. reg     [31:0]  wbs_dat_i_o         ;
  658. reg             wbs_dat_i_o_valid   ;
  659. reg     [31:0]  wbs_dat_o_o         ;
  660. reg             wbs_we_o            ;
  661. reg     [ 3:0]  wbs_sel_o           ;
  662. reg             wbs_ack_o           ;
  663. reg             wbs_err_o           ;
  664. reg             wbs_rty_o           ; 
  665. reg             wbs_cab_o           ;
  667. always@(posedge wb_rst_i or posedge wb_clk_i)
  668. begin
  669.     if (wb_rst_i)
  670.     begin
  671.         wbs_cyc_o           &lt;= 1'b0  ;
  672.         wbs_adr_o           &lt;= 32'h0 ;
  673.         wbs_dat_i_o         &lt;= 32'h0 ;
  674.         wbs_dat_o_o         &lt;= 32'h0 ;
  675.         wbs_sel_o           &lt;= 4'h0  ;
  676.         wbs_we_o            &lt;= 1'b0  ;
  677.         wbs_dat_i_o_valid   &lt;= 1'b0  ;
  678.         wbs_cab_o           &lt;= 1'b0  ;
  679.     end
  680.     else
  681.     begin:transfer_and_transfer_adr_ctrl_blk
  682.         reg start_cycle            ;
  683.         reg [3:0] end_cycle        ;
  684.         reg generate_int_adr       ;
  685.         
  686.         start_cycle  = ~wbs_cyc_o &amp; wbs_cyc_i &amp; wbs_stb_i &amp; ~wbs_ack_o &amp; ~wbs_err_o &amp; ~wbs_rty_o &amp; wb_init_complete_i ;
  687.         
  688.         // there is a few conditions when cycle must be terminated
  689.         // I've put them into bit array for better readability of the code
  691.         // 1st condition - pci bridge is signaling an error
  692.         end_cycle[0] = wbs_err_i ;
  693.     
  694.         // 2nd condition - pci bridge is signaling a retry - that can be ignored via the defines
  695.         end_cycle[1] = wbs_rty_i 
  696.             `ifdef PCI_WBS_B3_RTY_DISABLE 
  697.                 &amp; 1'b0 
  698.             `endif 
  699.                 ;
  701.         // 3rd condition - end non burst cycles as soon as pci bridge response is received
  702.         end_cycle[2] = wbs_cyc_i &amp; wbs_stb_i &amp; wbs_ack_i &amp; ~wbs_cab_o ;
  704.         // 4th condition - end cycle when acknowledge and strobe are both asserted and master is signaling end of burst
  705.         end_cycle[3] = wbs_cyc_i &amp; wbs_stb_i &amp; wbs_ack_o &amp; wbs_cab_o &amp; (wbs_cti_i == 3'b111) ;
  707.         if (wbs_dat_i_o_valid)
  708.         begin
  709.             if (wbs_ack_i | wbs_err_i 
  710.                 `ifdef PCI_WBS_B3_RTY_DISABLE 
  711.                 `else 
  712.                     | wbs_rty_i 
  713.                 `endif
  714.                     )
  715.                 wbs_dat_i_o_valid &lt;= 1'b0 ;
  716.         end
  717.         else
  718.         begin
  719.             if (wbs_cyc_i &amp; wbs_stb_i &amp; wbs_we_i &amp; ~wbs_ack_o &amp; ~wbs_err_o &amp; ~wbs_rty_o &amp; wb_init_complete_i)
  720.             begin
  721.                 wbs_dat_i_o       &lt;= wbs_dat_i_i ;
  722.                 wbs_dat_i_o_valid &lt;= 1'b1 ;
  723.             end
  724.         end
  726.         if (start_cycle)
  727.         begin
  728.             wbs_cyc_o   &lt;= 1'b1         ;
  729.             wbs_sel_o   &lt;= wbs_sel_i    ;
  730.             wbs_we_o    &lt;= wbs_we_i     ;
  731.             
  732.             if (wbs_cti_i == 3'b010)
  733.             begin
  734.                 case (wbs_bte_i)
  735.                 2'b00:  begin 
  736.                             wbs_cab_o &lt;= 1'b1 ; 
  737.                         end
  738.                 2'b01:  begin
  739.                             if (wbs_adr_i[3:2] == 2'b00)
  740.                                 wbs_cab_o &lt;= 1'b1 ;
  741.                             else
  742.                                 wbs_cab_o &lt;= 1'b0 ;
  743.                         end
  744.                 2'b10:  begin
  745.                             if (wbs_adr_i[4:2] == 3'b000)
  746.                                 wbs_cab_o &lt;= 1'b1 ;
  747.                             else
  748.                                 wbs_cab_o &lt;= 1'b0 ;
  749.                         end
  750.                 2'b11:  begin
  751.                             if (wbs_adr_i[5:2] == 4'b0000)
  752.                                 wbs_cab_o &lt;= 1'b1 ;
  753.                             else
  754.                                 wbs_cab_o &lt;= 1'b0 ;
  755.                         end
  756.                 endcase
  757.             end
  758.             else
  759.             begin
  760.                 wbs_cab_o &lt;= 1'b0 ;
  761.             end
  762.         end
  763.         else if ( wbs_cyc_o &amp; (|end_cycle) )
  764.         begin
  765.             wbs_cyc_o &lt;= 1'b0 ;
  766.         end        
  768.         if (start_cycle)
  769.             wbs_adr_o &lt;= wbs_adr_i ;
  770.         else if (wbs_ack_i)
  771.             wbs_adr_o[31:2] &lt;= wbs_adr_o[31:2] + 1'b1 ;
  773.         if (~wbs_we_o &amp; wbs_ack_i)
  774.             wbs_dat_o_o &lt;= wbs_dat_o_i ;
  775.     end
  776. end
  778. always@(posedge wb_rst_i or posedge wb_clk_i)
  779. begin
  780.     if (wb_rst_i)
  781.     begin
  782.         wbs_ack_o &lt;= 1'b0 ;
  783.         wbs_err_o &lt;= 1'b0 ;
  784.         wbs_rty_o &lt;= 1'b0 ;
  785.     end
  786.     else
  787.     begin
  788.         if (wbs_ack_o)
  789.             wbs_ack_o &lt;= wbs_ack_i | ~wbs_stb_i ;
  790.         else
  791.             wbs_ack_o &lt;= wbs_ack_i ;
  792.         
  793.         if (wbs_err_o)
  794.             wbs_err_o &lt;= ~wbs_stb_i ;
  795.         else
  796.             wbs_err_o &lt;= wbs_err_i ;
  798.     `ifdef PCI_WBS_B3_RTY_DISABLE
  799.         wbs_rty_o &lt;= 1'b0 ;
  800.     `else
  801.         if (wbs_rty_o)
  802.             wbs_rty_o &lt;= ~wbs_stb_i ;
  803.         else
  804.             wbs_rty_o &lt;= wbs_rty_i ;
  805.     `endif
  806.     end
  807. end
  809. assign wbs_stb_o = (wbs_cyc_o &amp; ~wbs_we_o &amp; ~wbs_ack_o &amp; ~wbs_err_o &amp; ~wbs_rty_o) |
  810.                    (wbs_cyc_o &amp; wbs_stb_i &amp; wbs_cab_o &amp; ~wbs_we_o &amp; wbs_cti_i != 3'b111) |
  811.                    (wbs_cyc_o &amp; wbs_we_o &amp; wbs_dat_i_o_valid) ;
  813. endmodule
  814. </pre>
  815. <hr />
  816. <address><span style="font-size: smaller">FreeBSD-CVSweb &lt;<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>&gt;</span></address>
  817. </body>
  818. </html>
  828. <!-- pf_body_end -->
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  832. </tr></table>
  834. <xcenter>
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  840. &nbsp;
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