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pci_wbr_fifo_control.v
资源名称：pci_core_verilog.rar　[点击查看]
上传用户：quan1896
上传日期：2014-05-14
资源大小：211k
文件大小：31k
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并行计算

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pci_wbr_fifo_control.v：源码内容
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  516. <a href="./pci_wbr_fifo_control.v#rev1.4"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_wbr_fifo_control.v#rev1.4">pci_wbr_fifo_control.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td>  <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td>
  517.  </tr>
  518. </table>
  519. <hr />
  520. <div class="log-markup">
  521. File:&nbsp;
  522.  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_wbr_fifo_control.v">pci_wbr_fifo_control.v</a><br />
  523. <a name="rev1.4"></a><a name="wb2hpi"></a><a name="rel_WB_B3"></a><a name="rel_9"></a><a name="rel_8"></a><a name="rel_7"></a><a name="rel_6"></a><a name="rel_13"></a><a name="rel_12"></a><a name="rel_11"></a><a name="rel_10"></a><a name="asyst_3"></a><a name="asyst_2"></a><a name="HEAD"></a>
  524.  Revision <b>1.4</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_wbr_fifo_control.v?rev=1.4;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_wbr_fifo_control.v?rev=1.4;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_wbr_fifo_control.v?annotate=1.4">annotated</a> - <a href="pci_wbr_fifo_control.v?r1=1.4#rev1.4">select&nbsp;for&nbsp;diffs</a><br />
  525. <i>Thu Aug 14 13:06:03 2003 UTC</i> (3 years, 9 months ago) by <i>simons</i><br />
  526. Branches: <a href="./pci_wbr_fifo_control.v?only_with_tag=MAIN">MAIN</a><br />
  527. CVS tags: <a href="./pci_wbr_fifo_control.v?only_with_tag=wb2hpi">wb2hpi</a>,
  528. <a href="./pci_wbr_fifo_control.v?only_with_tag=rel_WB_B3">rel_WB_B3</a>,
  529. <a href="./pci_wbr_fifo_control.v?only_with_tag=rel_9">rel_9</a>,
  530. <a href="./pci_wbr_fifo_control.v?only_with_tag=rel_8">rel_8</a>,
  531. <a href="./pci_wbr_fifo_control.v?only_with_tag=rel_7">rel_7</a>,
  532. <a href="./pci_wbr_fifo_control.v?only_with_tag=rel_6">rel_6</a>,
  533. <a href="./pci_wbr_fifo_control.v?only_with_tag=rel_13">rel_13</a>,
  534. <a href="./pci_wbr_fifo_control.v?only_with_tag=rel_12">rel_12</a>,
  535. <a href="./pci_wbr_fifo_control.v?only_with_tag=rel_11">rel_11</a>,
  536. <a href="./pci_wbr_fifo_control.v?only_with_tag=rel_10">rel_10</a>,
  537. <a href="./pci_wbr_fifo_control.v?only_with_tag=asyst_3">asyst_3</a>,
  538. <a href="./pci_wbr_fifo_control.v?only_with_tag=asyst_2">asyst_2</a>,
  539. <a href="./pci_wbr_fifo_control.v?only_with_tag=HEAD">HEAD</a><br />
  540. <pre class="log">
  541. synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
  542. </pre>
  543. </div>
  544. <hr /><pre>
  545. //////////////////////////////////////////////////////////////////////
  546. ////                                                              ////
  547. ////  File name &quot;wbr_fifo_control.v&quot;                              ////
  548. ////                                                              ////
  549. ////  This file is part of the &quot;PCI bridge&quot; project               ////
  550. ////  http://www.opencores.org/cores/pci/                         ////
  551. ////                                                              ////
  552. ////  Author(s):                                                  ////
  553. ////      - Miha Dolenc (mihad@opencores.org)                     ////
  554. ////                                                              ////
  555. ////  All additional information is avaliable in the README       ////
  556. ////  file.                                                       ////
  557. ////                                                              ////
  558. ////                                                              ////
  559. //////////////////////////////////////////////////////////////////////
  560. ////                                                              ////
  561. //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
  562. ////                                                              ////
  563. //// This source file may be used and distributed without         ////
  564. //// restriction provided that this copyright statement is not    ////
  565. //// removed from the file and that any derivative work contains  ////
  566. //// the original copyright notice and the associated disclaimer. ////
  567. ////                                                              ////
  568. //// This source file is free software; you can redistribute it   ////
  569. //// and/or modify it under the terms of the GNU Lesser General   ////
  570. //// Public License as published by the Free Software Foundation; ////
  571. //// either version 2.1 of the License, or (at your option) any   ////
  572. //// later version.                                               ////
  573. ////                                                              ////
  574. //// This source is distributed in the hope that it will be       ////
  575. //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  576. //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  577. //// PURPOSE.  See the GNU Lesser General Public License for more ////
  578. //// details.                                                     ////
  579. ////                                                              ////
  580. //// You should have received a copy of the GNU Lesser General    ////
  581. //// Public License along with this source; if not, download it   ////
  582. //// from http://www.opencores.org/lgpl.shtml                     ////
  583. ////                                                              ////
  584. //////////////////////////////////////////////////////////////////////
  585. //
  586. // CVS Revision History
  587. //
  588. // $Log: pci_wbr_fifo_control.v,v $
  589. // Revision 1.4  2003/08/14 13:06:03  simons
  590. // synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
  591. //
  592. // Revision 1.3  2003/07/29 08:20:11  mihad
  593. // Found and simulated the problem in the synchronization logic.
  594. // Repaired the synchronization logic in the FIFOs.
  595. //
  596. // Revision 1.2  2003/03/26 13:16:18  mihad
  597. // Added the reset value parameter to the synchronizer flop module.
  598. // Added resets to all synchronizer flop instances.
  599. // Repaired initial sync value in fifos.
  600. //
  601. // Revision 1.1  2003/01/27 16:49:31  mihad
  602. // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  603. //
  604. // Revision 1.6  2002/11/27 20:36:12  mihad
  605. // Changed the code a bit to make it more readable.
  606. // Functionality not changed in any way.
  607. // More robust synchronization in fifos is still pending.
  608. //
  609. // Revision 1.5  2002/09/30 16:03:04  mihad
  610. // Added meta flop module for easier meta stable FF identification during synthesis
  611. //
  612. // Revision 1.4  2002/09/25 15:53:52  mihad
  613. // Removed all logic from asynchronous reset network
  614. //
  615. // Revision 1.3  2002/02/01 15:25:13  mihad
  616. // Repaired a few bugs, updated specification, added test bench files and design document
  617. //
  618. // Revision 1.2  2001/10/05 08:14:30  mihad
  619. // Updated all files with inclusion of timescale file for simulation purposes.
  620. //
  621. // Revision 1.1.1.1  2001/10/02 15:33:47  mihad
  622. // New project directory structure
  623. //
  624. //
  626. /* FIFO_CONTROL module provides read/write address and status generation for
  627.    FIFOs implemented with standard dual port SRAM cells in ASIC or FPGA designs */
  628. `include &quot;pci_constants.v&quot;
  629. // synopsys translate_off
  630. `include &quot;timescale.v&quot;
  631. // synopsys translate_on
  633. module pci_wbr_fifo_control
  634. (
  635.     rclock_in,
  636.     wclock_in,
  637.     renable_in,
  638.     wenable_in,
  639.     reset_in,
  640.     flush_in,
  641.     empty_out,
  642.     waddr_out,
  643.     raddr_out,
  644.     rallow_out,
  645.     wallow_out
  646. ) ;
  648. parameter ADDR_LENGTH = 7 ;
  650. // independent clock inputs - rclock_in = read clock, wclock_in = write clock
  651. input  rclock_in, wclock_in;
  653. // enable inputs - read address changes on rising edge of rclock_in when reads are allowed
  654. //                 write address changes on rising edge of wclock_in when writes are allowed
  655. input  renable_in, wenable_in;
  657. // reset input
  658. input  reset_in;
  660. // flush input
  661. input flush_in ;
  663. // empty status output
  664. output empty_out;
  666. // read and write addresses outputs
  667. output [(ADDR_LENGTH - 1):0] waddr_out, raddr_out;
  669. // read and write allow outputs
  670. output rallow_out, wallow_out ;
  672. // read address register
  673. reg [(ADDR_LENGTH - 1):0] raddr ;
  675. // write address register
  676. reg [(ADDR_LENGTH - 1):0] waddr;
  677. assign waddr_out = waddr ;
  679. // grey code register
  680. reg [(ADDR_LENGTH - 1):0] wgrey_addr ;
  682. // next write gray address calculation - bitwise xor between address and shifted address
  683. wire [(ADDR_LENGTH - 2):0] calc_wgrey_next  = waddr[(ADDR_LENGTH - 1):1] ^ waddr[(ADDR_LENGTH - 2):0] ;
  685. // grey code register
  686. reg [(ADDR_LENGTH - 1):0] rgrey_addr ;
  688. // next read gray address calculation - bitwise xor between address and shifted address
  689. wire [(ADDR_LENGTH - 2):0] calc_rgrey_next  = raddr[(ADDR_LENGTH - 1):1] ^ raddr[(ADDR_LENGTH - 2):0] ;
  691. // FF for registered empty flag
  692. wire empty ;
  694. // write allow wire
  695. wire wallow = wenable_in ;
  697. // write allow output assignment
  698. assign wallow_out = wallow ;
  700. // read allow wire
  701. wire rallow ;
  703. // clear generation for FFs and registers
  704. wire clear = reset_in /*|| flush_in*/ ; // flush changed to synchronous operation
  706. assign empty_out = empty ;
  708. //rallow generation
  709. assign rallow = renable_in &amp;&amp; !empty ; // reads allowed if read enable is high and FIFO is not empty
  711. // rallow output assignment
  712. assign rallow_out = renable_in ;
  714. // at any clock edge that rallow is high, this register provides next read address, so wait cycles are not necessary
  715. // when FIFO is empty, this register provides actual read address, so first location can be read
  716. reg [(ADDR_LENGTH - 1):0] raddr_plus_one ;
  718. // address output mux - when FIFO is empty, current actual address is driven out, when it is non - empty next address is driven out
  719. // done for zero wait state burst
  720. assign raddr_out = rallow ? raddr_plus_one : raddr ;
  722. always@(posedge rclock_in or posedge clear)
  723. begin
  724.     if (clear)
  725.     begin
  726.         raddr_plus_one &lt;= #`FF_DELAY 2 ;
  727.         raddr          &lt;= #`FF_DELAY 1 ;
  728.     end
  729.     else if (flush_in)
  730.     begin
  731.         raddr_plus_one &lt;= #`FF_DELAY waddr + 1'b1 ; 
  732.         raddr          &lt;= #`FF_DELAY waddr ;
  733.     end
  734.     else if (rallow)
  735.     begin
  736.         raddr_plus_one &lt;= #`FF_DELAY raddr_plus_one + 1'b1 ;
  737.         raddr          &lt;= #`FF_DELAY raddr_plus_one ;
  738.     end
  739. end
  741. /*-----------------------------------------------------------------------------------------------
  742. Read address control consists of Read address counter and Grey Address register
  743. --------------------------------------------------------------------------------------------------*/
  744. // grey coded address
  745. always@(posedge rclock_in or posedge clear)
  746. begin
  747.     if (clear)
  748.     begin
  749.         rgrey_addr &lt;= #`FF_DELAY 0 ;
  750.     end
  751.     else if (flush_in)
  752.     begin
  753.         rgrey_addr &lt;= #`FF_DELAY wgrey_addr ;   // when flushed, copy value from write side
  754.     end
  755.     else if (rallow)
  756.     begin
  757.         rgrey_addr &lt;= #`FF_DELAY {raddr[ADDR_LENGTH - 1], calc_rgrey_next} ;
  758.     end
  759. end
  761. /*--------------------------------------------------------------------------------------------
  762. Write address control consists of write address counter and Grey Code Register
  763. ----------------------------------------------------------------------------------------------*/
  764. // grey coded address for status generation in write clock domain
  765. always@(posedge wclock_in or posedge clear)
  766. begin
  767.     if (clear)
  768.     begin
  769.         wgrey_addr &lt;= #1 0 ;
  770.     end
  771.     else
  772.     if (wallow)
  773.     begin
  774.         wgrey_addr &lt;= #1 {waddr[(ADDR_LENGTH - 1)], calc_wgrey_next} ;
  775.     end
  776. end
  778. // write address counter - nothing special except initial value
  779. always@(posedge wclock_in or posedge clear)
  780. begin
  781.     if (clear)
  782.         // initial value is 1
  783.         waddr &lt;= #`FF_DELAY 1 ;
  784.     else
  785.     if (wallow)
  786.         waddr &lt;= #`FF_DELAY waddr + 1'b1 ;
  787. end
  790. /*------------------------------------------------------------------------------------------------------------------------------
  791. Empty control:
  792. Gray coded write address pointer is synchronized to read clock domain and compared to Gray coded read address pointer.
  793. If they are equal, fifo is empty.
  794. --------------------------------------------------------------------------------------------------------------------------------*/
  795. wire [(ADDR_LENGTH - 1):0] rclk_sync_wgrey_addr ;
  796. reg  [(ADDR_LENGTH - 1):0] rclk_wgrey_addr ;
  797. pci_synchronizer_flop #(ADDR_LENGTH, 0) i_synchronizer_reg_wgrey_addr
  798. (
  799.     .data_in        (wgrey_addr),
  800.     .clk_out        (rclock_in),
  801.     .sync_data_out  (rclk_sync_wgrey_addr),
  802.     .async_reset    (clear)
  803. ) ;
  805. always@(posedge rclock_in or posedge clear)
  806. begin
  807.     if (clear)
  808.         rclk_wgrey_addr &lt;= #`FF_DELAY 0 ;
  809.     else
  810.         rclk_wgrey_addr &lt;= #`FF_DELAY rclk_sync_wgrey_addr ;
  811. end
  813. assign empty = (rgrey_addr == rclk_wgrey_addr) ;
  814. endmodule
  815. </pre>
  816. <hr />
  817. <address><span style="font-size: smaller">FreeBSD-CVSweb &lt;<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>&gt;</span></address>
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  915. </td></tr>
  916. <tr><td>
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  921. </td>
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  927. <!-- pf_footer_start -->
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