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bus_commands.v
资源名称：pci_core_verilog.rar　[点击查看]
上传用户：quan1896
上传日期：2014-05-14
资源大小：211k
文件大小：25k
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并行计算

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bus_commands.v：源码内容
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  516. <a href="./bus_commands.v#rev1.4"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./bus_commands.v#rev1.4">bus_commands.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td>  <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td>
  517.  </tr>
  518. </table>
  519. <hr />
  520. <div class="log-markup">
  521. File:&nbsp;
  522.  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/bus_commands.v">bus_commands.v</a><br />
  523. <a name="rev1.4"></a><a name="wb2hpi"></a><a name="rel_WB_B3"></a><a name="rel_9"></a><a name="rel_8"></a><a name="rel_7"></a><a name="rel_6"></a><a name="rel_5"></a><a name="rel_4"></a><a name="rel_3"></a><a name="rel_2"></a><a name="rel_13"></a><a name="rel_12"></a><a name="rel_11"></a><a name="rel_10"></a><a name="rel_1"></a><a name="asyst_3"></a><a name="asyst_2"></a><a name="HEAD"></a>
  524.  Revision <b>1.4</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/bus_commands.v?rev=1.4;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="bus_commands.v?rev=1.4;content-type=text%2Fplain" class="display-link">text</a>, <a href="bus_commands.v?annotate=1.4">annotated</a> - <a href="bus_commands.v?r1=1.4#rev1.4">select&nbsp;for&nbsp;diffs</a><br />
  525. <i>Thu Aug 22 13:28:05 2002 UTC</i> (4 years, 8 months ago) by <i>mihad</i><br />
  526. Branches: <a href="./bus_commands.v?only_with_tag=MAIN">MAIN</a><br />
  527. CVS tags: <a href="./bus_commands.v?only_with_tag=wb2hpi">wb2hpi</a>,
  528. <a href="./bus_commands.v?only_with_tag=rel_WB_B3">rel_WB_B3</a>,
  529. <a href="./bus_commands.v?only_with_tag=rel_9">rel_9</a>,
  530. <a href="./bus_commands.v?only_with_tag=rel_8">rel_8</a>,
  531. <a href="./bus_commands.v?only_with_tag=rel_7">rel_7</a>,
  532. <a href="./bus_commands.v?only_with_tag=rel_6">rel_6</a>,
  533. <a href="./bus_commands.v?only_with_tag=rel_5">rel_5</a>,
  534. <a href="./bus_commands.v?only_with_tag=rel_4">rel_4</a>,
  535. <a href="./bus_commands.v?only_with_tag=rel_3">rel_3</a>,
  536. <a href="./bus_commands.v?only_with_tag=rel_2">rel_2</a>,
  537. <a href="./bus_commands.v?only_with_tag=rel_13">rel_13</a>,
  538. <a href="./bus_commands.v?only_with_tag=rel_12">rel_12</a>,
  539. <a href="./bus_commands.v?only_with_tag=rel_11">rel_11</a>,
  540. <a href="./bus_commands.v?only_with_tag=rel_10">rel_10</a>,
  541. <a href="./bus_commands.v?only_with_tag=rel_1">rel_1</a>,
  542. <a href="./bus_commands.v?only_with_tag=asyst_3">asyst_3</a>,
  543. <a href="./bus_commands.v?only_with_tag=asyst_2">asyst_2</a>,
  544. <a href="./bus_commands.v?only_with_tag=HEAD">HEAD</a><br />
  545. <pre class="log">
  546. Updated for synthesis purposes. Gate level simulation was failing in some configurations
  547. </pre>
  548. </div>
  549. <hr /><pre>
  550. //////////////////////////////////////////////////////////////////////
  551. ////                                                              ////
  552. ////  File name &quot;bus_commands.v&quot;                                  ////
  553. ////                                                              ////
  554. ////  This file is part of the &quot;PCI bridge&quot; project               ////
  555. ////  http://www.opencores.org/cores/pci/                         ////
  556. ////                                                              ////
  557. ////  Author(s):                                                  ////
  558. ////      - Miha Dolenc (mihad@opencores.org)                     ////
  559. ////                                                              ////
  560. ////  All additional information is avaliable in the README.pdf   ////
  561. ////  file.                                                       ////
  562. ////                                                              ////
  563. ////                                                              ////
  564. //////////////////////////////////////////////////////////////////////
  565. ////                                                              ////
  566. //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
  567. ////                                                              ////
  568. //// This source file may be used and distributed without         ////
  569. //// restriction provided that this copyright statement is not    ////
  570. //// removed from the file and that any derivative work contains  ////
  571. //// the original copyright notice and the associated disclaimer. ////
  572. ////                                                              ////
  573. //// This source file is free software; you can redistribute it   ////
  574. //// and/or modify it under the terms of the GNU Lesser General   ////
  575. //// Public License as published by the Free Software Foundation; ////
  576. //// either version 2.1 of the License, or (at your option) any   ////
  577. //// later version.                                               ////
  578. ////                                                              ////
  579. //// This source is distributed in the hope that it will be       ////
  580. //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  581. //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  582. //// PURPOSE.  See the GNU Lesser General Public License for more ////
  583. //// details.                                                     ////
  584. ////                                                              ////
  585. //// You should have received a copy of the GNU Lesser General    ////
  586. //// Public License along with this source; if not, download it   ////
  587. //// from http://www.opencores.org/lgpl.shtml                     ////
  588. ////                                                              ////
  589. //////////////////////////////////////////////////////////////////////
  590. //
  591. // CVS Revision History
  592. //
  593. // $Log: bus_commands.v,v $
  594. // Revision 1.4  2002/08/22 13:28:05  mihad
  595. // Updated for synthesis purposes. Gate level simulation was failing in some configurations
  596. //
  597. // Revision 1.3  2002/02/01 15:25:12  mihad
  598. // Repaired a few bugs, updated specification, added test bench files and design document
  599. //
  600. // Revision 1.2  2001/10/05 08:14:28  mihad
  601. // Updated all files with inclusion of timescale file for simulation purposes.
  602. //
  603. // Revision 1.1.1.1  2001/10/02 15:33:47  mihad
  604. // New project directory structure
  605. //
  606. //
  608. // definitions of PCI bus commands | used by PCI Master | used by PCI Target
  609. `define BC_IACK             4'h0  // yes no
  610. `define BC_SPECIAL          4'h1  // no no
  611. `define BC_IO_READ          4'h2  // yes yes
  612. `define BC_IO_WRITE         4'h3  // yes yes
  613. `define BC_RESERVED0        4'h4  // no no
  614. `define BC_RESERVED1        4'h5  // no no
  615. `define BC_MEM_READ         4'h6  // yes yes
  616. `define BC_MEM_WRITE        4'h7  // yes yes
  617. `define BC_RESERVED2        4'h8  // no no
  618. `define BC_RESERVED3        4'h9  // no no
  619. `define BC_CONF_READ        4'hA  // yes yes
  620. `define BC_CONF_WRITE       4'hB  // yes yes
  621. `define BC_MEM_READ_MUL     4'hC  // yes yes
  622. `define BC_DUAL_ADDR_CYC    4'hD  // no no
  623. `define BC_MEM_READ_LN      4'hE  // yes yes
  624. `define BC_MEM_WRITE_INVAL  4'hF  // no yes
  626. // common bits for configuration cycle commands
  627. `define BC_CONF_RW 3'b101 
  628. // common bits for io cycle commands
  629. `define BC_IO_RW 3'b001
  630. </pre>
  631. <hr />
  632. <address><span style="font-size: smaller">FreeBSD-CVSweb &lt;<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>&gt;</span></address>
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