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pci_wbw_wbr_fifos.v
资源名称：pci_core_verilog.rar　[点击查看]
上传用户：quan1896
上传日期：2014-05-14
资源大小：211k
文件大小：45k
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并行计算

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pci_wbw_wbr_fifos.v：源码内容
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  516. <a href="./pci_wbw_wbr_fifos.v#rev1.7"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_wbw_wbr_fifos.v#rev1.7">pci_wbw_wbr_fifos.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td>  <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td>
  517.  </tr>
  518. </table>
  519. <hr />
  520. <div class="log-markup">
  521. File:&nbsp;
  522.  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_wbw_wbr_fifos.v">pci_wbw_wbr_fifos.v</a><br />
  523. <a name="rev1.7"></a><a name="HEAD"></a>
  524.  Revision <b>1.7</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_wbw_wbr_fifos.v?rev=1.7;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_wbw_wbr_fifos.v?rev=1.7;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_wbw_wbr_fifos.v?annotate=1.7">annotated</a> - <a href="pci_wbw_wbr_fifos.v?r1=1.7#rev1.7">select&nbsp;for&nbsp;diffs</a><br />
  525. <i>Tue Jul  4 13:16:19 2006 UTC</i> (10 months, 2 weeks ago) by <i>mihad</i><br />
  526. Branches: <a href="./pci_wbw_wbr_fifos.v?only_with_tag=MAIN">MAIN</a><br />
  527. CVS tags: <a href="./pci_wbw_wbr_fifos.v?only_with_tag=HEAD">HEAD</a><br />
  528. <pre class="log">
  529. Write burst performance patch applied.
  530. Not tested. Everything should be backwards
  531. compatible, since functional code is ifdefed.
  532. </pre>
  533. </div>
  534. <hr /><pre>
  535. //////////////////////////////////////////////////////////////////////
  536. ////                                                              ////
  537. ////  File name &quot;wbw_wbr_fifos.v&quot;                                 ////
  538. ////                                                              ////
  539. ////  This file is part of the &quot;PCI bridge&quot; project               ////
  540. ////  http://www.opencores.org/cores/pci/                         ////
  541. ////                                                              ////
  542. ////  Author(s):                                                  ////
  543. ////      - Miha Dolenc (mihad@opencores.org)                     ////
  544. ////                                                              ////
  545. ////  All additional information is avaliable in the README       ////
  546. ////  file.                                                       ////
  547. ////                                                              ////
  548. ////                                                              ////
  549. //////////////////////////////////////////////////////////////////////
  550. ////                                                              ////
  551. //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
  552. ////                                                              ////
  553. //// This source file may be used and distributed without         ////
  554. //// restriction provided that this copyright statement is not    ////
  555. //// removed from the file and that any derivative work contains  ////
  556. //// the original copyright notice and the associated disclaimer. ////
  557. ////                                                              ////
  558. //// This source file is free software; you can redistribute it   ////
  559. //// and/or modify it under the terms of the GNU Lesser General   ////
  560. //// Public License as published by the Free Software Foundation; ////
  561. //// either version 2.1 of the License, or (at your option) any   ////
  562. //// later version.                                               ////
  563. ////                                                              ////
  564. //// This source is distributed in the hope that it will be       ////
  565. //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  566. //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  567. //// PURPOSE.  See the GNU Lesser General Public License for more ////
  568. //// details.                                                     ////
  569. ////                                                              ////
  570. //// You should have received a copy of the GNU Lesser General    ////
  571. //// Public License along with this source; if not, download it   ////
  572. //// from http://www.opencores.org/lgpl.shtml                     ////
  573. ////                                                              ////
  574. //////////////////////////////////////////////////////////////////////
  575. //
  576. // CVS Revision History
  577. //
  578. // $Log: pci_wbw_wbr_fifos.v,v $
  579. // Revision 1.7  2006/07/04 13:16:19  mihad
  580. // Write burst performance patch applied.
  581. // Not tested. Everything should be backwards
  582. // compatible, since functional code is ifdefed.
  583. //
  584. // Revision 1.6  2003/12/19 11:11:30  mihad
  585. // Compact PCI Hot Swap support added.
  586. // New testcases added.
  587. // Specification updated.
  588. // Test application changed to support WB B3 cycles.
  589. //
  590. // Revision 1.5  2003/10/17 09:11:52  markom
  591. // mbist signals updated according to newest convention
  592. //
  593. // Revision 1.4  2003/08/14 13:06:03  simons
  594. // synchronizer_flop replaced with pci_synchronizer_flop, artisan ram instance updated.
  595. //
  596. // Revision 1.3  2003/03/26 13:16:18  mihad
  597. // Added the reset value parameter to the synchronizer flop module.
  598. // Added resets to all synchronizer flop instances.
  599. // Repaired initial sync value in fifos.
  600. //
  601. // Revision 1.2  2003/01/30 22:01:09  mihad
  602. // Updated synchronization in top level fifo modules.
  603. //
  604. // Revision 1.1  2003/01/27 16:49:31  mihad
  605. // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  606. //
  607. // Revision 1.9  2002/10/18 03:36:37  tadejm
  608. // Changed wrong signal name mbist_sen into mbist_ctrl_i.
  609. //
  610. // Revision 1.8  2002/10/17 22:49:22  tadejm
  611. // Changed BIST signals for RAMs.
  612. //
  613. // Revision 1.7  2002/10/11 10:09:01  mihad
  614. // Added additional testcase and changed rst name in BIST to trst
  615. //
  616. // Revision 1.6  2002/10/08 17:17:06  mihad
  617. // Added BIST signals for RAMs.
  618. //
  619. // Revision 1.5  2002/09/30 16:03:04  mihad
  620. // Added meta flop module for easier meta stable FF identification during synthesis
  621. //
  622. // Revision 1.4  2002/09/25 15:53:52  mihad
  623. // Removed all logic from asynchronous reset network
  624. //
  625. // Revision 1.3  2002/02/01 15:25:14  mihad
  626. // Repaired a few bugs, updated specification, added test bench files and design document
  627. //
  628. // Revision 1.2  2001/10/05 08:20:12  mihad
  629. // Updated all files with inclusion of timescale file for simulation purposes.
  630. //
  631. // Revision 1.1.1.1  2001/10/02 15:33:47  mihad
  632. // New project directory structure
  633. //
  634. //
  636. `include &quot;pci_constants.v&quot;
  638. // synopsys translate_off
  639. `include &quot;timescale.v&quot;
  640. // synopsys translate_on
  644. module pci_wbw_wbr_fifos
  645. (
  646.     wb_clock_in,
  647.     pci_clock_in,
  648.     reset_in,
  649.     wbw_wenable_in,
  650.     wbw_addr_data_in,
  651.     wbw_cbe_in,
  652.     wbw_control_in,
  653.     wbw_renable_in,
  654.     wbw_addr_data_out,
  655.     wbw_cbe_out,
  656.     wbw_control_out,
  657. //    wbw_flush_in,         write fifo flush not used
  658.     wbw_almost_full_out,
  659.     wbw_full_out,
  660.     wbw_empty_out,
  661.     wbw_transaction_ready_out,
  662.  wbw_half_full_out, ////Robert, burst issue
  663.     wbr_wenable_in,
  664.     wbr_data_in,
  665.     wbr_be_in,
  666.     wbr_control_in,
  667.     wbr_renable_in,
  668.     wbr_data_out,
  669.     wbr_be_out,
  670.     wbr_control_out,
  671.     wbr_flush_in,
  672.     wbr_empty_out
  673.  
  675. `ifdef PCI_BIST
  676.     ,
  677.     // debug chain signals
  678.     mbist_si_i,       // bist scan serial in
  679.     mbist_so_o,       // bist scan serial out
  680.     mbist_ctrl_i        // bist chain shift control
  681. `endif                        
  682. ) ;
  684. /*-----------------------------------------------------------------------------------------------------------
  685. System inputs:
  686. wb_clock_in - WISHBONE bus clock
  687. pci_clock_in - PCI bus clock
  688. reset_in - reset from control logic
  689. -------------------------------------------------------------------------------------------------------------*/
  690. input wb_clock_in, pci_clock_in, reset_in ;
  692. /*-----------------------------------------------------------------------------------------------------------
  693. WISHBONE WRITE FIFO interface signals prefixed with wbw_ - FIFO is used for posted writes initiated by
  694. WISHBONE master, traveling through FIFO and are completed on PCI by PCI master interface
  696. write enable signal:
  697. wbw_wenable_in = write enable input for WBW_FIFO - driven by WISHBONE slave interface
  699. data input signals:
  700. wbw_addr_data_in = data input - data from WISHBONE bus - first entry of transaction is address others are data entries
  701. wbw_cbe_in       = bus command/byte enable(~SEL[3:0]) input - first entry of transaction is bus command, other are byte enables
  702. wbw_control_in   = control input - encoded control bus input
  704. read enable signal:
  705. wbw_renable_in = read enable input driven by PCI master interface
  707. data output signals:
  708. wbw_addr_data_out = data output - data from WISHBONE bus - first entry of transaction is address, others are data entries
  709. wbw_cbe_out      = bus command/byte enable output - first entry of transaction is bus command, others are byte enables
  710. wbw_control_out = control input - encoded control bus input
  712. status signals - monitored by various resources in the core
  713. wbw_flush_in = flush signal input for WBW_FIFO - when asserted, fifo is flushed(emptied)
  714. wbw_almost_full_out = almost full output from WBW_FIFO
  715. wbw_full_out = full output from WBW_FIFO
  716. wbw_empty_out = empty output from WBW_FIFO
  717. wbw_transaction_ready_out = output indicating that one complete transaction is waiting in WBW_FIFO
  718. -----------------------------------------------------------------------------------------------------------*/
  719. // input control and data
  720. input        wbw_wenable_in ;
  721. input [31:0] wbw_addr_data_in ;
  722. input [3:0]  wbw_cbe_in ;
  723. input [3:0]  wbw_control_in ;
  725. // output control and data
  726. input         wbw_renable_in ;
  727. output [31:0] wbw_addr_data_out ;
  728. output [3:0]  wbw_cbe_out ;
  729. output [3:0]  wbw_control_out ;
  731. // flush input
  732. // input wbw_flush_in ; // not used
  734. // status outputs
  735. output wbw_almost_full_out ;
  736. output wbw_full_out ;
  737. output wbw_empty_out ;
  738. output wbw_transaction_ready_out ;
  739. output wbw_half_full_out; ////Robert, burst issue
  741. /*-----------------------------------------------------------------------------------------------------------
  742. WISHBONE READ FIFO interface signals prefixed with wbr_ - FIFO is used for holding delayed read completions
  743. initiated by master on WISHBONE bus and completed on PCI bus,
  745. write enable signal:
  746. wbr_wenable_in = write enable input for WBR_FIFO - driven by PCI master interface
  748. data input signals:
  749. wbr_data_in      = data input - data from PCI bus - there is no address entry here, since address is stored in separate register
  750. wbr_be_in        = byte enable(~BE#[3:0]) input - byte enables - same through one transaction
  751. wbr_control_in   = control input - encoded control bus input
  753. read enable signal:
  754. wbr_renable_in = read enable input driven by WISHBONE slave interface
  756. data output signals:
  757. wbr_data_out = data output - data from PCI bus
  758. wbr_be_out      = byte enable output(~#BE)
  759. wbr_control_out = control output - encoded control bus output
  761. status signals - monitored by various resources in the core
  762. wbr_flush_in = flush signal input for WBR_FIFO - when asserted, fifo is flushed(emptied)
  763. wbr full_out = full output from WBR_FIFO
  764. wbr_empty_out = empty output from WBR_FIFO
  765. -----------------------------------------------------------------------------------------------------------*/
  766. // input control and data
  767. input        wbr_wenable_in ;
  768. input [31:0] wbr_data_in ;
  769. input [3:0]  wbr_be_in ;
  770. input [3:0]  wbr_control_in ;
  772. // output control and data
  773. input         wbr_renable_in ;
  774. output [31:0] wbr_data_out ;
  775. output [3:0]  wbr_be_out ;
  776. output [3:0]  wbr_control_out ;
  778. // flush input
  779. input wbr_flush_in ;
  781. output wbr_empty_out ;
  783. `ifdef PCI_BIST
  784. /*-----------------------------------------------------
  785. BIST debug chain port signals
  786. -----------------------------------------------------*/
  787. input   mbist_si_i;       // bist scan serial in
  788. output  mbist_so_o;       // bist scan serial out
  789. input [`PCI_MBIST_CTRL_WIDTH - 1:0] mbist_ctrl_i;       // bist chain shift control
  790. `endif
  792. /*-----------------------------------------------------------------------------------------------------------
  793. FIFO depth parameters:
  794. WBW_DEPTH = defines WBW_FIFO depth
  795. WBR_DEPTH = defines WBR_FIFO depth
  796. WBW_ADDR_LENGTH = defines WBW_FIFO's location address length = log2(WBW_DEPTH)
  797. WBR_ADDR_LENGTH = defines WBR_FIFO's location address length = log2(WBR_DEPTH)
  798. -----------------------------------------------------------------------------------------------------------*/
  799. parameter WBW_DEPTH = `WBW_DEPTH ;
  800. parameter WBW_ADDR_LENGTH = `WBW_ADDR_LENGTH ;
  801. parameter WBR_DEPTH = `WBR_DEPTH ;
  802. parameter WBR_ADDR_LENGTH = `WBR_ADDR_LENGTH ;
  804. /*-----------------------------------------------------------------------------------------------------------
  805. wbw_wallow = WBW_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
  806. wbw_rallow = WBW_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
  807. -----------------------------------------------------------------------------------------------------------*/
  808. wire wbw_wallow ;
  809. wire wbw_rallow ;
  811. /*-----------------------------------------------------------------------------------------------------------
  812. wbr_wallow = WBR_FIFO write allow wire - writes to FIFO are allowed when FIFO isn't full and write enable is 1
  813. wbr_rallow = WBR_FIFO read allow wire - reads from FIFO are allowed when FIFO isn't empty and read enable is 1
  814. -----------------------------------------------------------------------------------------------------------*/
  815. wire wbr_wallow ;
  816. wire wbr_rallow ;
  818. /*-----------------------------------------------------------------------------------------------------------
  819. wires for address port conections from WBW_FIFO control logic to RAM blocks used for WBW_FIFO
  820. -----------------------------------------------------------------------------------------------------------*/
  821. wire [(WBW_ADDR_LENGTH - 1):0] wbw_raddr ;
  822. wire [(WBW_ADDR_LENGTH - 1):0] wbw_waddr ;
  824. /*-----------------------------------------------------------------------------------------------------------
  825. wires for address port conections from WBR_FIFO control logic to RAM blocks used for WBR_FIFO
  826. -----------------------------------------------------------------------------------------------------------*/
  827. wire [(WBR_ADDR_LENGTH - 1):0] wbr_raddr ;
  828. wire [(WBR_ADDR_LENGTH - 1):0] wbr_waddr ;
  830. /*-----------------------------------------------------------------------------------------------------------
  831. WBW_FIFO transaction counters: used to count incoming transactions and outgoing transactions. When number of
  832. input transactions is equal to number of output transactions, it means that there isn't any complete transaction
  833. currently present in the FIFO.
  834. -----------------------------------------------------------------------------------------------------------*/
  835. reg [(WBW_ADDR_LENGTH - 2):0] wbw_inTransactionCount ;
  836. reg [(WBW_ADDR_LENGTH - 2):0] wbw_outTransactionCount ;
  838. /*-----------------------------------------------------------------------------------------------------------
  839. wires monitoring control bus. When control bus on a write transaction has a value of `LAST, it means that
  840. complete transaction is in the FIFO. When control bus on a read transaction has a value of `LAST,
  841. it means that there was one complete transaction taken out of FIFO.
  842. -----------------------------------------------------------------------------------------------------------*/
  843. wire wbw_last_in  = wbw_control_in[`LAST_CTRL_BIT]  ;
  844. wire wbw_last_out = wbw_control_out[`LAST_CTRL_BIT] ;
  846. wire wbw_empty ;
  847. wire wbr_empty ;
  849. assign wbw_empty_out = wbw_empty ;
  850. assign wbr_empty_out = wbr_empty ;
  852. // clear wires for fifos
  853. wire wbw_clear = reset_in /*|| wbw_flush_in*/ ; // WBW_FIFO clear flush not used
  854. wire wbr_clear = reset_in /*|| wbr_flush_in*/ ; // WBR_FIFO clear - flush changed from asynchronous to synchronous
  856. /*-----------------------------------------------------------------------------------------------------------
  857. Definitions of wires for connecting RAM instances
  858. -----------------------------------------------------------------------------------------------------------*/
  859. wire [39:0] dpram_portA_output ;
  860. wire [39:0] dpram_portB_output ;
  862. wire [39:0] dpram_portA_input = {wbw_control_in, wbw_cbe_in, wbw_addr_data_in} ;
  863. wire [39:0] dpram_portB_input = {wbr_control_in, wbr_be_in, wbr_data_in} ;
  865. /*-----------------------------------------------------------------------------------------------------------
  866. Fifo output assignments - each ram port provides data for different fifo
  867. -----------------------------------------------------------------------------------------------------------*/
  868. assign wbw_control_out = dpram_portB_output[39:36] ;
  869. assign wbr_control_out = dpram_portA_output[39:36] ;
  871. assign wbw_cbe_out     = dpram_portB_output[35:32] ;
  872. assign wbr_be_out      = dpram_portA_output[35:32] ;
  874. assign wbw_addr_data_out = dpram_portB_output[31:0] ;
  875. assign wbr_data_out      = dpram_portA_output[31:0] ;
  877. `ifdef WB_RAM_DONT_SHARE
  879.     /*-----------------------------------------------------------------------------------------------------------
  880.     Piece of code in this ifdef section is used in applications which can provide enough RAM instances to
  881.     accomodate four fifos - each occupying its own instance of ram. Ports are connected in such a way,
  882.     that instances of RAMs can be changed from two port to dual port ( async read/write port ). In that case,
  883.     write port is always port a and read port is port b.
  884.     -----------------------------------------------------------------------------------------------------------*/
  886.     /*-----------------------------------------------------------------------------------------------------------
  887.     Pad redundant address lines with zeros. This may seem stupid, but it comes in perfect for FPGA impl.
  888.     -----------------------------------------------------------------------------------------------------------*/
  889.     /*
  890.     wire [(`WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WBW_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
  891.     wire [(`WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WBR_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b0}} ;
  892.     */
  894.     // compose complete port addresses
  895.     wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_waddr = wbw_waddr ;
  896.     wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbw_whole_raddr = wbw_raddr ;
  898.     wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_waddr = wbr_waddr ;
  899.     wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] wbr_whole_raddr = wbr_raddr ;
  901.     wire wbw_read_enable = 1'b1 ;
  902.     wire wbr_read_enable = 1'b1 ;
  904.     `ifdef PCI_BIST
  905.     wire mbist_so_o_internal ; // wires for connection of debug ports on two rams
  906.     wire mbist_si_i_internal = mbist_so_o_internal ;
  907.     `endif
  909.     // instantiate and connect two generic rams - one for wishbone write fifo and one for wishbone read fifo
  910.     pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbw_fifo_storage
  911.     (
  912.         /////////////////Generic synchronous two-port RAM interface
  913.         .clk_a(wb_clock_in),
  914.         .rst_a(reset_in),
  915.         .ce_a(1'b1),
  916.         .we_a(wbw_wallow),
  917.         .oe_a(1'b1),
  918.         .addr_a(wbw_whole_waddr),
  919.         .di_a(dpram_portA_input),
  920.         .do_a(),
  922.         .clk_b(pci_clock_in),
  923.         .rst_b(reset_in),
  924.         .ce_b(wbw_read_enable),
  925.         .we_b(1'b0),
  926.         .oe_b(1'b1),
  927.         .addr_b(wbw_whole_raddr),
  928.         .di_b(40'h00_0000_0000),
  929.         .do_b(dpram_portB_output)
  931.     `ifdef PCI_BIST
  932.         ,
  933.         .mbist_si_i       (mbist_si_i),
  934.         .mbist_so_o       (mbist_so_o_internal),
  935.         .mbist_ctrl_i       (mbist_ctrl_i)
  936.     `endif
  937.     );
  938.  
  939.     pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbr_fifo_storage
  940.     (
  941.         // Generic synchronous two-port RAM interface
  942.         .clk_a(pci_clock_in),
  943.         .rst_a(reset_in),
  944.         .ce_a(1'b1),
  945.         .we_a(wbr_wallow),
  946.         .oe_a(1'b1),
  947.         .addr_a(wbr_whole_waddr),
  948.         .di_a(dpram_portB_input),
  949.         .do_a(),
  951.         .clk_b(wb_clock_in),
  952.         .rst_b(reset_in),
  953.         .ce_b(wbr_read_enable),
  954.         .we_b(1'b0),
  955.         .oe_b(1'b1),
  956.         .addr_b(wbr_whole_raddr),
  957.         .di_b(40'h00_0000_0000),
  958.         .do_b(dpram_portA_output)
  960.     `ifdef PCI_BIST
  961.         ,
  962.         .mbist_si_i       (mbist_si_i_internal),
  963.         .mbist_so_o       (mbist_so_o),
  964.         .mbist_ctrl_i       (mbist_ctrl_i)
  965.     `endif
  966.     );
  969. `else // RAM blocks sharing between two fifos
  971.     /*-----------------------------------------------------------------------------------------------------------
  972.     Code section under this ifdef is used for implementation where RAM instances are too expensive. In this
  973.     case one RAM instance is used for both - WISHBONE read and WISHBONE write fifo.
  974.     -----------------------------------------------------------------------------------------------------------*/
  975.     /*-----------------------------------------------------------------------------------------------------------
  976.     Address prefix definition - since both FIFOs reside in same RAM instance, storage is separated by MSB
  977.     addresses. WISHBONE write fifo addresses are padded with zeros on the MSB side ( at least one address line
  978.     must be used for this ), WISHBONE read fifo addresses are padded with ones on the right ( at least one ).
  979.     -----------------------------------------------------------------------------------------------------------*/
  980.     wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH - 1):0] wbw_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBW_ADDR_LENGTH){1'b0}} ;
  981.     wire [(`WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH - 1):0] wbr_addr_prefix = {( `WB_FIFO_RAM_ADDR_LENGTH - WBR_ADDR_LENGTH){1'b1}} ;
  983.     /*-----------------------------------------------------------------------------------------------------------
  984.     Port A address generation for RAM instance. RAM instance must be full two port RAM - read and write capability
  985.     on both sides.
  986.     Port A is clocked by WISHBONE clock, DIA is input for wbw_fifo, DOA is output for wbr_fifo.
  987.     Address is multiplexed so operation can be switched between fifos. Default is a read on port.
  988.     -----------------------------------------------------------------------------------------------------------*/
  989.     wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portA_addr = wbw_wallow ? {wbw_addr_prefix, wbw_waddr} : {wbr_addr_prefix, wbr_raddr} ;
  991.     /*-----------------------------------------------------------------------------------------------------------
  992.     Port B is clocked by PCI clock, DIB is input for wbr_fifo, DOB is output for wbw_fifo.
  993.     Address is multiplexed so operation can be switched between fifos. Default is a read on port.
  994.     -----------------------------------------------------------------------------------------------------------*/
  995.     wire [(`WB_FIFO_RAM_ADDR_LENGTH-1):0] portB_addr  = wbr_wallow ? {wbr_addr_prefix, wbr_waddr} : {wbw_addr_prefix, wbw_raddr} ;
  997.     wire portA_enable      = 1'b1 ;
  999.     wire portB_enable      = 1'b1 ;
  1001.     // instantiate RAM for these two fifos
  1002.     pci_wb_tpram #(`WB_FIFO_RAM_ADDR_LENGTH, 40) wbu_fifo_storage
  1003.     (
  1004.         // Generic synchronous two-port RAM interface
  1005.         .clk_a(wb_clock_in),
  1006.         .rst_a(reset_in),
  1007.         .ce_a(portA_enable),
  1008.         .we_a(wbw_wallow),
  1009.         .oe_a(1'b1),
  1010.         .addr_a(portA_addr),
  1011.         .di_a(dpram_portA_input),
  1012.         .do_a(dpram_portA_output),
  1013.         .clk_b(pci_clock_in),
  1014.         .rst_b(reset_in),
  1015.         .ce_b(portB_enable),
  1016.         .we_b(wbr_wallow),
  1017.         .oe_b(1'b1),
  1018.         .addr_b(portB_addr),
  1019.         .di_b(dpram_portB_input),
  1020.         .do_b(dpram_portB_output)
  1022.     `ifdef PCI_BIST
  1023.         ,
  1024.         .mbist_si_i       (mbist_si_i),
  1025.         .mbist_so_o       (mbist_so_o),
  1026.         .mbist_ctrl_i       (mbist_ctrl_i)
  1027.     `endif
  1028.     );
  1030. `endif
  1033. /*-----------------------------------------------------------------------------------------------------------
  1034. Instantiation of two control logic modules - one for WBW_FIFO and one for WBR_FIFO
  1035. -----------------------------------------------------------------------------------------------------------*/
  1036. pci_wbw_fifo_control #(WBW_ADDR_LENGTH) wbw_fifo_ctrl
  1037. (
  1038.     .rclock_in(pci_clock_in),
  1039.     .wclock_in(wb_clock_in),
  1040.     .renable_in(wbw_renable_in),
  1041.     .wenable_in(wbw_wenable_in),
  1042.     .reset_in(reset_in),
  1043. //////////////////////////////    .flush_in(wbw_flush_in),
  1044.     .almost_full_out(wbw_almost_full_out),
  1045.     .full_out(wbw_full_out),
  1046.     .empty_out(wbw_empty),
  1047.     .waddr_out(wbw_waddr),
  1048.     .raddr_out(wbw_raddr),
  1049.     .rallow_out(wbw_rallow),
  1050.     .wallow_out(wbw_wallow),
  1051. .half_full_out(wbw_half_full_out) ////Robert, burst issue
  1052. );
  1054. pci_wbr_fifo_control #(WBR_ADDR_LENGTH) wbr_fifo_ctrl
  1055. (   .rclock_in(wb_clock_in),
  1056.     .wclock_in(pci_clock_in),
  1057.     .renable_in(wbr_renable_in),
  1058.     .wenable_in(wbr_wenable_in),
  1059.     .reset_in(reset_in),
  1060.     .flush_in(wbr_flush_in),
  1061.     .empty_out(wbr_empty),
  1062.     .waddr_out(wbr_waddr),
  1063.     .raddr_out(wbr_raddr),
  1064.     .rallow_out(wbr_rallow),
  1065.     .wallow_out(wbr_wallow)
  1066. );
  1069. // in and out transaction counters and grey codes
  1070. reg  [(WBW_ADDR_LENGTH-2):0] inGreyCount ;
  1071. reg  [(WBW_ADDR_LENGTH-2):0] outGreyCount ;
  1072. wire [(WBW_ADDR_LENGTH-2):0] inNextGreyCount = {wbw_inTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_inTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_inTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
  1073. wire [(WBW_ADDR_LENGTH-2):0] outNextGreyCount = {wbw_outTransactionCount[(WBW_ADDR_LENGTH-2)], wbw_outTransactionCount[(WBW_ADDR_LENGTH-2):1] ^ wbw_outTransactionCount[(WBW_ADDR_LENGTH-3):0]} ;
  1075. // input transaction counter increment - when last data of transaction is written to fifo
  1076. wire in_count_en  = wbw_wallow &amp;&amp; wbw_last_in ;
  1078. // output transaction counter increment - when last data is on top of fifo and read from it
  1079. wire out_count_en = wbw_renable_in &amp;&amp; wbw_last_out ;
  1081. // register holding grey coded count of incoming transactions
  1082. always@(posedge wb_clock_in or posedge wbw_clear)
  1083. begin
  1084.     if (wbw_clear)
  1085.     begin
  1086.         inGreyCount &lt;= #3 0 ;
  1087.     end
  1088.     else
  1089.     if (in_count_en)
  1090.         inGreyCount &lt;= #3 inNextGreyCount ;
  1091. end
  1093. wire [(WBW_ADDR_LENGTH-2):0] pci_clk_sync_inGreyCount ;
  1094. reg  [(WBW_ADDR_LENGTH-2):0] pci_clk_inGreyCount ;
  1095. pci_synchronizer_flop #((WBW_ADDR_LENGTH - 1), 0) i_synchronizer_reg_inGreyCount
  1096. (
  1097.     .data_in        (inGreyCount),
  1098.     .clk_out        (pci_clock_in),
  1099.     .sync_data_out  (pci_clk_sync_inGreyCount),
  1100.     .async_reset    (wbw_clear)
  1101. ) ;
  1103. always@(posedge pci_clock_in or posedge wbw_clear)
  1104. begin
  1105.     if (wbw_clear)
  1106.         pci_clk_inGreyCount &lt;= #`FF_DELAY 0 ;
  1107.     else
  1108.         pci_clk_inGreyCount &lt;= # `FF_DELAY pci_clk_sync_inGreyCount ;
  1109. end
  1111. // register holding grey coded count of outgoing transactions
  1112. always@(posedge pci_clock_in or posedge wbw_clear)
  1113. begin
  1114.     if (wbw_clear)
  1115.     begin
  1116.         outGreyCount &lt;= #`FF_DELAY 0 ;
  1117.     end
  1118.     else
  1119.     if (out_count_en)
  1120.         outGreyCount &lt;= #`FF_DELAY outNextGreyCount ;
  1121. end
  1123. // incoming transactions counter
  1124. always@(posedge wb_clock_in or posedge wbw_clear)
  1125. begin
  1126.     if (wbw_clear)
  1127.         wbw_inTransactionCount &lt;= #`FF_DELAY 1 ;
  1128.     else
  1129.     if (in_count_en)
  1130.         wbw_inTransactionCount &lt;= #`FF_DELAY wbw_inTransactionCount + 1'b1 ;
  1131. end
  1133. // outgoing transactions counter
  1134. always@(posedge pci_clock_in or posedge wbw_clear)
  1135. begin
  1136.     if (wbw_clear)
  1137.         wbw_outTransactionCount &lt;= 1 ;
  1138.     else
  1139.     if (out_count_en)
  1140.         wbw_outTransactionCount &lt;= #`FF_DELAY wbw_outTransactionCount + 1'b1 ;
  1141. end
  1143. assign wbw_transaction_ready_out = pci_clk_inGreyCount != outGreyCount ;
  1145. endmodule
  1147. </pre>
  1148. <hr />
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