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pci_async_reset_flop(1).v
资源名称：pci_core_verilog.rar　[点击查看]
上传用户：quan1896
上传日期：2014-05-14
资源大小：211k
文件大小：26k
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pci_async_reset_flop(1).v：源码内容
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  516. <a href="./pci_async_reset_flop.v#rev1.1"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_async_reset_flop.v#rev1.1">pci_async_reset_flop.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td>  <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td>
  517.  </tr>
  518. </table>
  519. <hr />
  520. <div class="log-markup">
  521. File:&nbsp;
  522.  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_async_reset_flop.v">pci_async_reset_flop.v</a><br />
  523. <a name="rev1.1"></a><a name="wb2hpi"></a><a name="rel_WB_B3"></a><a name="rel_9"></a><a name="rel_8"></a><a name="rel_7"></a><a name="rel_6"></a><a name="rel_5"></a><a name="rel_4"></a><a name="rel_13"></a><a name="rel_12"></a><a name="rel_11"></a><a name="rel_10"></a><a name="asyst_3"></a><a name="asyst_2"></a><a name="HEAD"></a>
  524.  Revision <b>1.1</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_async_reset_flop.v?rev=1.1;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_async_reset_flop.v?rev=1.1;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_async_reset_flop.v?annotate=1.1">annotated</a> - <a href="pci_async_reset_flop.v?r1=1.1#rev1.1">select&nbsp;for&nbsp;diffs</a><br />
  525. <i>Mon Jan 27 16:49:31 2003 UTC</i> (4 years, 3 months ago) by <i>mihad</i><br />
  526. Branches: <a href="./pci_async_reset_flop.v?only_with_tag=MAIN">MAIN</a><br />
  527. CVS tags: <a href="./pci_async_reset_flop.v?only_with_tag=wb2hpi">wb2hpi</a>,
  528. <a href="./pci_async_reset_flop.v?only_with_tag=rel_WB_B3">rel_WB_B3</a>,
  529. <a href="./pci_async_reset_flop.v?only_with_tag=rel_9">rel_9</a>,
  530. <a href="./pci_async_reset_flop.v?only_with_tag=rel_8">rel_8</a>,
  531. <a href="./pci_async_reset_flop.v?only_with_tag=rel_7">rel_7</a>,
  532. <a href="./pci_async_reset_flop.v?only_with_tag=rel_6">rel_6</a>,
  533. <a href="./pci_async_reset_flop.v?only_with_tag=rel_5">rel_5</a>,
  534. <a href="./pci_async_reset_flop.v?only_with_tag=rel_4">rel_4</a>,
  535. <a href="./pci_async_reset_flop.v?only_with_tag=rel_13">rel_13</a>,
  536. <a href="./pci_async_reset_flop.v?only_with_tag=rel_12">rel_12</a>,
  537. <a href="./pci_async_reset_flop.v?only_with_tag=rel_11">rel_11</a>,
  538. <a href="./pci_async_reset_flop.v?only_with_tag=rel_10">rel_10</a>,
  539. <a href="./pci_async_reset_flop.v?only_with_tag=asyst_3">asyst_3</a>,
  540. <a href="./pci_async_reset_flop.v?only_with_tag=asyst_2">asyst_2</a>,
  541. <a href="./pci_async_reset_flop.v?only_with_tag=HEAD">HEAD</a><br />
  542. <pre class="log">
  543. Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  544. </pre>
  545. </div>
  546. <hr /><pre>
  547. //===========================================================================
  548. // $Id: pci_async_reset_flop.v,v 1.1 2003/01/27 16:49:31 mihad Exp $
  549. //
  550. //////////////////////////////////////////////////////////////////////
  551. ////                                                              ////
  552. //// async_reset_flop                                             ////
  553. ////                                                              ////
  554. //// This file is part of the general opencores effort.           ////
  555. //// &lt;http://www.opencores.org/cores/misc/&gt;                       ////
  556. ////                                                              ////
  557. //// Module Description:                                          ////
  558. ////                                                              ////
  559. //// Make a rising-edge triggered flop with async reset with a    ////
  560. ////   distinguished name so that it's output can be easily       ////
  561. ////   traced, because it is used for asynchronous reset of some  ////
  562. ////   flip-flops.                                                ////
  563. ////                                                              ////
  564. //// This flop should be used instead of a regular flop for ALL   ////
  565. ////   asynchronous-reset generator flops.                        ////
  566. ////                                                              ////
  567. //// To Do:                                                       ////
  568. //// Nothing                                                      ////
  569. ////                                                              ////
  570. //// Author(s):                                                   ////
  571. ////      - Tadej Markovic, tadej@opencores.org                   ////
  572. ////                                                              ////
  573. //////////////////////////////////////////////////////////////////////
  574. ////                                                              ////
  575. //// Copyright (C) 2001 Authors and OPENCORES.ORG                 ////
  576. ////                                                              ////
  577. //// This source file may be used and distributed without         ////
  578. //// restriction provided that this copyright statement is not    ////
  579. //// removed from the file and that any derivative work contains  ////
  580. //// the original copyright notice and the associated disclaimer. ////
  581. ////                                                              ////
  582. //// This source file is free software; you can redistribute it   ////
  583. //// and/or modify it under the terms of the GNU Lesser General   ////
  584. //// Public License as published by the Free Software Foundation; ////
  585. //// either version 2.1 of the License, or (at your option) any   ////
  586. //// later version.                                               ////
  587. ////                                                              ////
  588. //// This source is distributed in the hope that it will be       ////
  589. //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  590. //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  591. //// PURPOSE. See the GNU Lesser General Public License for more  ////
  592. //// details.                                                     ////
  593. ////                                                              ////
  594. //// You should have received a copy of the GNU Lesser General    ////
  595. //// Public License along with this source; if not, download it   ////
  596. //// from &lt;http://www.opencores.org/lgpl.shtml&gt;                   ////
  597. ////                                                              ////
  598. //////////////////////////////////////////////////////////////////////
  599. //
  600. // CVS Revision History
  601. //
  602. // $Log: pci_async_reset_flop.v,v $
  603. // Revision 1.1  2003/01/27 16:49:31  mihad
  604. // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  605. //
  606. // Revision 1.3  2002/08/14 16:44:19  mihad
  607. // Include statement was enclosed in synosys translate off/on directive - repaired
  608. //
  609. // Revision 1.2  2002/02/25 15:15:43  mihad
  610. // Added include statement that was missing and causing errors
  611. //
  612. // Revision 1.1  2002/02/01 14:43:31  mihad
  613. // *** empty log message ***
  614. //
  615. // 
  616. //
  618. // synopsys translate_off
  619. `include &quot;timescale.v&quot;
  620. // synopsys translate_on
  622. `include &quot;pci_constants.v&quot;
  624. module pci_async_reset_flop (
  625.   data_in, clk_in, async_reset_data_out, reset_in
  626. );
  628. input      data_in;
  629. input      clk_in;
  630. output     async_reset_data_out;
  631. input      reset_in;
  633. reg        async_reset_data_out;
  635. always @(posedge clk_in or posedge reset_in)
  636. begin
  637.   if (reset_in)
  638.   begin
  639.     async_reset_data_out &lt;= #`FF_DELAY 1'b0;
  640.   end
  641.   else
  642.   begin
  643.     async_reset_data_out &lt;= #`FF_DELAY data_in;
  644.   end
  645. end
  647. endmodule
  649. </pre>
  650. <hr />
  651. <address><span style="font-size: smaller">FreeBSD-CVSweb &lt;<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>&gt;</span></address>
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