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pci_constants(1).v
资源名称：pci_core_verilog.rar　[点击查看]
上传用户：quan1896
上传日期：2014-05-14
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文件大小：29k
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并行计算

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pci_constants(1).v：源码内容
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  516. <a href="./pci_constants.v#rev1.2"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_constants.v#rev1.2">pci_constants.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td>  <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td>
  517.  </tr>
  518. </table>
  519. <hr />
  520. <div class="log-markup">
  521. File:&nbsp;
  522.  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_constants.v">pci_constants.v</a><br />
  523. <a name="rev1.2"></a><a name="wb2hpi"></a><a name="rel_13"></a><a name="asyst_3"></a><a name="asyst_2"></a><a name="HEAD"></a><a name="MAIN"></a>
  524.  Revision <b>1.2</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_constants.v?rev=1.2;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_constants.v?rev=1.2;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_constants.v?annotate=1.2">annotated</a> - <a href="pci_constants.v?r1=1.2#rev1.2">select&nbsp;for&nbsp;diffs</a><br />
  525. <i>Fri Dec 19 11:11:30 2003 UTC</i> (3 years, 4 months ago) by <i>mihad</i><br />
  526. Branches: <a href="./pci_constants.v?only_with_tag=MAIN">MAIN</a><br />
  527. CVS tags: <a href="./pci_constants.v?only_with_tag=wb2hpi">wb2hpi</a>,
  528. <a href="./pci_constants.v?only_with_tag=rel_13">rel_13</a>,
  529. <a href="./pci_constants.v?only_with_tag=asyst_3">asyst_3</a>,
  530. <a href="./pci_constants.v?only_with_tag=asyst_2">asyst_2</a>,
  531. <a href="./pci_constants.v?only_with_tag=HEAD">HEAD</a><br />
  532. <pre class="log">
  533. Compact PCI Hot Swap support added.
  534. New testcases added.
  535. Specification updated.
  536. Test application changed to support WB B3 cycles.
  537. </pre>
  538. </div>
  539. <hr /><pre>
  540. //////////////////////////////////////////////////////////////////////
  541. ////                                                              ////
  542. ////  File name &quot;pci_constants.v&quot;                                 ////
  543. ////                                                              ////
  544. ////  This file is part of the &quot;PCI bridge&quot; project               ////
  545. ////  http://www.opencores.org/cores/pci/                         ////
  546. ////                                                              ////
  547. ////  Author(s):                                                  ////
  548. ////      - Miha Dolenc (mihad@opencores.org)                     ////
  549. ////      - Tadej Markovic (tadej@opencores.org)                  ////
  550. ////                                                              ////
  551. ////  All additional information is avaliable in the README.txt   ////
  552. ////  file.                                                       ////
  553. ////                                                              ////
  554. ////                                                              ////
  555. //////////////////////////////////////////////////////////////////////
  556. ////                                                              ////
  557. //// Copyright (C) 2000 Miha Dolenc, mihad@opencores.org          ////
  558. ////                                                              ////
  559. //// This source file may be used and distributed without         ////
  560. //// restriction provided that this copyright statement is not    ////
  561. //// removed from the file and that any derivative work contains  ////
  562. //// the original copyright notice and the associated disclaimer. ////
  563. ////                                                              ////
  564. //// This source file is free software; you can redistribute it   ////
  565. //// and/or modify it under the terms of the GNU Lesser General   ////
  566. //// Public License as published by the Free Software Foundation; ////
  567. //// either version 2.1 of the License, or (at your option) any   ////
  568. //// later version.                                               ////
  569. ////                                                              ////
  570. //// This source is distributed in the hope that it will be       ////
  571. //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  572. //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  573. //// PURPOSE.  See the GNU Lesser General Public License for more ////
  574. //// details.                                                     ////
  575. ////                                                              ////
  576. //// You should have received a copy of the GNU Lesser General    ////
  577. //// Public License along with this source; if not, download it   ////
  578. //// from http://www.opencores.org/lgpl.shtml                     ////
  579. ////                                                              ////
  580. //////////////////////////////////////////////////////////////////////
  581. //
  582. // CVS Revision History
  583. //
  584. // $Log: pci_constants.v,v $
  585. // Revision 1.2  2003/12/19 11:11:30  mihad
  586. // Compact PCI Hot Swap support added.
  587. // New testcases added.
  588. // Specification updated.
  589. // Test application changed to support WB B3 cycles.
  590. //
  591. // Revision 1.1  2002/02/01 14:43:31  mihad
  592. // *** empty log message ***
  593. //
  594. // Revision 1.2  2001/10/05 08:14:28  mihad
  595. // Updated all files with inclusion of timescale file for simulation purposes.
  596. //
  597. // Revision 1.1.1.1  2001/10/02 15:33:46  mihad
  598. // New project directory structure
  599. //
  601. // first include user definable parameters
  602. `ifdef REGRESSION // Used only for regression testing purposes!!!
  603. `include &quot;pci_regression_constants.v&quot;
  604. `else
  605. `include &quot;pci_user_constants.v&quot;
  606. `endif
  608. ////////////////////////////////////////////////////////////////////////
  609. ////                                                                ////
  610. //// FIFO parameters define behaviour of FIFO control logic and     ////
  611. //// FIFO depths.                                                   ////
  612. ////                                                                ////
  613. ////////////////////////////////////////////////////////////////////////
  614. `define WBW_DEPTH (1 &lt;&lt; `WBW_ADDR_LENGTH)
  615. `define WBR_DEPTH (1 &lt;&lt; `WBR_ADDR_LENGTH)
  616. `define PCIW_DEPTH (1 &lt;&lt; `PCIW_ADDR_LENGTH)
  617. `define PCIR_DEPTH (1 &lt;&lt; `PCIR_ADDR_LENGTH)
  619. // defines on which bit in control bus means what
  620. `define ADDR_CTRL_BIT 3
  621. `define LAST_CTRL_BIT 0
  622. `define DATA_ERROR_CTRL_BIT 1
  623. `define UNUSED_CTRL_BIT 2
  624. `define BURST_BIT 2
  626. // MAX Retry counter value for PCI Master state-machine
  627. //  This value is 8-bit because of 8-bit retry counter !!!
  628. //`define PCI_RTY_CNT_MAX 8'h08
  630. // Value of address mask for WB configuration image. This has to be defined always, since it is a value, that is not changable in runtime.
  631. // !!!!!!!!!!!!!!!!!!!!!!!If this is not defined, WB configuration access will not be possible!!!!!!!!!!!!!!!!!!!!!1
  632. `define WB_AM0 20'hffff_f
  634. // PCI target &amp; WB slave ADDRESS names for configuration space !!!
  635. // This does not include address offsets of PCI Header registers - they starts at offset 0 (see PCI spec.)
  636. //   ALL VALUES are without 2 LSBits AND there is required that address bit [8] is set while
  637. //   accessing this registers, otherwise the configuration header will be accessed !!!
  638. `define PCI_CAP_PTR_VAL         8'h80
  639. `define P_IMG_CTRL0_ADDR 6'h00 // Address offset = h 100
  640. `define P_BA0_ADDR 6'h01 // Address offset = h 104
  641. `define P_AM0_ADDR 6'h02   // Address offset = h 108
  642. `define P_TA0_ADDR 6'h03   // Address offset = h 10c
  643. `define P_IMG_CTRL1_ADDR        6'h04   // Address offset = h 110
  644. `define P_BA1_ADDR 6'h05   // Address offset = h 114
  645. `define P_AM1_ADDR 6'h06   // Address offset = h 118
  646. `define P_TA1_ADDR 6'h07   // Address offset = h 11c
  647. `define P_IMG_CTRL2_ADDR 6'h08   // Address offset = h 120
  648. `define P_BA2_ADDR 6'h09   // Address offset = h 124
  649. `define P_AM2_ADDR 6'h0a   // Address offset = h 128
  650. `define P_TA2_ADDR 6'h0b   // Address offset = h 12c
  651. `define P_IMG_CTRL3_ADDR 6'h0c   // Address offset = h 130
  652. `define P_BA3_ADDR 6'h0d   // Address offset = h 134
  653. `define P_AM3_ADDR 6'h0e   // Address offset = h 138
  654. `define P_TA3_ADDR 6'h0f   // Address offset = h 13c
  655. `define P_IMG_CTRL4_ADDR 6'h10   // Address offset = h 140
  656. `define P_BA4_ADDR 6'h11   // Address offset = h 144
  657. `define P_AM4_ADDR 6'h12   // Address offset = h 148
  658. `define P_TA4_ADDR 6'h13   // Address offset = h 14c
  659. `define P_IMG_CTRL5_ADDR 6'h14   // Address offset = h 150
  660. `define P_BA5_ADDR 6'h15   // Address offset = h 154
  661. `define P_AM5_ADDR 6'h16   // Address offset = h 158
  662. `define P_TA5_ADDR 6'h17   // Address offset = h 15c
  663. `define P_ERR_CS_ADDR 6'h18   // Address offset = h 160
  664. `define P_ERR_ADDR_ADDR 6'h19   // Address offset = h 164
  665. `define P_ERR_DATA_ADDR 6'h1a   // Address offset = h 168
  667. `define WB_CONF_SPC_BAR_ADDR 6'h20 // Address offset = h 180
  668. `define W_IMG_CTRL1_ADDR 6'h21   // Address offset = h 184
  669. `define W_BA1_ADDR 6'h22   // Address offset = h 188
  670. `define W_AM1_ADDR 6'h23   // Address offset = h 18c
  671. `define W_TA1_ADDR 6'h24   // Address offset = h 190
  672. `define W_IMG_CTRL2_ADDR 6'h25   // Address offset = h 194
  673. `define W_BA2_ADDR 6'h26   // Address offset = h 198
  674. `define W_AM2_ADDR 6'h27   // Address offset = h 19c
  675. `define W_TA2_ADDR 6'h28   // Address offset = h 1a0
  676. `define W_IMG_CTRL3_ADDR 6'h29   // Address offset = h 1a4
  677. `define W_BA3_ADDR 6'h2a   // Address offset = h 1a8
  678. `define W_AM3_ADDR 6'h2b   // Address offset = h 1ac
  679. `define W_TA3_ADDR 6'h2c   // Address offset = h 1b0
  680. `define W_IMG_CTRL4_ADDR 6'h2d   // Address offset = h 1b4
  681. `define W_BA4_ADDR 6'h2e   // Address offset = h 1b8
  682. `define W_AM4_ADDR 6'h2f   // Address offset = h 1bc
  683. `define W_TA4_ADDR 6'h30   // Address offset = h 1c0
  684. `define W_IMG_CTRL5_ADDR 6'h31   // Address offset = h 1c4
  685. `define W_BA5_ADDR 6'h32   // Address offset = h 1c8
  686. `define W_AM5_ADDR 6'h33   // Address offset = h 1cc
  687. `define W_TA5_ADDR 6'h34   // Address offset = h 1d0
  688. `define W_ERR_CS_ADDR 6'h35   // Address offset = h 1d4
  689. `define W_ERR_ADDR_ADDR 6'h36   // Address offset = h 1d8
  690. `define W_ERR_DATA_ADDR 6'h37   // Address offset = h 1dc
  691. `define CNF_ADDR_ADDR 6'h38   // Address offset = h 1e0
  692. // Following two registers are not implemented in a configuration space but in a WishBone unit!
  693. `define CNF_DATA_ADDR 6'h39 // Address offset = h 1e4
  694. `define INT_ACK_ADDR 6'h3a   // Address offset = h 1e8
  695. // -------------------------------------
  696. `define ICR_ADDR 6'h3b   // Address offset = h 1ec
  697. `define ISR_ADDR         6'h3c   // Address offset = h 1f0
  699. `ifdef PCI33
  700.     `define HEADER_66MHz        1'b0
  701. `else
  702. `ifdef PCI66
  703.     `define HEADER_66MHz        1'b1
  704. `endif
  705. `endif
  707. // all flip-flops in the design have this inter-assignment delay
  708. `define FF_DELAY 1
  710. </pre>
  711. <hr />
  712. <address><span style="font-size: smaller">FreeBSD-CVSweb &lt;<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>&gt;</span></address>
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