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pci_conf_cyc_addr_dec(1).v
资源名称：pci_core_verilog.rar　[点击查看]
上传用户：quan1896
上传日期：2014-05-14
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pci_conf_cyc_addr_dec(1).v：源码内容
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  516. <a href="./pci_conf_cyc_addr_dec.v#rev1.1"><img src="/icons/back.gif" alt="[BACK]" border="0" width="20" height="22" /></a><b>Return to <a href="./pci_conf_cyc_addr_dec.v#rev1.1">pci_conf_cyc_addr_dec.v</a> CVS log</b> <img src="/icons/text.gif" alt="[TXT]" border="0" width="20" height="22" /></td>  <td style="text-align: right"><img src="/icons/dir.gif" alt="[DIR]" border="0" width="20" height="22" /> <b>Up to  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a></b></td>
  517.  </tr>
  518. </table>
  519. <hr />
  520. <div class="log-markup">
  521. File:&nbsp;
  522.  <a href="/cvsweb.shtml/#dirlist">[Official OpenCores CVS Repository]</a> / <a href="/cvsweb.shtml/pci/#dirlist">pci</a> / <a href="/cvsweb.shtml/pci/rtl/#dirlist">rtl</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/#dirlist">verilog</a> / <a href="/cvsweb.shtml/pci/rtl/verilog/pci_conf_cyc_addr_dec.v">pci_conf_cyc_addr_dec.v</a><br />
  523. <a name="rev1.1"></a><a name="wb2hpi"></a><a name="rel_WB_B3"></a><a name="rel_9"></a><a name="rel_8"></a><a name="rel_7"></a><a name="rel_6"></a><a name="rel_5"></a><a name="rel_4"></a><a name="rel_13"></a><a name="rel_12"></a><a name="rel_11"></a><a name="rel_10"></a><a name="asyst_3"></a><a name="asyst_2"></a><a name="HEAD"></a><a name="MAIN"></a>
  524.  Revision <b>1.1</b>: <a href="/cvsweb.cgi/~checkout~/pci/rtl/verilog/pci_conf_cyc_addr_dec.v?rev=1.1;content-type=text%2Fplain" class="download-link">download</a> - view: <a href="pci_conf_cyc_addr_dec.v?rev=1.1;content-type=text%2Fplain" class="display-link">text</a>, <a href="pci_conf_cyc_addr_dec.v?annotate=1.1">annotated</a> - <a href="pci_conf_cyc_addr_dec.v?r1=1.1#rev1.1">select&nbsp;for&nbsp;diffs</a><br />
  525. <i>Mon Jan 27 16:49:31 2003 UTC</i> (4 years, 3 months ago) by <i>mihad</i><br />
  526. Branches: <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=MAIN">MAIN</a><br />
  527. CVS tags: <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=wb2hpi">wb2hpi</a>,
  528. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_WB_B3">rel_WB_B3</a>,
  529. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_9">rel_9</a>,
  530. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_8">rel_8</a>,
  531. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_7">rel_7</a>,
  532. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_6">rel_6</a>,
  533. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_5">rel_5</a>,
  534. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_4">rel_4</a>,
  535. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_13">rel_13</a>,
  536. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_12">rel_12</a>,
  537. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_11">rel_11</a>,
  538. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=rel_10">rel_10</a>,
  539. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=asyst_3">asyst_3</a>,
  540. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=asyst_2">asyst_2</a>,
  541. <a href="./pci_conf_cyc_addr_dec.v?only_with_tag=HEAD">HEAD</a><br />
  542. <pre class="log">
  543. Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  544. </pre>
  545. </div>
  546. <hr /><pre>
  547. //////////////////////////////////////////////////////////////////////
  548. ////                                                              ////
  549. ////  File name &quot;conf_cyc_addr_dec.v&quot;                             ////
  550. ////                                                              ////
  551. ////  This file is part of the &quot;PCI bridge&quot; project               ////
  552. ////  http://www.opencores.org/cores/pci/                         ////
  553. ////                                                              ////
  554. ////  Author(s):                                                  ////
  555. ////      - Miha Dolenc (mihad@opencores.org)                     ////
  556. ////                                                              ////
  557. ////  All additional information is avaliable in the README       ////
  558. ////  file.                                                       ////
  559. ////                                                              ////
  560. ////                                                              ////
  561. //////////////////////////////////////////////////////////////////////
  562. ////                                                              ////
  563. //// Copyright (C) 2001 Miha Dolenc, mihad@opencores.org          ////
  564. ////                                                              ////
  565. //// This source file may be used and distributed without         ////
  566. //// restriction provided that this copyright statement is not    ////
  567. //// removed from the file and that any derivative work contains  ////
  568. //// the original copyright notice and the associated disclaimer. ////
  569. ////                                                              ////
  570. //// This source file is free software; you can redistribute it   ////
  571. //// and/or modify it under the terms of the GNU Lesser General   ////
  572. //// Public License as published by the Free Software Foundation; ////
  573. //// either version 2.1 of the License, or (at your option) any   ////
  574. //// later version.                                               ////
  575. ////                                                              ////
  576. //// This source is distributed in the hope that it will be       ////
  577. //// useful, but WITHOUT ANY WARRANTY; without even the implied   ////
  578. //// warranty of MERCHANTABILITY or FITNESS FOR A PARTICULAR      ////
  579. //// PURPOSE.  See the GNU Lesser General Public License for more ////
  580. //// details.                                                     ////
  581. ////                                                              ////
  582. //// You should have received a copy of the GNU Lesser General    ////
  583. //// Public License along with this source; if not, download it   ////
  584. //// from http://www.opencores.org/lgpl.shtml                     ////
  585. ////                                                              ////
  586. //////////////////////////////////////////////////////////////////////
  587. //
  588. // CVS Revision History
  589. //
  590. // $Log: pci_conf_cyc_addr_dec.v,v $
  591. // Revision 1.1  2003/01/27 16:49:31  mihad
  592. // Changed module and file names. Updated scripts accordingly. FIFO synchronizations changed.
  593. //
  594. // Revision 1.3  2002/02/01 15:25:12  mihad
  595. // Repaired a few bugs, updated specification, added test bench files and design document
  596. //
  597. // Revision 1.2  2001/10/05 08:14:28  mihad
  598. // Updated all files with inclusion of timescale file for simulation purposes.
  599. //
  600. // Revision 1.1.1.1  2001/10/02 15:33:46  mihad
  601. // New project directory structure
  602. //
  603. //
  606. // module is a simple decoder which decodes device num field of configuration address
  607. // for type0 configuration cycles. If type 1 configuration cycle is
  608. // initiated then address goes through unchanged
  610. // synopsys translate_off
  611. `include &quot;timescale.v&quot;
  612. // synopsys translate_on
  614. module pci_conf_cyc_addr_dec
  615. (
  616.     ccyc_addr_in,
  617.     ccyc_addr_out
  618. ) ;
  620. input   [31:0]  ccyc_addr_in ;
  621. output  [31:0]  ccyc_addr_out ;
  622. reg     [31:11]  ccyc_addr_31_11 ;
  624. // lower 11 address lines are alweys going through unchanged
  625. assign ccyc_addr_out = {ccyc_addr_31_11, ccyc_addr_in[10:0]} ;
  627. // configuration cycle type indicator
  628. wire ccyc_type = ccyc_addr_in[0] ;
  630. always@(ccyc_addr_in or ccyc_type)
  631. begin
  632.     if (ccyc_type)
  633.         // type 1 cycle - address goes through unchanged
  634.         ccyc_addr_31_11 = ccyc_addr_in[31:11] ;
  635.     else
  636.     begin
  637.         // type 0 conf. cycle - decode device number field to appropriate value
  638.         case (ccyc_addr_in[15:11])
  639.             5'h00:ccyc_addr_31_11 = 21'h00_0001 ;
  640.             5'h01:ccyc_addr_31_11 = 21'h00_0002 ;
  641.             5'h02:ccyc_addr_31_11 = 21'h00_0004 ;
  642.             5'h03:ccyc_addr_31_11 = 21'h00_0008 ;
  643.             5'h04:ccyc_addr_31_11 = 21'h00_0010 ;
  644.             5'h05:ccyc_addr_31_11 = 21'h00_0020 ;
  645.             5'h06:ccyc_addr_31_11 = 21'h00_0040 ;
  646.             5'h07:ccyc_addr_31_11 = 21'h00_0080 ;
  647.             5'h08:ccyc_addr_31_11 = 21'h00_0100 ;
  648.             5'h09:ccyc_addr_31_11 = 21'h00_0200 ;
  649.             5'h0A:ccyc_addr_31_11 = 21'h00_0400 ;
  650.             5'h0B:ccyc_addr_31_11 = 21'h00_0800 ;
  651.             5'h0C:ccyc_addr_31_11 = 21'h00_1000 ;
  652.             5'h0D:ccyc_addr_31_11 = 21'h00_2000 ;
  653.             5'h0E:ccyc_addr_31_11 = 21'h00_4000 ;
  654.             5'h0F:ccyc_addr_31_11 = 21'h00_8000 ;
  655.             5'h10:ccyc_addr_31_11 = 21'h01_0000 ;
  656.             5'h11:ccyc_addr_31_11 = 21'h02_0000 ;
  657.             5'h12:ccyc_addr_31_11 = 21'h04_0000 ;
  658.             5'h13:ccyc_addr_31_11 = 21'h08_0000 ;
  659.             5'h14:ccyc_addr_31_11 = 21'h10_0000 ;
  660.             default: ccyc_addr_31_11 = 21'h00_0000 ;
  661.         endcase
  662.     end
  663. end
  665. endmodule
  666. </pre>
  667. <hr />
  668. <address><span style="font-size: smaller">FreeBSD-CVSweb &lt;<a href="mailto:freebsd-cvsweb@FreeBSD.org">freebsd-cvsweb@FreeBSD.org</a>&gt;</span></address>
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