irq.c
上传用户:jndfzc
上传日期:2014-06-02
资源大小:325k
文件大小:4k
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  1. #define __IRQ_C
  2. #include "irq.h"
  3. #include "define.h"
  4. #include "display.h"
  5. #include "P103_MMI2DSP.H"
  6. #include "maindef.h"
  7. #define  SECOND  100
  8. /*0:FIQ,1:SWIRQ,2:US0IRQ,3:US1IRQ,4:TC0IRQ,5:TC1IRQ,6:TC2IRQ,7:WDIRQ,8:PIOIRQ, 16:IRQ0,17:IRQ1,18:IRQ2 */
  9. typedef void (* FunctionPtr)();
  10. const unsigned char RegOffset[12]={0x00,0x04,0x08,0x0c,0x10,0x14,0x18,0x1c,0x20,0x40,0x44,0x48};
  11. const unsigned char SMRValue[12]={0x60,0x60,0x60,0x60,0x65,0x60,0x60,0x60,0x60,0x60,0x60,0x60};
  12. const FunctionPtr HandlerArray[12]={
  13. FIQ_Handler,SWIRQ_Handler,
  14. US0IRQ_Handler,US1IRQ_Handler,
  15. TC0IRQ_Handler,TC1IRQ_Handler,TC2IRQ_Handler,
  16. WDIRQ_Handler,PIOIRQ_Handler,
  17. IRQ0IRQ_Handler,IRQ1IRQ_Handler,IRQ2IRQ_Handler
  18. };
  19. US usT_1000ms=0;
  20. UC  ucsigned_1000ms_flag=0;
  21. UC ucsigned_60s=0;
  22. US ucsigned_60s_Count=0;
  23. extern UC time_modify_flag;
  24. void EnableIRQ(void) 
  25. {
  26.   int tmp;
  27.   __asm
  28.   {
  29.   mrs tmp,CPSR
  30.   bic tmp,tmp,#0x80
  31.   msr CPSR_c,tmp // use CPSR_c instead of CPSR for ADS1.2
  32.   }
  33. }
  34.  
  35. // enable the F bit in current CPSR
  36. void EnableFIQ(void)
  37. {
  38. int tmp;
  39. __asm
  40. {
  41. mrs tmp,CPSR
  42. bic  tmp,tmp,#0x40
  43. msr CPSR_c,tmp
  44. }
  45. }
  46. // disable the I bit in current CPSR
  47. void DisableIRQ(void)
  48. {
  49.   int tmp;
  50.   __asm
  51.   {
  52.   mrs tmp,CPSR
  53.   orr tmp,tmp,#0x80
  54.   msr CPSR_c,tmp
  55.   }
  56. }
  57. // enable the F bit in current CPSR
  58. void DisableFIQ(void)
  59. {
  60. int tmp;
  61. __asm
  62. {
  63. mrs tmp,CPSR
  64. orr  tmp,tmp,#0x40
  65. msr CPSR_c,tmp
  66. }
  67. }
  68. void Delay(unsigned int count)
  69. {
  70.   unsigned int i, j;
  71.   
  72.   for(i = 0; i < count; i++)
  73.    for(j = 0; j < 1650; j++);
  74. }
  75. void C_Undefined_Handler(void)
  76. {
  77. while(1);
  78. }
  79. void C_Prefetch_Handler(void)
  80. {
  81. while(1);
  82. }
  83. void C_Abort_Handler(void)
  84. {
  85. while(1);
  86. }
  87. void C_FIQ_Handler(void)
  88. {
  89. while(1);
  90. REG32_WRITE(AIC_EOICR,0x1);
  91. }
  92. void C_SWIRQ_Handler(void)
  93. {
  94. while(1);
  95. REG32_WRITE(AIC_EOICR,0x1);
  96. }
  97. void C_US0IRQ_Handler(void) //Sci0_Int
  98. {
  99. REG32_WRITE(AIC_EOICR,0x1);
  100. }
  101. //串口1中断
  102. void C_US1IRQ_Handler(void)
  103. {
  104. REG32_WRITE(AIC_EOICR,0x1);
  105. }
  106. void C_TC0IRQ_Handler(void)
  107. {
  108. // while(1);
  109. unsigned int i;
  110. /*中断计时*/
  111. WATCHDOG_OUT0;
  112. if(time_modify_flag==0)
  113. {
  114. usT_1000ms++;
  115. if( usT_1000ms >= 3*SECOND )   //  3秒
  116.     {  usT_1000ms=0;ucsigned_60s_Count++; 
  117. ucsigned_1000ms_flag=1; 
  118. }
  119.   if( ucsigned_60s_Count>= 100 ) /*5min*/
  120.     {
  121.      ucsigned_60s_Count=0; ucsigned_60s=1;
  122.    
  123.     }
  124. }
  125. WATCHDOG_OUT1;
  126. Updata_key(RdPortE32(PIO_PDSR));
  127. CommDspTimeUpdate();
  128. WATCHDOG_OUT0;
  129. i=REG32_READ(TC0+TCSR);
  130. REG32_WRITE(AIC_EOICR,0x1);
  131. }
  132. void C_TC1IRQ_Handler(void)
  133. {
  134. unsigned int i;
  135. i=REG32_READ(TC1+TCSR);
  136. REG32_WRITE(AIC_EOICR,0x1);
  137. }
  138. void C_TC2IRQ_Handler(void)
  139. {
  140. while(1);
  141. REG32_WRITE(AIC_EOICR,0x1);
  142. }
  143. void C_WDIRQ_Handler(void) //Watch Dog Interrupt
  144. {
  145. REG32_WRITE(AIC_EOICR,0x1);
  146. }
  147. void C_PIOIRQ_Handler(void)
  148. {
  149. while(1);
  150. REG32_WRITE(AIC_EOICR,0x1);
  151. }
  152. void C_IRQ0IRQ_Handler(void)
  153. {
  154. while(1);
  155. REG32_WRITE(AIC_EOICR,0x1);
  156. }
  157. void C_IRQ1IRQ_Handler(void)
  158. {
  159. while(1);
  160. REG32_WRITE(AIC_EOICR,0x1);
  161. }
  162. void C_IRQ2IRQ_Handler(void)
  163. {
  164. while(1);
  165. REG32_WRITE(AIC_EOICR,0x1);
  166. }
  167. //中断初始化
  168. void Interrupt_Init(void)
  169. {
  170. int i;
  171. i=REG32_READ(AIC_IPR);
  172. REG32_WRITE(AIC_EOICR,0x1);
  173. REG32_WRITE(AIC_IDCR,0xFFFFFFFF);
  174. REG32_WRITE(AIC_ICCR,0xFFFFFFFF);
  175. for(i=0;i<12;i++){
  176. REG32_WRITE(AIC_SMR0+RegOffset[i],SMRValue[i]);
  177. REG32_WRITE(AIC_SVR0+RegOffset[i],(unsigned int)(HandlerArray[i]));
  178. }
  179. }
  180. //参数为EnumInitKind类型
  181. void Interrupt_Enable(EnumIntKind IntKind)
  182. {
  183. REG32_WRITE(AIC_IECR,IntKind);
  184. }
  185. void Interrupt_Disable(EnumIntKind IntKind)
  186. {
  187. REG32_WRITE(AIC_IDCR,IntKind);
  188. }