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nand_interface.fit
资源名称：NANDflash.rar　[点击查看]
上传用户：dgrongshen
上传日期：2016-07-09
资源大小：827k
文件大小：10k
源码类别：

VHDL/FPGA/Verilog

开发平台：

VHDL

nand_interface.fit：源码内容
  1. --------------------------------------------------
  2. | Created    : XPLAOPT Version 3.45              |
  3. | DESIGN     : NAND_INTERFACE.blx                |
  4. | DEVICE     : XCR3064XL-6VQ44                   |
  5. | DATE       : Aug 03 11:03:52 2001              |
  6. --------------------------------------------------
  8. $DEVICES XCR3064XL-6VQ44 fit (1 sec)
  10. ---------------------------------------------------
  11. |          Total Device Resource Summary          |
  12. ---------------------------------------------------
  13. | RESOURCE     AVAIL.     USED     UTILIZATION    |
  14. ---------------------------------------------------
  15. | Clock Inputs     4         0         0.00%      |
  16. | Global C-Terms   4         0         0.00%      |
  17. | Func Blocks      4         3        75.00%      |
  18. | I/O Pins        32        18        56.25%      |
  19. | Macro Cells     64         9        14.07%      |
  20. | Registers       64         4         6.25%      |
  21. | PLA P-Terms    192        17         8.86%      |
  22. | PLA S-Terms     64         5         7.82%      |
  23. | Block C-Terms   32        10        31.25%      |
  24. | Fbk Nands        0         0         0.00%      |
  25. ---------------------------------------------------
  27. ---------------------------------------------------
  28. |        Function Block 1  Resource Summary       |
  29. ---------------------------------------------------
  30. | RESOURCE     AVAIL.     USED     UTILIZATION    |
  31. ---------------------------------------------------
  32. | Global Clocks    2         0         0.00%      |
  33. | Block C-Terms    8         7        87.50%      |
  34. | Fanins          38        11        28.95%      |
  35. | I/O Pins         8         7        87.50%      |
  36. | Macro Cells     16         8        50.00%      |
  37. | Registers       16         3        18.75%      |
  38. | PLA P-Terms     48        14        29.17%      |
  39. | PLA S-Terms     16         5        31.25%      |
  40. | Fbk Nands        0         0         0.00%      |
  41. ---------------------------------------------------
  43. ---------------------------------------------------
  44. |        Function Block 2  Resource Summary       |
  45. ---------------------------------------------------
  46. | RESOURCE     AVAIL.     USED     UTILIZATION    |
  47. ---------------------------------------------------
  48. | Global Clocks    2         0         0.00%      |
  49. | Block C-Terms    8         3        37.50%      |
  50. | Fanins          38         7        18.43%      |
  51. | I/O Pins         8         7        87.50%      |
  52. | Macro Cells     16         1         6.25%      |
  53. | Registers       16         1         6.25%      |
  54. | PLA P-Terms     48         3         6.25%      |
  55. | PLA S-Terms     16         0         0.00%      |
  56. | Fbk Nands        0         0         0.00%      |
  57. ---------------------------------------------------
  59. ---------------------------------------------------
  60. |        Function Block 3  Resource Summary       |
  61. ---------------------------------------------------
  62. | RESOURCE     AVAIL.     USED     UTILIZATION    |
  63. ---------------------------------------------------
  64. | Global Clocks    2         0         0.00%      |
  65. | Block C-Terms    8         0         0.00%      |
  66. | Fanins          38         0         0.00%      |
  67. | I/O Pins         8         4        50.00%      |
  68. | Macro Cells     16         0         0.00%      |
  69. | Registers       16         0         0.00%      |
  70. | PLA P-Terms     48         0         0.00%      |
  71. | PLA S-Terms     16         0         0.00%      |
  72. | Fbk Nands        0         0         0.00%      |
  73. ---------------------------------------------------
  75. ---------------------
  76. | PARTITION SUMMARY |
  77. ---------------------
  79. $FUNCTION BLOCK 1:
  80. I/O MACROCELLS
  81.  PIN LOC    | PIN,   NODE,   BURIED COM
  82. ------------+----------------------------------------------------------------
  83.  35  FB1_1  | wp_n,     -
  84.  34  FB1_2  | ready,    -
  85.  33  FB1_8  | cle,      -
  86. *32  FB1_9  |    ,   N115
  87.  31  FB1_10 | re_n,     -
  88.  30  FB1_11 | we_n,     -
  89.  28  FB1_14 | outce_n,  -
  90.  27  FB1_15 | se_n,     -
  93. $FUNCTION BLOCK 2:
  94. I/O MACROCELLS
  95.  PIN LOC    | PIN,   NODE,   BURIED COM
  96. ------------+----------------------------------------------------------------
  97.  42  FB2_1  | ale,      -
  98.  43  FB2_2  | ce_n
  99.  44  FB2_3  | port_addr[0]
  100. *1   FB2_9  |    
  101.  2   FB2_10 | port_addr[1]
  102.  3   FB2_11 | port_addr[2]
  103.  5   FB2_14 | port_addr[3]
  104.  6   FB2_15 | reset
  107. $FUNCTION BLOCK 3:
  108. I/O MACROCELLS
  109.  PIN LOC    | PIN,   NODE,   BURIED COM
  110. ------------+----------------------------------------------------------------
  111. *26  FB3_1  |    
  112.  25  FB3_2  | com_lat_n
  113.  23  FB3_4  | read_n
  114.  22  FB3_9  | ry_byn
  115.  21  FB3_10 | write_n
  116.  20  FB3_11 |    
  117.  19  FB3_12 |    
  118.  18  FB3_13 |    
  122. * Multi-function pin reserved for ISP or prohibited by the user.
  124. TOTAL PINS USED  18
  126. Signal                           Pin      Func    Slew  Power
  127. Name                             Number   Loc     Rate  Up
  128. --------------------------------------------------------------------------
  129. ale                              : 42     FB2_1   FAST  LOW 
  130. ce_n                             : 43     FB2_2             
  131. cle                              : 33     FB1_8   FAST      
  132. com_lat_n                        : 25     FB3_2             
  133. outce_n                          : 28     FB1_14  FAST  LOW 
  134. port_addr[0]                     : 44     FB2_3             
  135. port_addr[1]                     : 2      FB2_10            
  136. port_addr[2]                     : 3      FB2_11            
  137. port_addr[3]                     : 5      FB2_14            
  138. re_n                             : 31     FB1_10  FAST      
  139. read_n                           : 23     FB3_4             
  140. ready                            : 34     FB1_2   FAST      
  141. reset                            : 6      FB2_15            
  142. ry_byn                           : 22     FB3_9             
  143. se_n                             : 27     FB1_15  FAST  LOW 
  144. we_n                             : 30     FB1_11  FAST      
  145. wp_n                             : 35     FB1_1   FAST  LOW 
  146. write_n                          : 21     FB3_10            
  148. TOTAL NODES USED   1
  150. Node                             Func        Power
  151. Name                             Loc         Up
  152. --------------------------------------------------------------------------
  153. N115                             : FB1_9         
  156. ;;------------------------------------------------------------------------;;
  157. ; Implemented Equations.
  159. "********( N115 )***********************************************************
  160. "PLA 1 pts
  161. !N115        = !write_n & port_addr[2] & !ce_n & port_addr[1] 
  162.                & !port_addr[0] & !port_addr[3]; "PT0
  163. "********( ale )************************************************************
  164. "PLA 0 pts
  165. ale.D        = 0; "LUT
  166. ale.AP       = !port_addr[3] & !write_n & !port_addr[2] & !port_addr[0] 
  167.                & !ce_n & port_addr[1]; "BCT0
  168. ale.AR       = reset; "BCT1
  169. ale.LH       = !port_addr[3] & !write_n & !port_addr[2] & port_addr[0] 
  170.                & !ce_n & port_addr[1]; "BCT4
  171. "********( cle )************************************************************
  172. "PLA 1 pts
  173. cle          = !port_addr[2] & !ce_n & !port_addr[1] & port_addr[0] 
  174.                & !port_addr[3]; "PT0
  175. "********( outce_n )********************************************************
  176. "PLA 0 pts
  177. outce_n.D    = 1; "LUT
  178. outce_n.AP   = reset; "BCT1
  179. outce_n.AR   = !reset & !write_n & !port_addr[2] & !ce_n & !port_addr[1] 
  180.                & !port_addr[0] & port_addr[3]; "BCT2
  181. outce_n.LH   = !write_n & !port_addr[2] & !ce_n & !port_addr[1] 
  182.                & port_addr[0] & port_addr[3]; "BCT6
  183. "********( re_n )***********************************************************
  184. "PLA 1 pts
  185. !re_n        = !port_addr[2] & !read_n & !ce_n & !port_addr[1] 
  186.                & !port_addr[0] & !port_addr[3]; "PT0
  187. "********( ready )**********************************************************
  188. "PLA 1 pts
  189. ready        = ry_byn; "PT0
  190. ready.OE     = port_addr[2] & !read_n & !ce_n & port_addr[1] 
  191.                & port_addr[0] & port_addr[3]; "BCT0
  192. "********( se_n )***********************************************************
  193. "PLA 0 pts
  194. se_n.D       = 1; "LUT
  195. se_n.AP      = reset; "BCT1
  196. se_n.AR      = !reset & !write_n & port_addr[2] & !ce_n & !port_addr[1] 
  197.                & !port_addr[0] & !port_addr[3]; "BCT3
  198. se_n.LH      = !write_n & port_addr[2] & !ce_n & !port_addr[1] 
  199.                & port_addr[0] & !port_addr[3]; "PT1(PT37)
  200. "********( we_n )***********************************************************
  201. "PLA 2 pts
  202. !we_n        = !com_lat_n & !write_n & !port_addr[2] & !ce_n 
  203.                & !port_addr[1] & !port_addr[3]
  204.                # !write_n & !port_addr[2] & !ce_n & !port_addr[1] 
  205.                & !port_addr[0] & !port_addr[3];
  206. "********( wp_n )***********************************************************
  207. "PLA 0 pts
  208. wp_n.D       = 1; "LUT
  209. !wp_n.AR     = !reset & N115; "BCT4
  210. wp_n.LH      = !write_n & port_addr[2] & !ce_n & port_addr[1] 
  211.                & port_addr[0] & !port_addr[3]; "BCT5
  213. ****************************  Compiler Options  ****************************
  215. " XPLAOPT -dev xcr3064xl-6vq44 -mode 1 -th 28 -fi 32 -xor n -reg -fbn 0 -ucf 
  216. "         nand_interface.ucf -ncf nand_interface.ncf -it blif -i nand_interface.blx -run f -log 
  217. "         nand_interface.er3 -ot n -ctrl NAND_INTERFACE.ctrl -dev XCR3064XL-6VQ44 -bfi 38 -fbn 0 
  218. "         -pre ignore -vho time_sim.vhd -rsp 3208.rsp 
  219. Following is a list of all global compiler options used by the fitter run.
  221. Device(s) Specified                         : XCR3064XL-6VQ44
  222. Use Design Location Constraints             : IGNORE
  223. Reserve JTAG Port Pins for ISP              : ON
  224. Use Fast Input Registers                    : ON
  225. Use Foldback NANDs                          : OFF
  226. Pull Up Unused I/O Pins                     : ON
  227. Default Register Initial State              : RESET
  228. Output Slew Rate                            : FAST
  229. Optimizing Method                           : DENSITY
  230. D/T Synthesis                               : ON
  231. Xor Synthesis                               : NONE
  232. Automatic Node Collapsing                   : ON
  233. Collapsing Pterm Limit                      : 28
  234. Collapsing Input Limit                      : 32
  235. Block Input Limit                           : 38