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dsk5510_dma_aic23.c
资源名称：DSP-C6000-DM642DEMO.rar　[点击查看]
上传用户：dahaojd
上传日期：2008-01-29
资源大小：14357k
文件大小：13k
源码类别：

DSP编程

开发平台：

C/C++

dsk5510_dma_aic23.c：源码内容
  1. /*
  2.  *  Copyright 2003 by Texas Instruments Incorporated.
  3.  *  All rights reserved. Property of Texas Instruments Incorporated.
  4.  *  Restricted rights to use, duplicate or disclose this code are
  5.  *  granted through contract.
  6.  *  
  7.  */
  8. /* "@(#) DDK 1.10.00.23 07-02-03 (ddk-b12)" */
  9. /* 
  10.  *  ======== dsk5510_dma_aic23.c ========
  11.  * 
  12.  *  DMA interrupt-driven low-level streaming device driver for TI
  13.  *  5510 DSK. Uses the C55x Chip Support Library. 
  14.  *
  15.  *  DSP/BIOS configuration:
  16.  *     DMA channel 4 RX ISR plugged to DSK5510_DMA_AIC23_isr with arg = 0
  17.  *     DMA channel 5 TX ISR plugged to DSK5510_DMA_AIC23_isr with arg = 1
  18.  */
  20. #include <std.h>
  22. #include <csl.h>
  23. #include <csl_dma.h>
  24. #include <csl_mcbsp.h>
  26. #include <iom.h>
  28. #include <c55xx_dma_mcbsp.h>
  29. #include <dsk5510_dma_aic23.h>
  30. #include <aic23.h>
  32. /*
  33.  * Forward declaration of IOM interface functions.
  34.  */
  35. static Int mdBindDev(Ptr *hDevice, Int devid, Ptr devParams);
  36. static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
  37.         Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg);
  39. /*
  40.  * Public IOM interface table.
  41.  */
  42. IOM_Fxns DSK5510_DMA_AIC23_FXNS;
  44. /* CSL handle to the McBSP2. The McBSP is shared between the two channels */
  45. static MCBSP_Config mcbspCfg2 = {
  46.     MCBSP_SPCR1_RMK(
  47.         MCBSP_SPCR1_DLB_OFF,                   /* DLB      = 0 */
  48.         MCBSP_SPCR1_RJUST_RZF,                 /* RJUST    = 0 */
  49.         MCBSP_SPCR1_CLKSTP_DISABLE,            /* CLKSTP   = 0 */
  50.         MCBSP_SPCR1_DXENA_NA,                  /* DXENA    = 0 */
  51.         MCBSP_SPCR1_ABIS_DISABLE,              /* ABIS     = 0 */
  52.         MCBSP_SPCR1_RINTM_RRDY,                /* RINTM    = 0 */
  53.         0,                                     /* RSYNCER  = 0 */
  54.         0,                                     /* RFULL    = 0 */
  55.         0,                                     /* RRDY     = 0 */
  56.         MCBSP_SPCR1_RRST_DISABLE               /* RRST     = 0 */
  57.     ),
  58.     MCBSP_SPCR2_RMK(
  59.         MCBSP_SPCR2_FREE_NO,                   /* FREE     = 0 */
  60.         MCBSP_SPCR2_SOFT_YES,                  /* SOFT     = 1 */
  61.         MCBSP_SPCR2_FRST_RESET,                /* FRST     = 0 */
  62.         MCBSP_SPCR2_GRST_RESET,                /* GRST     = 0 */
  63.         MCBSP_SPCR2_XINTM_XRDY,                /* XINTM    = 0 */
  64.         0,                                     /* XSYNCER  = 0 */
  65.         0,                                     /* XEMPTY   = 0 */
  66.         0,                                     /* XRDY     = 0 */
  67.         MCBSP_SPCR2_XRST_DISABLE               /* XRST     = 0 */
  68.     ),
  69.     MCBSP_RCR1_RMK(
  70.         MCBSP_RCR1_RFRLEN1_OF(1),              /* RFRLEN1  = 1 */
  71.         MCBSP_RCR1_RWDLEN1_16BIT               /* RWDLEN1  = 2 */
  72.     ),
  73.     MCBSP_RCR2_RMK(
  74.         MCBSP_RCR2_RPHASE_SINGLE,              /* RPHASE   = 0 */
  75.         MCBSP_RCR2_RFRLEN2_OF(0),              /* RFRLEN2  = 0 */
  76.         MCBSP_RCR2_RWDLEN2_8BIT,               /* RWDLEN2  = 0 */
  77.         MCBSP_RCR2_RCOMPAND_MSB,               /* RCOMPAND = 0 */
  78.         MCBSP_RCR2_RFIG_YES,                   /* RFIG     = 0 */
  79.         MCBSP_RCR2_RDATDLY_0BIT                /* RDATDLY  = 0 */
  80.     ),
  81.     MCBSP_XCR1_RMK(
  82.         MCBSP_XCR1_XFRLEN1_OF(1),              /* XFRLEN1  = 1 */
  83.         MCBSP_XCR1_XWDLEN1_16BIT               /* XWDLEN1  = 2 */
  84.     ),
  85.     MCBSP_XCR2_RMK(
  86.         MCBSP_XCR2_XPHASE_SINGLE,              /* XPHASE   = 0 */
  87.         MCBSP_XCR2_XFRLEN2_OF(0),              /* XFRLEN2  = 0 */
  88.         MCBSP_XCR2_XWDLEN2_8BIT,               /* XWDLEN2  = 0 */
  89.         MCBSP_XCR2_XCOMPAND_MSB,               /* XCOMPAND = 0 */
  90.         MCBSP_XCR2_XFIG_YES,                   /* XFIG     = 0 */
  91.         MCBSP_XCR2_XDATDLY_0BIT                /* XDATDLY  = 0 */
  92.     ),
  93.     MCBSP_SRGR1_RMK(
  94.         MCBSP_SRGR1_FWID_OF(0),                /* FWID     = 0 */
  95.         MCBSP_SRGR1_CLKGDV_OF(0)               /* CLKGDV   = 0 */
  96.     ),
  97.     MCBSP_SRGR2_RMK(
  98.         MCBSP_SRGR2_GSYNC_FREE,                /* FREE     = 0 */
  99.         MCBSP_SRGR2_CLKSP_RISING,              /* CLKSP    = 0 */
  100.         MCBSP_SRGR2_CLKSM_CLKS,                /* CLKSM    = 0 */
  101.         MCBSP_SRGR2_FSGM_DXR2XSR,              /* FSGM     = 0 */
  102.         MCBSP_SRGR2_FPER_OF(0)                 /* FPER     = 0 */
  103.     ),
  104.     MCBSP_MCR1_DEFAULT,
  105.     MCBSP_MCR2_DEFAULT,
  106.     MCBSP_PCR_RMK(
  107.         MCBSP_PCR_IDLEEN_RESET,                /* IDLEEN   = 0 */
  108.         MCBSP_PCR_XIOEN_SP,                    /* XIOEN    = 0 */
  109.         MCBSP_PCR_RIOEN_SP,                    /* RIOEN    = 0 */
  110.         MCBSP_PCR_FSXM_EXTERNAL,               /* FSXM     = 0 */
  111.         MCBSP_PCR_FSRM_EXTERNAL,               /* FSRM     = 0 */
  112.         MCBSP_PCR_SCLKME_NO,                   /* SCLKME   = 0 */
  113.         0,                                     /* CLKSSTAT = 0 */
  114.         0,                                     /* DXSTAT   = 0 */
  115.         0,                                     /* DRSTAT   = 0 */
  116.         MCBSP_PCR_CLKXM_INPUT,                 /* CLKXM    = 0 */
  117.         MCBSP_PCR_CLKRM_INPUT,                 /* CLKRM    = 0 */
  118.         MCBSP_PCR_FSXP_ACTIVEHIGH,             /* FSXP     = 0 */
  119.         MCBSP_PCR_FSRP_ACTIVEHIGH,             /* FSRP     = 0 */
  120.         MCBSP_PCR_CLKXP_FALLING,               /* CLKXP    = 1 */
  121.         MCBSP_PCR_CLKRP_RISING                 /* CLKRP    = 1 */
  122.     ),
  123.     MCBSP_RCERA_DEFAULT,
  124.     MCBSP_RCERB_DEFAULT,
  125.     MCBSP_RCERC_DEFAULT,
  126.     MCBSP_RCERD_DEFAULT,
  127.     MCBSP_RCERE_DEFAULT,
  128.     MCBSP_RCERF_DEFAULT,
  129.     MCBSP_RCERG_DEFAULT,
  130.     MCBSP_RCERH_DEFAULT,
  131.     MCBSP_XCERA_DEFAULT,
  132.     MCBSP_XCERB_DEFAULT,
  133.     MCBSP_XCERC_DEFAULT,
  134.     MCBSP_XCERD_DEFAULT,
  135.     MCBSP_XCERE_DEFAULT,
  136.     MCBSP_XCERF_DEFAULT,
  137.     MCBSP_XCERG_DEFAULT,
  138.     MCBSP_XCERH_DEFAULT
  139. };
  142. /*  CSL to handle the DMA Channels 4 and 5 */
  143. static DMA_Config dmaRxCfg = {
  144.     0,                         /* DMACSDP will be initialized by mdBindDev */
  145.     DMA_DMACCR_RMK(
  146.         DMA_DMACCR_DSTAMODE_POSTINC,
  147.         DMA_DMACCR_SRCAMODE_CONST,
  148.         DMA_DMACCR_ENDPROG_OFF,
  149.         DMA_DMACCR_REPEAT_OFF,
  150.         DMA_DMACCR_AUTOINIT_OFF,
  151.         DMA_DMACCR_EN_STOP,
  152.         DMA_DMACCR_PRIO_HI,
  153.         DMA_DMACCR_FS_DISABLE,
  154.         DMA_DMACCR_SYNC_REVT2
  155.     ),                              /* DMACCR   */
  156.     DMA_DMACICR_RMK(
  157.         DMA_DMACICR_BLOCKIE_OFF,
  158.         DMA_DMACICR_LASTIE_OFF,
  159.         DMA_DMACICR_FRAMEIE_ON,
  160.         DMA_DMACICR_FIRSTHALFIE_OFF,
  161.         DMA_DMACICR_DROPIE_OFF,
  162.         DMA_DMACICR_TIMEOUTIE_OFF
  163.     ),                             /* DMACICR                          */
  164.     (DMA_AdrPtr)((Uint32)(_MCBSP_DRR12_ADDR<<1)), /*DMACSSAL=MCBSP2 DRR*/
  165.     0x0000,                        /* DMACSSAU                         */
  166.     (DMA_AdrPtr)0x0000,            /* DMACDSAL, to be loaded by submit */
  167.     0x0000,                        /* DMACDSAU                         */
  168.     0x0000,                        /* DMACEN                           */
  169.     0x0001,                        /* DMACFN                           */
  170.     0x0000,                        /* DMACFI                           */
  171.     0x0000                         /* DMACEI                           */
  172. };
  174. static DMA_Config dmaTxCfg = {
  175.     0,                           /* DMACSDP will be initialized by mdBindDev */
  176.     DMA_DMACCR_RMK(
  177.         DMA_DMACCR_DSTAMODE_CONST,
  178.         DMA_DMACCR_SRCAMODE_POSTINC,
  179.         DMA_DMACCR_ENDPROG_OFF,
  180.         DMA_DMACCR_REPEAT_OFF,
  181.         DMA_DMACCR_AUTOINIT_OFF,
  182.         DMA_DMACCR_EN_STOP,
  183.         DMA_DMACCR_PRIO_HI,
  184.         DMA_DMACCR_FS_DISABLE,
  185.         DMA_DMACCR_SYNC_XEVT2
  186.     ),                              /* DMACCR   */
  187.     DMA_DMACICR_RMK(
  188.         DMA_DMACICR_BLOCKIE_OFF,
  189.         DMA_DMACICR_LASTIE_OFF,
  190.         DMA_DMACICR_FRAMEIE_ON,
  191.         DMA_DMACICR_FIRSTHALFIE_OFF,
  192.         DMA_DMACICR_DROPIE_OFF,
  193.         DMA_DMACICR_TIMEOUTIE_OFF
  194.     ),                              /* DMACICR                          */
  195.     (DMA_AdrPtr)0x0000,             /* DMACSSAL, to be loaded by submit */
  196.     0x0000,                         /* DMACSSAU                         */
  197.     (DMA_AdrPtr)((Uint32)(_MCBSP_DXR12_ADDR<<1)), /* DMACDSAL=MCBSP2 DXR */
  198.     0x0000,                         /* DMACDSAU                         */
  199.     0x0000,                         /* DMACEN                           */
  200.     0x0001,                         /* DMACFN                           */
  201.     0x0000,                         /* DMACFI                           */
  202.     0x0000                          /* DMACEI                           */
  203. };
  205. /*
  206.  * These arrays are used to initialized csdp value for different DMA port
  207.  * type. This is done by mdBindDev using params->dmaPortType
  208.  */
  209. static Uns rxCsdpValue[3] = {
  210.     DMA_DMACSDP_RMK(            /* DSK5510_DMA_AIC23_PORTTYPE_DARAM */
  211.         DMA_DMACSDP_DSTBEN_NOBURST,
  212.         DMA_DMACSDP_DSTPACK_OFF,
  213.         DMA_DMACSDP_DST_DARAM,
  214.         DMA_DMACSDP_SRCBEN_NOBURST,
  215.         DMA_DMACSDP_SRCPACK_OFF,
  216.         DMA_DMACSDP_SRC_PERIPH,
  217.         DMA_DMACSDP_DATATYPE_16BIT
  218.     ),
  219.     DMA_DMACSDP_RMK(            /* DSK5510_DMA_AIC23_PORTTYPE_SARAM */
  220.         DMA_DMACSDP_DSTBEN_NOBURST,
  221.         DMA_DMACSDP_DSTPACK_OFF,
  222.         DMA_DMACSDP_DST_SARAM,
  223.         DMA_DMACSDP_SRCBEN_NOBURST,
  224.         DMA_DMACSDP_SRCPACK_OFF,
  225.         DMA_DMACSDP_SRC_PERIPH,
  226.         DMA_DMACSDP_DATATYPE_16BIT
  227.     ),
  228.     DMA_DMACSDP_RMK(            /* DSK5510_DMA_AIC23_PORTTYPE_EMIF */
  229.         DMA_DMACSDP_DSTBEN_NOBURST,
  230.         DMA_DMACSDP_DSTPACK_OFF,
  231.         DMA_DMACSDP_DST_EMIF,
  232.         DMA_DMACSDP_SRCBEN_NOBURST,
  233.         DMA_DMACSDP_SRCPACK_OFF,
  234.         DMA_DMACSDP_SRC_PERIPH,
  235.         DMA_DMACSDP_DATATYPE_16BIT
  236.     )
  237. };
  239. static Uns txCsdpValue[3] = {
  240.     DMA_DMACSDP_RMK(            /* DSK5510_DMA_AIC23_PORTTYPE_DARAM */
  241.         DMA_DMACSDP_DSTBEN_NOBURST,
  242.         DMA_DMACSDP_DSTPACK_OFF,
  243.         DMA_DMACSDP_DST_PERIPH,
  244.         DMA_DMACSDP_SRCBEN_NOBURST,
  245.         DMA_DMACSDP_SRCPACK_OFF,
  246.         DMA_DMACSDP_SRC_DARAM,
  247.         DMA_DMACSDP_DATATYPE_16BIT
  248.     ),
  249.     DMA_DMACSDP_RMK(            /* DSK5510_DMA_AIC23_PORTTYPE_SARAM */
  250.         DMA_DMACSDP_DSTBEN_NOBURST,
  251.         DMA_DMACSDP_DSTPACK_OFF,
  252.         DMA_DMACSDP_DST_PERIPH,
  253.         DMA_DMACSDP_SRCBEN_NOBURST,
  254.         DMA_DMACSDP_SRCPACK_OFF,
  255.         DMA_DMACSDP_SRC_SARAM,
  256.         DMA_DMACSDP_DATATYPE_16BIT
  257.     ),
  258.     DMA_DMACSDP_RMK(            /* DSK5510_DMA_AIC23_PORTTYPE_EMIF */
  259.         DMA_DMACSDP_DSTBEN_NOBURST,
  260.         DMA_DMACSDP_DSTPACK_OFF,
  261.         DMA_DMACSDP_DST_PERIPH,
  262.         DMA_DMACSDP_SRCBEN_NOBURST,
  263.         DMA_DMACSDP_SRCPACK_OFF,
  264.         DMA_DMACSDP_SRC_EMIF,
  265.         DMA_DMACSDP_DATATYPE_16BIT
  266.     )
  267. };
  269. /*
  270.  *  ======== mdBindDev ========
  271.  */
  272. #pragma CODE_SECTION(mdBindDev, ".text:init")
  273. static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams)
  274. {
  275.     DSK5510_DMA_AIC23_DevParams *params =
  276.         (DSK5510_DMA_AIC23_DevParams *)devParams;
  277.     C55XX_DMA_MCBSP_DevParams genericDevParams;
  278.     DSK5510_DMA_AIC23_DevParams defaultParams = 
  279.                         DSK5510_DMA_AIC23_DEVPARAMS_DEFAULT;
  281.     /* use default parameters if none are given */
  282.     if (params == NULL) {
  283.         params = &defaultParams;
  284.     }
  286.     /* Check the version number */
  287.     if (params->versionId != DSK5510_DMA_AIC23_VERSION_1){
  288.         /* Unsupported version */
  289.         return(IOM_EBADARGS);
  290.     }
  292.     /* set codec parameters (this will also initialize the codec) */
  293.     if (!AIC23_setParams(&(params->aic23))) {
  294.         return(IOM_EBADIO);
  295.     }
  297.     /* set dmacsdp register to the right dma port type */
  298.     dmaRxCfg.dmacsdp = rxCsdpValue[params->dmaPortType];
  299.     dmaTxCfg.dmacsdp = txCsdpValue[params->dmaPortType];
  301.     genericDevParams.versionId = C55XX_DMA_MCBSP_VERSION_1;
  302.     genericDevParams.rxDmaId = params->rxDmaId;
  303.     genericDevParams.txDmaId = params->txDmaId;
  304.     genericDevParams.mcbspCfg = &mcbspCfg2;
  305.     genericDevParams.rxIerMask[0] = params->rxIerMask[0];
  306.     genericDevParams.rxIerMask[1] = params->rxIerMask[1];
  307.     genericDevParams.txIerMask[0] = params->txIerMask[0];
  308.     genericDevParams.txIerMask[1] = params->txIerMask[1];
  309.     
  311.     return (C55XX_DMA_MCBSP_FXNS.mdBindDev(devp, MCBSP_PORT2,
  312.             &genericDevParams));
  313. }
  315. /*
  316.  *  ======== mdCreateChan ========
  317.  */
  318. static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
  319.                 Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg)
  320. {
  321.     C55XX_DMA_MCBSP_ChanParams genericChanParams;
  323.     if (mode == IOM_INPUT) {
  324.         genericChanParams.dmaCfg = &dmaRxCfg;
  325.     }
  326.     else if (mode == IOM_OUTPUT) {
  327.         genericChanParams.dmaCfg = &dmaTxCfg;
  328.     }
  329.     else {
  330.         return (IOM_EBADMODE);
  331.     }
  333.     return (C55XX_DMA_MCBSP_FXNS.mdCreateChan(chanp, devp, name, mode,
  334.         &genericChanParams, cbFxn, cbArg));
  335. }
  337. /*
  338.  *  ======== DSK5510_DMA_AIC23_init ========
  339.  *
  340.  *  Controller initialization function
  341.  */
  342. #pragma CODE_SECTION(DSK5510_DMA_AIC23_init, ".text:init")
  343. Void DSK5510_DMA_AIC23_init(Void)
  344. {
  345.     /*
  346.      * Use C55XX_DMA_MCBSP_FXNS functions for the heart of the 
  347.      * controller.  This is common DMA/MCBSP code that works for
  348.      * many DMA/MCBSP/codec combinations.
  349.      */
  350.     C55XX_DMA_MCBSP_init();
  352.     DSK5510_DMA_AIC23_FXNS = C55XX_DMA_MCBSP_FXNS;
  353.     DSK5510_DMA_AIC23_FXNS.mdBindDev = mdBindDev;
  354.     DSK5510_DMA_AIC23_FXNS.mdCreateChan = mdCreateChan;
  355. }