evmdm642_vdisparamsVGA.c
上传用户:dahaojd
上传日期:2008-01-29
资源大小:14357k
文件大小:5k
源码类别:

DSP编程

开发平台:

C/C++

  1. /*
  2.  *  Copyright 2003 by Texas Instruments Incorporated.
  3.  *  All rights reserved. Property of Texas Instruments Incorporated.
  4.  *  Restricted rights to use, duplicate or disclose this code are
  5.  *  granted through contract.
  6.  *  
  7.  */
  8. /* "@(#) DDK 1.11.00.00 11-04-03 (ddk-b13)" */
  9. #include <vport.h>
  10. #include <vportdis.h>
  11. #include <saa7105.h> 
  12. #include <csl_edma.h>
  13. #include "evmdm642_vdisparams.h"
  14. #define LINE_SZ   640
  15. #define NUM_LINES 480
  16. VPORTDIS_Params EVMDM642_vDisParamsChan = {
  17.     VPORT_MODE_RAW_16BIT, /* dmode:3       */
  18.     VPORT_FLDOP_PROGRESSIVE,/* fldOp:3       */
  19.     VPORT_SCALING_DISABLE,     /* scale:1       */    
  20.     VPORT_RESMPL_DISABLE,      /* resmpl:1      */      
  21.     VPORTDIS_DEFVAL_ENABLE,    /* defValEn:1    */
  22.     VPORTDIS_BPK_10BIT_NORMAL, /*bpk10Bit:1 */
  23.     
  24.     VPORTDIS_VCTL1_HSYNC,  /* vctl1Config:2 */
  25.     VPORTDIS_VCTL2_VSYNC,  /* vctl2Config:2 */
  26.     VPORTDIS_VCTL3_FLD,  /* vctl3Config:1 */
  27.     VPORTDIS_EXC_DISABLE,  /* extCtl:3      */
  28.                
  29.     800,                   /* frmHSize */
  30.     525,                   /* frmVSize */
  31.     0,                     /* imgHOffsetFld1 */
  32.     0,                     /* imgVOffsetFld1 */
  33.     LINE_SZ,               /* imgHSizeFld1   */
  34.     NUM_LINES,             /* imgVSizeFld1   */
  35.     
  36.     0,                     /* imgHOffsetFld2 */
  37.     0,                     /* imgVOffsetFld2 */
  38.     0,                     /* imgHSizeFld2   */
  39.     0,                     /* imgVSizeFld2   */
  40.     640,                   /* hBlnkStart      */                    
  41.     0,                     /* hBlnkStop       */                    
  42.     
  43.     0,                     /* vBlnkXStartFld1 */                    
  44.     1,                     /* vBlnkYStartFld1 */                    
  45.     0,                     /* vBlnkXStopFld1  */                    
  46.     46,                    /* vBlnkYStopFld1  */                    
  47.     
  48.     0,                     /* vBlnkXStartFld2 */                    
  49.     0,                     /* vBlnkYStartFld2 */                    
  50.     0,                     /* vBlnkXStopFld2  */                    
  51.     0,                     /* vBlnkYStopFld2  */                    
  52.     
  53.     0,                     /* xStartFld1 */                         
  54.     1,                     /* yStartFld1 */                         
  55.     
  56.     0,                     /* xStartFld2 */                         
  57.     0,                     /* yStartFld2 */                         
  58.     656-3,                 /* hSyncStart */                         
  59.     752-3,                 /* hSyncStop  */                         
  60.     656-3,                 /* vSyncXStartFld1 */                    
  61.     11,                    /* vSyncYStartFld1 */                    
  62.     656-3,                 /* vSyncXStopFld1  */                    
  63.     13,                    /* vSyncYStopFld1  */                    
  64.     0,                     /* vSyncXStartFld2 */                    
  65.     0,                     /* vSyncYStartFld2 */                    
  66.     0,                     /* vSyncXStopFld2  */                    
  67.     0,                     /* vSyncYStopFld2  */                    
  68.     0x10,                   /* yClipLow        */                    
  69.     0xf0,                   /* yClipHigh       */                    
  70.     
  71.     0x10,                   /* cClipLow        */                    
  72.     0xf0,                   /* cClipHigh       */                    
  73.     
  74.     0x0,                    /*VPDIS_DefVal     */                    
  75.     0x0,
  76.     0x0,
  77.     VPORTDIS_RGBX_DISABLE,  /*rawPk_3_4 disable raw 3/4 packing for RGB output*/
  78.     1,                     /* incPix, for raw mode only */          
  79.     (LINE_SZ>>3),          /*thrld     */
  80.     3,                     /*numFrmBufs*/
  81.     128,                     /*alignment */
  82.     VPORT_FLDS_MERGED,     /*mergeFlds */
  83.     NULL,                  /*segId     */            
  84.     EDMA_OPT_PRI_HIGH,     /*edmaPri   */
  85.     8                      /* irqId    */    
  86. };
  87. VPORT_PortParams EVMDM642_vDisParamsPort = {
  88.     FALSE,                      /*  enableDualChan;     */ 
  89.     VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 1 polarity    */
  90.     VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 2 polarity    */
  91.     VPORT_POLARITY_ACTIVE_HIGH, /* vport control pin 3 polarity    */
  92.     &SAA7105_Fxns,
  93.     INV,
  94. };    
  95.           
  96. SAA7105_ConfParams EVMDM642_vDisParamsSAA7105 = {
  97.   SAA7105_AFMT_RGB,
  98.   SAA7105_MODE_VGA,
  99.   SAA7105_IFMT_RGB565,
  100.   TRUE,
  101.   FALSE,
  102.   INV,                   /*handleI2C */
  103. };