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vportcap.c
资源名称：DSP-C6000-DM642DEMO.rar　[点击查看]
上传用户：dahaojd
上传日期：2008-01-29
资源大小：14357k
文件大小：42k
源码类别：

DSP编程

开发平台：

C/C++

vportcap.c：源码内容
  1. /*
  2.  *  Copyright 2003 by Texas Instruments Incorporated.
  3.  *  All rights reserved. Property of Texas Instruments Incorporated.
  4.  *  Restricted rights to use, duplicate or disclose this code are
  5.  *  granted through contract.
  6.  *  
  7.  */
  8. /* "@(#) DDK 1.11.00.00 11-04-03 (ddk-b13)" */
  10. /* DSP/BIOS standard include files */
  11. #include <std.h>
  12. #include <mem.h>
  13. #include <que.h>     
  14. #include <tsk.h>    
  15. #include <hwi.h>          
  16. #include <clk.h>
  18. /* Chip-support library include files */
  19. #include <csl.h>
  20. #include <csl_edma.h>
  21. #include <csl_vphal.h>         
  22. #include <csl_irq.h>
  23. #include <csl_cache.h>
  25. /* IOM/GIO driver model include files */
  26. #include <iom.h>
  27. #include <fvid.h>                       
  29. /* video driver specific include files */
  30. #include <vport.h>
  31. #include <vportcap.h>
  32. #include <edc.h>
  33. #include "_vport.h"
  35. /* debug include files */
  36. /* to minimize code size and cycle count overhead of the driver */             
  37. /* error checking is only performed at debug time               */
  38. #include <assert.h>
  40. /* type defines and data structures */
  41. /**************************************************************
  42.  *     data structure for video port object                   *
  43.  **************************************************************/
  44. typedef struct PortObj{
  45.     /* port status register, contains information on whether */
  46.     /* port is opened, configured, etc.                      */
  47.     Int     status;
  48.     /* vp base address for all register access */
  49.     Int     base;
  50.     
  51.     /* two channel objects for channel A & B.  */
  52.     /* This is only for capture operation      */
  53.     _VPORT_ChanObj chanObj[2];
  54. } PortObj;
  57. /* mini-driver API functions */
  58. static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams);
  59. static Int mdControlChan(Ptr chanp, Uns cmd, Ptr args);
  60. static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
  61.         Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg);
  62. static Int mdDeleteChan(Ptr chanp);
  63. static Int mdSubmitChan(Ptr chanp, IOM_Packet *packet);
  66. /* local functions */
  67. static void captureEdmaISR(Int tcc);
  68. static void captureISR(Int portNum);
  69. static Int _configCh(Ptr chanp, VPORTCAP_Params *params);
  70. static Int _configChan(Ptr chanp, Ptr args);     
  71. static Int _configPort(Ptr chanp, Ptr args);    
  72. static Int _configTransfer(Ptr chanp,VPORTCAP_Params *params);  
  73. static Int _covrRecover(Ptr chanp);
  74. static Int _setVIntCb(Ptr chanp, Ptr args);
  75. static Int _startVPCapture(Ptr chanp);
  76. static Int _stopVPCapture(Ptr chanp);   
  79. /* global and static variables */
  80. IOM_Fxns VPORTCAP_Fxns = {
  81.     mdBindDev,    
  82.     (IOM_TmdUnBindDev)IOM_mdNotImpl,
  83.     mdControlChan,
  84.     mdCreateChan,
  85.     mdDeleteChan,
  86.     mdSubmitChan
  87. };
  89. /**************************************************************
  90.  * Static allocation and initialization of port objects       *
  91.  **************************************************************/
  92. static PortObj portObjs[_VP_PORT_CNT] = {
  93.     /* video port 0 */
  94.     {0, _VP_BASE_PORT0,
  95.     /* channel A */  
  96.         {{0, 0, 0, _VP_BASE_CHAPORT0, EDMA_CHA_VP0EVTYA, EDMA_CHA_VP0EVTUA, 
  97.         EDMA_CHA_VP0EVTVA, _VP_YSRCA0_ADDR, _VP_CBSRCA0_ADDR, 
  98.         _VP_CRSRCA0_ADDR }, 
  99.     /* channel B */  
  100.         {0, 0, 1, _VP_BASE_CHBPORT0, EDMA_CHA_VP0EVTYB, EDMA_CHA_VP0EVTUB, 
  101.         EDMA_CHA_VP0EVTVB,  _VP_YSRCB0_ADDR, _VP_CBSRCB0_ADDR, 
  102.         _VP_CRSRCB0_ADDR}}},
  104.     /* video port 1 */
  105.     {0, _VP_BASE_PORT1, 
  106.     /* channel A */  
  107.         {{0, 1, 0, _VP_BASE_CHAPORT1, EDMA_CHA_VP1EVTYA, EDMA_CHA_VP1EVTUA, 
  108.         EDMA_CHA_VP1EVTVA, _VP_YSRCA1_ADDR, _VP_CBSRCA1_ADDR, 
  109.         _VP_CRSRCA1_ADDR }, 
  110.     /* channel B */  
  111.         {0, 1, 1, _VP_BASE_CHBPORT1, EDMA_CHA_VP1EVTYB, EDMA_CHA_VP1EVTUB, 
  112.         EDMA_CHA_VP1EVTVB, _VP_YSRCB1_ADDR, _VP_CBSRCB1_ADDR, 
  113.         _VP_CRSRCB1_ADDR}}},
  115.     /* video port 2 */
  116.     {0, _VP_BASE_PORT2,
  117.     /* channel A */  
  118.         {{0, 2, 0, _VP_BASE_CHAPORT2, EDMA_CHA_VP2EVTYA, EDMA_CHA_VP2EVTUA, 
  119.          EDMA_CHA_VP2EVTVA, _VP_YSRCA2_ADDR, _VP_CBSRCA2_ADDR, 
  120.          _VP_CRSRCA2_ADDR  }, 
  121.     /* channel B */  
  122.         {0, 2, 1, _VP_BASE_CHBPORT2, EDMA_CHA_VP2EVTYB, EDMA_CHA_VP2EVTUB, 
  123.          EDMA_CHA_VP2EVTVB,  _VP_YSRCB2_ADDR, _VP_CBSRCB2_ADDR, 
  124.          _VP_CRSRCB2_ADDR }}}
  125. };
  129. /*
  130.  *  =================== mdBindDev ============================
  131.  *  Register all external devices to video port capture driver 
  132.  */
  133. static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams)
  134. {
  135.     Int portNum = devid;         
  136.     volatile Int i;
  137.     volatile Int* base = (volatile Int *)portObjs[portNum].base;                       
  138.    
  139.     assert(portNum < _VP_PORT_CNT);
  140.     base[_VP_VPCTL_OFFSET] = 
  141.              VP_VPCTL_VPRST_RESET << _VP_VPCTL_VPRST_SHIFT;
  142.     for(i = 0; i < 100000; i ++);             
  143.    
  144.     *devp = &portObjs[portNum];                                                                                           
  145.     return mdControlChan(&portObjs[portNum], VPORT_CMD_CONFIG_PORT, devParams); 
  146. }
  149. /*
  150.  *  ======== mdControlChan ========
  151.  */
  152. static Int mdControlChan(Ptr chanp, Uns cmd, Ptr args)
  153. {
  154.     Int retVal = IOM_EBADMODE;
  155.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  156.     PortObj* port = &portObjs[chan->portNum];
  158.     switch (cmd) {
  159.         case VPORT_CMD_START:
  160.         retVal = _startVPCapture(chanp);
  161.         break;
  162.         case VPORT_CMD_STOP:
  163.         retVal = _stopVPCapture(chanp);
  164.         break;
  165.         case VPORT_CMD_SET_VINTCB:
  166.         retVal = _setVIntCb(chanp, args);
  167.         break;
  168.         case VPORT_CMD_CONFIG_PORT:
  169.         retVal = _configPort(chanp, args);
  170.         break;
  171.         case VPORT_CMD_COVR_RECOVER:
  172.         retVal = _covrRecover(chanp);
  173.         break;
  174.         case VPORT_CMD_CONFIG_CHAN:
  175.         if(! (port->status & _VPORT_CFGED)) {
  176.             retVal = _configChan(chanp, args);
  177.         }
  178.         break;
  179.         default: 
  180.         if(chan->edcFxns!=INV){
  181.             retVal = chan->edcFxns->ctrl(chan->edcHandle, 
  182.                 cmd-VPORT_CMD_EDC_BASE,(Arg)args);
  183.         }else {
  184.             retVal = IOM_ENOTIMPL;
  185.         } 
  186.         break;   
  187.     }
  188.     return retVal;
  189. }              
  192. /*
  193.  *  =================== mdCreateChan ============================
  194.  *  create a capture channel
  195.  */
  196. static Int  mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
  197.                       Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg)
  198. {
  199.     Int chanNum;           
  200.     volatile Int* base;
  201.     PortObj* port;
  202.     Int retVal = IOM_COMPLETED;       
  203.      
  205.     if(mode != IOM_INPUT){
  206.         return IOM_EBADARGS;
  207.     }
  208.     if(*name ++ != '/') {
  209.         return IOM_EBADARGS;
  210.     }
  211.     chanNum = *name ++ - 'A';
  213.     assert(chanNum < _VPORT_CHAN_CNT);
  214.     
  215.     port = (PortObj *)devp;
  216.     if(port->chanObj[chanNum].edcFxns != INV) {
  217.         /* open external device */
  218.         port->chanObj[chanNum].edcHandle 
  219.            = port->chanObj[chanNum].edcFxns->open(name, (Arg)INV);
  220.     } 
  221.     if(! (port->status & _VPORT_OPENED)) {
  222.         port->status |= _VPORT_OPENED;
  223.         base = (volatile Int *)port->base;                       
  224.         
  225.         /* reset both channels */
  226.         base[_VP_VCACTL_OFFSET] |= 
  227.             VP_VCACTL_RSTCH_RESET << _VP_VCACTL_RSTCH_SHIFT;
  228.         base[_VP_VCBCTL_OFFSET] |= 
  229.             VP_VCBCTL_RSTCH_RESET << _VP_VCBCTL_RSTCH_SHIFT;
  230.     } /* if(!port->opened)  */
  231.     /* initialize the channel object */
  232.     if(! (port->chanObj[chanNum].status & _VPORT_OPENED)) {
  233.         Int j;
  234.         _VPORT_ChanObj *chan = &port->chanObj[chanNum];       
  235.         chan->status |= _VPORT_OPENED;
  236.         chan->vIntMask = 0;
  237.         QUE_new(&chan->qIn);
  238.         chan->cbFxn = cbFxn;
  239.         chan->vIntFxn = (VPORT_IntCallBack)INV;
  240.         chan->queEmpty = FALSE;   
  241.         chan->cbArg = (Arg)cbArg;
  242.         chan->mrViop = INV;
  243.         chan->packetIOM = INV;     
  244.         chan->numFrms = 0;
  245.         chan->vIntCbArg = (Int)INV;
  246.         chan->bufSz = 0;
  247.         for(j = 0; j < _VPORT_NUM_EDMA_CHANS && retVal == IOM_COMPLETED; j ++){
  248.             
  249.             if( (chan->hEdma[j] = EDMA_open(chan->edmaChanNum[j], 
  250.                 EDMA_OPEN_RESET))==EDMA_HINV
  251.             ||  (chan->hRld[4 * j] = EDMA_allocTable(-1))==EDMA_HINV
  252.             ||  (chan->hRld[4 * j + 1] = EDMA_allocTable(-1))==EDMA_HINV
  253.             ||  (chan->hRld[4 * j + 2] = EDMA_allocTable(-1))==EDMA_HINV
  254.             ||  (chan->hRld[4 * j + 3] = EDMA_allocTable(-1))==EDMA_HINV
  255.             ||  (chan->tcc[j] = EDMA_intAlloc(chan->edmaChanNum[j])) == -1){
  256.                 retVal = IOM_EALLOC;
  257.             }/* if((port->...*/ 
  258.         }/* for(j = 0; j < NUM_EDMA_CHANS; j++) {...*/
  259.         if( retVal == IOM_COMPLETED && (void *)chanParams != INV) {
  260.             retVal = mdControlChan(&port->chanObj[chanNum], 
  261.                 VPORT_CMD_CONFIG_CHAN, chanParams); 
  262.         }
  263.         if(retVal == IOM_COMPLETED) {
  264.              /* configure the channel */
  265.              *chanp = &port->chanObj[chanNum];
  266.         }else {
  267.             mdDeleteChan(&port->chanObj);
  268.             *chanp = INV;                     
  269.         }               
  270.     } /*if(!chan->opened) */
  271.     return retVal;
  272. }               
  275. /*
  276.  *  =================== mdDeleteChan ============================
  277.  *  delete the capture channel
  278.  */
  280. static Int  mdDeleteChan(Ptr chanp)
  281. {
  282.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  283.     PortObj* port = &portObjs[chan->portNum];
  284.     Int j;
  285.     volatile Int* base;
  286.     
  287.     if(chan->status & _VPORT_OPENED) {
  288.         chan->status = 0;
  289.         mdControlChan(chanp, VPORT_CMD_STOP, NULL);
  290.         for(j = 0; j < _VPORT_NUM_EDMA_CHANS; j ++) {
  291.             EDMA_disableChannel(chan->hEdma[j]);
  292.             EDMA_clearChannel(chan->hEdma[j]);
  293.             EDMA_close(chan->hEdma[j]);
  294.             EDMA_freeTable(chan->hRld[4 * j]);
  295.             EDMA_freeTable(chan->hRld[4 * j + 1]);
  296.             EDMA_freeTable(chan->hRld[4 * j + 2]);
  297.             EDMA_freeTable(chan->hRld[4 * j + 3]);
  298.             EDMA_intFree(chan->tcc[j]);
  299.         }
  300.         for(j = 0; j < chan->numFrms ; j ++) {
  301.             MEM_free(chan->segId, chan->viops[j].frame.iFrm.y1, chan->bufSz);
  302.         }        
  303.         /* close external device */
  304.         if(chan->edcFxns != INV) {
  305.             chan->edcFxns->close(chan->edcHandle);
  306.         }
  307.     }    
  308.     
  309.     if(! (port->chanObj[0].status & _VPORT_OPENED) 
  310.        && ! (port->chanObj[1].status & _VPORT_OPENED)) {
  311.         base = (volatile Int *)port->base;
  312.         /* reset both channels */
  313.         base[_VP_VCACTL_OFFSET] |= 
  314.             VP_VCACTL_RSTCH_RESET << _VP_VCACTL_RSTCH_SHIFT;
  315.         base[_VP_VCBCTL_OFFSET] |= 
  316.             VP_VCBCTL_RSTCH_RESET << _VP_VCBCTL_RSTCH_SHIFT;
  318.         /* reset video port */
  319.         base[_VP_VPCTL_OFFSET] |= 
  320.             VP_VPCTL_VPRST_RESET << _VP_VPCTL_VPRST_SHIFT;
  321.         port->status = 0;
  322.     }
  323.     return IOM_COMPLETED;
  324. }
  327. /*
  328.  *  ======== mdSubmitChan ========
  329.  */
  330. static Int  mdSubmitChan(Ptr chanp, IOM_Packet *packet)
  331. {
  333.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  334.     FVID_Frame* viop;                             
  335.     Uint32 gie = IRQ_globalDisable();
  336.     Int retVal = IOM_PENDING;  
  337.     Int offset = chan->nextEDMARlds << 1;
  338.     Bool nextViopChanged = FALSE;             
  339.     Bool notToLate = TRUE;
  340.     volatile Int* cBase = (volatile Int *)chan->base;
  341.     Int capStatReg = cBase[_VP_VCASTAT_OFFSETA];
  342.     short lineNum;
  343.     
  344.      
  345.     /* get the current line number being captured */
  346.     lineNum = (capStatReg & _VP_VCASTAT_VCYPOS_MASK)
  347.                            >> _VP_VCASTAT_VCYPOS_SHIFT;
  348.             
  349.     /* account for field/frame operation modes */ 
  350.     lineNum += chan->numLinesFld1 
  351.         * ((capStatReg & _VP_VCASTAT_VCFLD_MASK) >> _VP_VCASTAT_VCFLD_SHIFT);    
  353.     /* make sure we are not too close to the end of a frame */
  354.     notToLate = (lineNum < (chan->lastLineNum - 5));
  356.     assert(chan->status & _VPORT_READY);
  357.     if(packet->cmd != FVID_ALLOC 
  358.         && packet->cmd != FVID_FREE 
  359.         && packet->cmd != FVID_EXCHANGE){    
  360.         /* other commands not supported */
  361.         return IOM_ENOTIMPL;    
  362.     }
  363.     
  364.     if(packet->cmd != FVID_ALLOC) {/* FVID_FREE or FVID_EXCHANGE */
  365.         viop = *(void **)packet->addr; /* pointer of a video I/O packet */
  366.         if(chan->queEmpty && notToLate) {
  367.             /* don't put it into queue, update the rld register directly */
  368.             chan->nextViop = viop; 
  369.             nextViopChanged = TRUE;
  370.         } 
  371.         else {               
  372.             QUE_enqueue(&chan->qIn, (QUE_Handle)viop);    
  373.         }
  374.         chan->queEmpty = FALSE;
  375.         retVal = packet->status = IOM_COMPLETED;
  376.     }
  377.     if(packet->cmd != FVID_FREE) {/* FVID_ALLOC or FVID_EXCHANGE */
  378.         if(chan->mrViop != INV) {
  379.             /* only when there is no outstanding pending request */
  380.             if(chan->packetIOM == INV){
  381.                 if(chan->nextViop != chan->mrViop){
  382.                     *(void **)packet->addr = (void *)chan->mrViop;
  383.                     chan->mrViop = INV;
  384.                     packet->size = sizeof(FVID_Frame);
  385.                     retVal = packet->status = IOM_COMPLETED;                
  386.                 } else {
  387.                     if (notToLate) {
  388.                         *(void **)packet->addr = (void *)chan->mrViop;
  389.                         chan->mrViop = INV;
  390.                         packet->size = sizeof(FVID_Frame);
  391.                         retVal = packet->status = IOM_COMPLETED;
  392.                         /* If queue is already empty, it means the driver currently*/
  393.                         /* only owns one frame, which is the current frame. So make*/
  394.                         /* the next frame the same as the current one              */
  395.                         chan->nextViop = chan->curViop;
  396.                     } else {
  397.                         chan->mrViop = INV; /* too late, just recycle the mrViop */                    
  398.                         chan->packetIOM = packet;
  399.                         retVal = packet->status = IOM_PENDING;
  400.                     }
  401.                 }
  402.             }
  403.             else retVal = IOM_EINUSE;    
  404.         } else {
  405.             chan->packetIOM = packet;
  406.             retVal = packet->status = IOM_PENDING;
  407.         }        
  408.     }    
  409.     if(nextViopChanged) {
  410.         /* now modify the EDMA rld entries */
  411.         if(chan->mergeFlds){
  412.             EDMA_RSETH(chan->hRld[offset], DST, 
  413.                 chan->nextViop->frame.iFrm.y1);
  414.             EDMA_RSETH(chan->hRld[offset + 1], DST, 
  415.                 chan->nextViop->frame.iFrm.y2);
  416.             EDMA_RSETH(chan->hRld[4 + offset], DST, 
  417.                 chan->nextViop->frame.iFrm.cb1);     
  418.             EDMA_RSETH(chan->hRld[5 + offset], DST, 
  419.                 chan->nextViop->frame.iFrm.cb2);                         
  420.             EDMA_RSETH(chan->hRld[8 + offset], DST, 
  421.                 chan->nextViop->frame.iFrm.cr1);     
  422.             EDMA_RSETH(chan->hRld[9 + offset], DST, 
  423.                 chan->nextViop->frame.iFrm.cr2);              
  424.         } else {
  425.             EDMA_RSETH(chan->hRld[offset], DST, 
  426.                 chan->nextViop->frame.iFrm.y1);
  427.             EDMA_RSETH(chan->hRld[4 + offset], DST, 
  428.                 chan->nextViop->frame.iFrm.cb1);     
  429.             EDMA_RSETH(chan->hRld[8 + offset], DST, 
  430.                 chan->nextViop->frame.iFrm.cr1);                         
  431.         } /* if(chan->mergeFlds) */            
  432.     }    
  433.     IRQ_globalRestore(gie);
  434.     return retVal;
  435. }
  438. /*
  439.  *  ======== _captureEdmaISR ========
  440.  *  EDMA ISR
  441.  */
  442. static void captureEdmaISR(Int tcc) 
  443. {
  444.     Int i, j;
  445.     Int offset;
  446.     FVID_Frame *viop, *curViop;      
  447.     
  448.     
  449.     /* find out the source of the edma interrupt */
  450.     for(j = 0; j < _VP_PORT_CNT; j ++) {
  451.         for(i = 0; i < _VPORT_CHAN_CNT; i ++ ){ /* loop through two channels */
  452.             _VPORT_ChanObj* chan = &portObjs[j].chanObj[i];    
  453.             if((chan->status & _VPORT_READY)
  454.               && (tcc == chan->tcc[0] || tcc == chan->tcc[1])){
  456.                 /* re-sync tcc with activeEDMARlds */
  457.                 /* they may be out of sync after interrupt over-run */
  458.                 /* e.g. execution is halted at break-point */
  459.                 chan->nextEDMARlds = (tcc == chan->tcc[0]) ? 0 : 1;
  460.                 offset = chan->nextEDMARlds << 1;
  462.                 /* update the current and next viop pointers */
  463.                 curViop = chan->curViop;
  464.                 chan->curViop = chan->nextViop;             
  465.                 
  466.                 /* update the most recent viop */
  467.                 if(curViop != chan->mrViop  && chan->mrViop != INV) {
  468.                       QUE_enqueue(&chan->qIn, chan->mrViop);
  469.                 } 
  470.                 chan->mrViop = curViop;
  472.                 if((viop = (FVID_Frame *)QUE_dequeue(&chan->qIn))
  473.                     !=(FVID_Frame *)&chan->qIn) {
  474.                     /* queue IS not empty */
  475.                     chan->nextViop = viop;
  476.                 }else {
  477.                     if(chan->packetIOM == INV) {
  478.                         /* in queue is empty, but no request is pending */
  479.                         /* recycle the current VIOP back                */
  480.                         /* but still set it as the most recent VIOP     */
  481.                         chan->nextViop = curViop;
  482.                     }
  483.                     chan->queEmpty = TRUE;
  484.                 }                              
  486.                 /* call the channel's callback function */
  487.                 if(curViop != chan->curViop) {
  488.                     if(chan->packetIOM != INV) {
  489.                          /* call the channel's callback function */
  490.                          *(void **)chan->packetIOM->addr = curViop;             
  491.                          chan->packetIOM->size = sizeof(FVID_Frame);
  492.                          chan->cbFxn((Ptr)chan->cbArg, chan->packetIOM);   
  493.                          chan->packetIOM = INV;
  494.                          chan->mrViop = INV;
  495.                     }else if(chan->queEmpty){
  496.                         chan->nextViop = chan->mrViop;
  497.                     }
  498.                 }else {
  499.                     chan->mrViop = INV;
  500.                 }        
  501.                 /* Update the EDMA reload entry  */
  502.                 if(chan->mergeFlds){
  503.                     EDMA_RSETH(chan->hRld[offset], DST, 
  504.                         chan->nextViop->frame.iFrm.y1);
  505.                     EDMA_RSETH(chan->hRld[offset + 1], DST, 
  506.                         chan->nextViop->frame.iFrm.y2);
  507.                     EDMA_RSETH(chan->hRld[4 + offset], DST, 
  508.                         chan->nextViop->frame.iFrm.cb1);     
  509.                     EDMA_RSETH(chan->hRld[5 + offset], DST, 
  510.                         chan->nextViop->frame.iFrm.cb2);                         
  511.                     EDMA_RSETH(chan->hRld[8 + offset], DST, 
  512.                         chan->nextViop->frame.iFrm.cr1);     
  513.                     EDMA_RSETH(chan->hRld[9 + offset], DST, 
  514.                         chan->nextViop->frame.iFrm.cr2);                         
  515.                 }else {
  516.                     EDMA_RSETH(chan->hRld[offset], DST, 
  517.                         chan->nextViop->frame.iFrm.y1);
  518.                     EDMA_RSETH(chan->hRld[offset + 4], DST, 
  519.                         chan->nextViop->frame.iFrm.cb1);
  520.                     EDMA_RSETH(chan->hRld[offset + 8], DST, 
  521.                         chan->nextViop->frame.iFrm.cr1);
  522.                 }/* if(chan->mergeFlds) {*/
  525.             }    
  526.         }
  527.     }
  528. }
  531. /*
  532.  *  ======== _configCh ========
  533.  *  configure video port channel settings
  534.  */
  535. static Int _configCh(
  536.         Ptr                 chanp, 
  537.         VPORTCAP_Params  *params
  538.         )
  539. {
  540.     _VPORT_ChanObj* chan= (_VPORT_ChanObj *)chanp;
  541.     volatile Int vpCtl, vcCtl, fld1Strt, fld2Strt, fld1Stop, fld2Stop;
  542.     volatile Int* base = (volatile Int *)chan->base;                         
  543.     Int retVal = IOM_COMPLETED;
  544.     Int numPixels, numLines, numCPixels;  
  545.     
  546.     
  547.     if(chan->status & _VPORT_OPENED) {
  548.         /* configure channel A capture settings  */
  549.         vcCtl = VP_VCACTL_RMK(0,1,0,params->fldInv, 
  550.             params->extCtl, params->fldDect, params->vCtRst,
  551.             params->hCtRst, 0, params->bpk10Bit, 0, 0, 
  552.             params->resmpl,params->scale,1,
  553.             ((params->fldOp & 4) >> 2), 
  554.             ((params->fldOp & 2) >> 1), 
  555.             (params->fldOp & 1), 
  556.             params->cmode);
  558.         fld1Strt = params->fldXStrt1 + (params->fldYStrt1 << 16);
  559.         fld1Stop = params->fldXStop1 + (params->fldYStop1 << 16);
  560.         fld2Strt = params->fldXStrt2 + (params->fldYStrt2 << 16);
  561.         fld2Stop = params->fldXStop2 + (params->fldYStop2 << 16);
  562.         if(params->fldOp == VPORT_FLDOP_FRAME) {
  563.             assert(params->fldXStop1 == params->fldXStop2);
  564.             assert(params->fldXStrt1 == params->fldXStrt2);
  565.         }   
  566.         base[_VP_VCACTL_OFFSETA]   = vcCtl;
  567.         base[_VP_VCASTRT1_OFFSETA] = fld1Strt;
  568.         base[_VP_VCASTOP1_OFFSETA] = fld1Stop;
  569.         base[_VP_VCASTRT2_OFFSETA] = fld2Strt;
  570.         base[_VP_VCASTOP2_OFFSETA] = fld2Stop;
  571.         numPixels = params->fldXStop1 - params->fldXStrt1 + 1;/* line size */
  572.         numLines = 0;
  573.         
  574.         if(params->fldOp != VPORT_FLDOP_FLD2){
  575.             numLines += params->fldYStop1 - params->fldYStrt1 + 1;
  576.         }
  577.         chan->numLinesFld1 = numLines;
  578.         
  579.         if(params->fldOp == VPORT_FLDOP_FLD2
  580.           || params->fldOp == VPORT_FLDOP_FRAME){
  581.             numLines += params->fldYStop2 - params->fldYStrt2 + 1;
  582.         }
  583.         chan->resmpl = params->resmpl;
  584.         chan->scale = params->scale;
  585.         chan->numLines = numLines;
  586.         numPixels >>= params->scale;
  587.         numCPixels = numPixels >> 1;
  588.         /* set both field1 and field2 threshold to the line size */
  589.         chan->numPixels = numPixels;
  590.         chan->lastLineNum = chan->numLines;        
  591.         if(params->cmode & _VPORT_MASK_10BIT){
  592.             /* 10-bit BT.656 or 20-bit Y/C mode */
  593.             if( params->bpk10Bit == VPORTCAP_BPK_10BIT_ZERO_EXTENDED
  594.              || params->bpk10Bit == VPORTCAP_BPK_10BIT_SIGN_EXTENDED){
  595.                 chan->yPitch = (numPixels * 2 + 7) & (~ 7);
  596.                 chan->cPitch = (numCPixels * 2 + 7) & (~ 7);
  597.             }else {
  598.                 chan->yPitch = (numPixels * 4 / 3 + 7) & (~ 7);
  599.                 chan->cPitch = (numCPixels* 4 / 3 + 7) & (~ 7);
  600.             }
  601.         } else {/* 8-bit BT.656 or 16-bit Y/C mode */
  602.             chan->yPitch = (numPixels + 7) & (~ 7);
  603.             chan->cPitch = (numCPixels + 7) & (~ 7);
  604.         }     
  605.         chan->yThrld = params->thrld;
  606.         if(params->mergeFlds && params->fldOp == VPORT_FLDOP_FRAME) { 
  607.             /* merge field comments */
  608.             /* frame capture and merge 2 fields into one frame */
  609.             /* set threshold is same as line size */
  610.             chan->yThrld = chan->yPitch >> 3;
  611.             chan->numEventsFld1 = chan->numLinesFld1;
  612.             chan->numEvents = chan->numLines;
  613.             chan->mergeFlds = TRUE;  
  614.         }else {            
  615.             assert(((chan->yPitch*chan->numLinesFld1) / (chan->yThrld << 3)) 
  616.                 *(chan->yThrld << 3) == (chan->yPitch * chan->numLinesFld1));
  617.             assert(((chan->yPitch * chan->numLines) / (chan->yThrld << 3)) 
  618.                 *(chan->yThrld << 3) == (chan->yPitch * chan->numLines));
  619.             chan->numEventsFld1 = 
  620.                 chan->yPitch * chan->numLinesFld1 / (chan->yThrld << 3);
  621.             chan->numEvents = 
  622.                 chan->yPitch * chan->numLines / (chan->yThrld << 3);
  623.             chan->mergeFlds = FALSE;
  624.         }            
  626.         chan->cThrld = (chan->yThrld + 1) >> 1;
  628.         base[_VP_VCATHRLD_OFFSETA] = VP_VCATHRLD_RMK(chan->yThrld,chan->yThrld);
  629.         base[_VP_VCAEVTCT_OFFSETA] = VP_VCAEVTCT_RMK(
  630.             (chan->numEvents-chan->numEventsFld1), chan->numEventsFld1 );  
  631.         
  632.         chan->status|=_VPORT_CFGED;
  633.         retVal = IOM_COMPLETED;
  634.     }    
  635.     return retVal;
  637. }
  640. /*
  641.  *  ======== _configChan ========
  642.  *  configure channel settings
  643.  */
  644. static Int _configChan(Ptr chanp, Ptr args)
  645. {
  646.     VPORTCAP_Params*   params = (VPORTCAP_Params*)args; 
  647.     
  648.     
  649.     /* configure video port channel A/B control register */
  650.     _configCh(chanp, params);
  652.     /* configure EDMA and frame buffer */
  653.     _configTransfer(chanp, params);
  654.     return IOM_COMPLETED;
  655. }
  658. /*
  659.  *  ======== _configPort ========
  660.  *  configure port level registers
  661.  */
  662. static Int _configPort(Ptr chanp, Ptr args)
  663. {
  664.     PortObj* port = (PortObj *)chanp;
  665.     volatile Int *base = (volatile Int *)port->base; 
  666.     /* configure video port control register */
  667.     VPORT_PortParams* portParams = (VPORT_PortParams*)args; 
  668.     
  669.     
  670.     /* enable video port */
  671.     base[_VP_PCR_OFFSET] |= VP_PCR_PEREN_ENABLE << _VP_PCR_PEREN_SHIFT;
  672.                 
  673.     /* reset video port */
  674.     base[_VP_VPCTL_OFFSET] |= 
  675.         VP_VPCTL_VPRST_RESET << _VP_VPCTL_VPRST_SHIFT;
  677.     base[_VP_VPCTL_OFFSET] = VP_VPCTL_RMK(0,0,0,portParams->vc3Polarity,
  678.         portParams->vc2Polarity,portParams->vc1Polarity,0,0,
  679.         portParams->dualChanEnable);
  680.     
  681.     /* enable video port */
  682.     base[_VP_VPCTL_OFFSET] |= (VP_VPCTL_VPHLT_CLEAR << _VP_VPCTL_VPHLT_SHIFT);
  683.     port->chanObj[0].edcFxns = portParams->edcTbl[0];
  684.     port->chanObj[1].edcFxns = portParams->edcTbl[1];
  685.     
  686.     IRQ_clear(IRQ_EVT_EDMAINT);
  687.     return IOM_COMPLETED;
  689. }
  692. /*
  693.  *  ======== _configTransfer ========
  694.  *  configure channel EDMA settings
  695.  */
  696. static Int _configTransfer(
  697.         Ptr                 chanp, 
  698.         VPORTCAP_Params  *params
  699.         )
  700. {
  701.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  702.     Int i;
  703.     EDMA_Config  cfgEdma;
  704.     Int thrld;
  705.     Int8* curAddr;
  706.     
  707.     if(chan->status & _VPORT_CFGED) {
  708.      
  709.         assert(params->numFrmBufs >= 2 && params->numFrmBufs 
  710.                 <= VPORT_MAX_NUM_FRMBUFS);
  711.         QUE_new(&chan->qIn);     
  712.         chan->queEmpty = FALSE;   
  713.         chan->mrViop = INV;
  714.         chan->packetIOM = INV;     
  715.         chan->segId = params->segId;
  716.         
  717.         EDMA_intDisable(chan->tcc[0]);
  718.         EDMA_intDisable(chan->tcc[1]);
  719.         
  720.         if(chan->numFrms == 0) {
  721.             chan->numFrms = params->numFrmBufs;
  723.             /* allocate frame buffer */
  724.             chan->bufSz = chan->yPitch * chan->numLines 
  725.                   + chan->cPitch * chan->numLines * 2;
  726.             for(i = 0; i < chan->numFrms; i ++) {                    
  727.                 if((curAddr = MEM_calloc(params->segId,chan->bufSz, 
  728.                     params->alignment)) == MEM_ILLEGAL){
  729.                     return IOM_EALLOC;
  730.                 }    
  731.                 /* field 1 */
  732.                 chan->viops[i].frame.iFrm.y1 = curAddr;
  733.                 curAddr += chan->numLines*chan->yPitch;
  734.                 chan->viops[i].frame.iFrm.cb1 = curAddr;
  735.                 curAddr += chan->numLines*chan->cPitch;
  736.                 chan->viops[i].frame.iFrm.cr1 = curAddr;
  737.                 curAddr += chan->numLines*chan->cPitch;
  738.                 /* field 2 */    
  739.                 if(params->fldOp == VPORT_FLDOP_FLD2) {
  740.                     chan->viops[i].frame.iFrm.y2 = 
  741.                         chan->viops[i].frame.iFrm.y1;
  742.                     chan->viops[i].frame.iFrm.cb2 = 
  743.                         chan->viops[i].frame.iFrm.cb1;
  744.                     chan->viops[i].frame.iFrm.cr2 = 
  745.                         chan->viops[i].frame.iFrm.cr1;
  746.                 }
  747.                 else if(! chan->mergeFlds) {
  748.                     chan->viops[i].frame.iFrm.y2 = 
  749.                       chan->viops[i].frame.iFrm.y1
  750.                         + chan->numLinesFld1*chan->yPitch;
  751.                     chan->viops[i].frame.iFrm.cb2 = 
  752.                       chan->viops[i].frame.iFrm.cb1
  753.                         + (chan->numLinesFld1*chan->cPitch);
  754.                     chan->viops[i].frame.iFrm.cr2 = 
  755.                       chan->viops[i].frame.iFrm.cr1
  756.                         + (chan->numLinesFld1*chan->cPitch);
  757.                 }else {
  758.                     chan->viops[i].frame.iFrm.y2 = 
  759.                       chan->viops[i].frame.iFrm.y1 + chan->yPitch;
  760.                     chan->viops[i].frame.iFrm.cb2 = 
  761.                       chan->viops[i].frame.iFrm.cb1 + chan->cPitch;
  762.                     chan->viops[i].frame.iFrm.cr2 = 
  763.                       chan->viops[i].frame.iFrm.cr1 + chan->cPitch;            
  764.                 }    
  765.                 if(i > 1) {
  766.                     /* don't put the first 2 viop into the queue */
  767.                     QUE_enqueue(&chan->qIn, (QUE_Handle)&chan->viops[i]);
  768.                 }
  770.             }
  771.         }    
  772.         CACHE_clean(CACHE_L2ALL, 0, 0);
  773.         chan->curViop = &chan->viops[0];
  774.         chan->nextViop = &chan->viops[1]; 
  775.         for(i = 0; i < _VPORT_NUM_EDMA_CHANS; i ++) {
  776.             Int optFld1 = EDMA_OPT_RMK(
  777.                 params->edmaPri,
  778.                 EDMA_OPT_ESIZE_32BIT,
  779.                 EDMA_OPT_2DS_NO,
  780.                 EDMA_OPT_SUM_NONE,
  781.                 EDMA_OPT_2DD_YES,
  782.                 EDMA_OPT_DUM_INC,
  783.                 EDMA_OPT_TCINT_NO,
  784.                 EDMA_OPT_TCC_OF(0), 
  785.                 EDMA_OPT_TCCM_OF(0),
  786.                 EDMA_OPT_ATCINT_NO,    
  787.                 EDMA_OPT_ATCC_DEFAULT,
  788.                 EDMA_OPT_PDTS_DISABLE,
  789.                 EDMA_OPT_PDTD_DISABLE,
  790.                 EDMA_OPT_LINK_YES,
  791.                 EDMA_OPT_FS_NO
  792.             );
  793.     
  794.             Int optFld2a = EDMA_OPT_RMK(
  795.                 params->edmaPri,
  796.                 EDMA_OPT_ESIZE_32BIT,
  797.                 EDMA_OPT_2DS_NO,
  798.                 EDMA_OPT_SUM_NONE,
  799.                 EDMA_OPT_2DD_YES,
  800.                 EDMA_OPT_DUM_INC,
  801.                 (i == 0 ? EDMA_OPT_TCINT_YES:EDMA_OPT_TCINT_NO),
  802.                 EDMA_OPT_TCC_OF(i == 0 ? chan->tcc[0] & 0x0f : 0), 
  803.                 EDMA_OPT_TCCM_OF(i == 0 ? chan->tcc[0] >> 4 : 0),
  804.                 EDMA_OPT_ATCINT_NO,    
  805.                 EDMA_OPT_ATCC_DEFAULT,
  806.                 EDMA_OPT_PDTS_DISABLE,
  807.                 EDMA_OPT_PDTD_DISABLE,
  808.                 EDMA_OPT_LINK_YES,
  809.                 EDMA_OPT_FS_NO
  810.             );
  811.             Int optFld2b = EDMA_OPT_RMK(
  812.                 params->edmaPri,
  813.                 EDMA_OPT_ESIZE_32BIT,
  814.                 EDMA_OPT_2DS_NO,
  815.                 EDMA_OPT_SUM_NONE,
  816.                 EDMA_OPT_2DD_YES,
  817.                 EDMA_OPT_DUM_INC,
  818.                 (i == 0 ? EDMA_OPT_TCINT_YES:EDMA_OPT_TCINT_NO),
  819.                 EDMA_OPT_TCC_OF(i == 0 ? chan->tcc[1] & 0x0f : 0), 
  820.                 EDMA_OPT_TCCM_OF(i == 0 ? chan->tcc[1] >> 4 : 0),
  821.                 EDMA_OPT_ATCINT_NO,    
  822.                 EDMA_OPT_ATCC_DEFAULT,
  823.                 EDMA_OPT_PDTS_DISABLE,
  824.                 EDMA_OPT_PDTD_DISABLE,
  825.                 EDMA_OPT_LINK_YES,
  826.                 EDMA_OPT_FS_NO
  827.             );
  829.             thrld = (i == 0) ? chan->yThrld : chan->cThrld;
  830.             cfgEdma.src = EDMA_SRC_RMK(chan->edmaAddr[i]);
  831.             if(chan->mergeFlds) {
  832.                 /* to merge the two fields together */
  833.                 /* EDMA is configured to transfer only field 1 initially */
  834.                 /* line pitch is twice the line size */
  835.                 /* this requires that the threlhold is the same as line size */
  836.                 
  837.                 /* first field */
  838.                 cfgEdma.cnt = 
  839.                   EDMA_CNT_RMK((chan->numEventsFld1) - 1, (thrld << 1));
  840.                 cfgEdma.idx = EDMA_IDX_RMK(thrld << 4, 0);
  841.     
  842.                 /* hard code the first two frames as current and reload buffers */                
  843.                 /* first field */
  844.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i + 1]);
  845.                 cfgEdma.opt = optFld1;
  846.                 cfgEdma.dst = 
  847.                   EDMA_DST_RMK(*((Int *)(&chan->viops[0].frame.iFrm.y1) + i));
  848.                 EDMA_config(chan->hEdma[i], &cfgEdma);
  849.                 EDMA_config(chan->hRld[4 * i], &cfgEdma); 
  850.                 cfgEdma.dst = 
  851.                   EDMA_DST_RMK(*((Int *)(&chan->viops[1].frame.iFrm.y1) + i));
  852.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i + 3]);
  853.                 EDMA_config(chan->hRld[4 * i + 2], &cfgEdma);
  855.                 /* second field */
  856.                 cfgEdma.opt = optFld2a;
  857.                 cfgEdma.cnt = 
  858.                   EDMA_CNT_RMK((chan->numEvents-chan->numEventsFld1) - 1, 
  859.                    (thrld << 1));
  860.                 cfgEdma.dst = 
  861.                   EDMA_DST_RMK(*((Int *)(&chan->viops[0].frame.iFrm.y2) + i));
  862.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i + 2]);
  863.                 EDMA_config(chan->hRld[4 * i + 1], &cfgEdma); 
  864.                 cfgEdma.opt = optFld2b;
  865.                 cfgEdma.dst = 
  866.                   EDMA_DST_RMK(*((Int *)(&chan->viops[1].frame.iFrm.y2) + i));
  867.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i]);
  868.                 EDMA_config(chan->hRld[4 * i + 3], &cfgEdma);
  869.                 
  870.             }else {/* if fields are not merged, configure EDMA to transfer */
  871.                    /* for both field1 and field 2                          */
  872.                    /* the line pitch is just the line size                 */
  873.                 cfgEdma.opt = optFld2a;
  874.                 cfgEdma.cnt = EDMA_CNT_RMK((chan->numEvents) - 1, (thrld << 1));
  875.                 cfgEdma.idx = EDMA_IDX_RMK(thrld << 3, 0);
  876.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i + 2]);
  877.                 /* hard code the first and second frame buffer as current  */
  878.                 /* and reload buffers */
  879.                 cfgEdma.dst = EDMA_DST_RMK(
  880.                     *((Int *)(&chan->viops[0].frame.iFrm.y1) + i));
  881.                 EDMA_config(chan->hEdma[i], &cfgEdma);
  882.                 EDMA_config(chan->hRld[4 * i], &cfgEdma);
  884.                 cfgEdma.opt = optFld2b;
  885.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i]);
  886.                 cfgEdma.dst = EDMA_DST_RMK(
  887.                     *((Int *)(&chan->viops[1].frame.iFrm.y1) + i));
  888.                 EDMA_config(chan->hRld[4 * i + 2], &cfgEdma);
  889.             }
  890.         }
  891.         chan->nextEDMARlds = 1;        
  892.         /* enable EDMA channel */
  893.         /*
  894.          * The EDMA interrupt dispatcher will be called by the
  895.          * BIOS HWI interrupt dispatcher.
  896.          */
  897.         IRQ_map(IRQ_EVT_EDMAINT, params->irqId);
  898.         HWI_dispatchPlug(params->irqId, (Fxn)EDMA_intDispatcher, -1, NULL);
  899.         
  900.         EDMA_intClear(chan->tcc[0]);
  901.         EDMA_intHook(chan->tcc[0], captureEdmaISR);       
  902.         EDMA_intEnable(chan->tcc[0]);
  903.         EDMA_intClear(chan->tcc[1]);
  904.         EDMA_intHook(chan->tcc[1], captureEdmaISR);       
  905.         EDMA_intEnable(chan->tcc[1]);
  906.         for(i = 0; i < _VPORT_NUM_EDMA_CHANS; i ++) {
  907.             EDMA_disableChannel(chan->hEdma[i]);
  908.             EDMA_clearChannel(chan->hEdma[i]);
  909.             EDMA_enableChannel(chan->hEdma[i]);
  910.         }    
  911.         chan->status |= _VPORT_READY;
  912.         IRQ_enable(IRQ_EVT_EDMAINT);
  913.         
  914.     }   
  915.     return IOM_COMPLETED;
  917. }
  919. /*
  920.  *  ======== _covrRecover ========
  921.  *  force recover from FIFO over-run
  922.  */
  923. static Int _covrRecover(Ptr chanp)
  924. {
  925.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  926.     PortObj* port = &portObjs[chan->portNum];
  927.     volatile Int *base = (volatile Int *)port->base;
  928.     volatile Int *cbase = (volatile Int *)chan->base;    
  929.     Int numEvents;
  930.     volatile Int i;                                            
  931.     
  932.     
  933.     /* disable over-run interrupt */
  934.     base[_VP_VPIE_OFFSET] &= ~(_VP_VPIE_COVRA_MASK<<(chan->chanNum*16));
  935.     /* block capture events */
  936.     cbase[_VP_VCACTL_OFFSETA] |= _VP_VCACTL_BLKCAP_MASK;
  938.     /* Disable the edmas before settings them up */
  939.     EDMA_intDisable(chan->tcc[0]);
  940.     EDMA_intDisable(chan->tcc[1]);
  941.     for(i = 0; i < _VPORT_NUM_EDMA_CHANS; i ++) {
  942.         EDMA_disableChannel(chan->hEdma[i]);
  943.         EDMA_clearChannel(chan->hEdma[i]);
  944.     }
  945.     if(chan->mergeFlds) {
  946.         numEvents = chan->numEventsFld1;        
  947.     } else {
  948.         numEvents = chan->numEvents;
  949.     }
  951.     /* set up DMA parameters again */
  952.     EDMA_RSETH(chan->hEdma[0], DST, chan->curViop->frame.iFrm.y1);
  953.     EDMA_RSETH(chan->hEdma[1], DST, chan->curViop->frame.iFrm.cb1);
  954.     EDMA_RSETH(chan->hEdma[2], DST, chan->curViop->frame.iFrm.cr1);
  955.     EDMA_RSETH(chan->hEdma[0], CNT, EDMA_CNT_RMK(numEvents - 1, 
  956.         (chan->yThrld << 1)));
  957.     EDMA_RSETH(chan->hEdma[1], CNT, EDMA_CNT_RMK(numEvents - 1, 
  958.         (chan->cThrld << 1)));
  959.     EDMA_RSETH(chan->hEdma[2], CNT, EDMA_CNT_RMK(numEvents - 1, 
  960.         (chan->cThrld<<1)));
  962.     /* enable the edma events again before settings them up */
  963.     EDMA_intEnable(chan->tcc[0]);
  964.     EDMA_intEnable(chan->tcc[1]);
  965.     for(i = 0;i < 3;i ++) {
  966.         EDMA_enableChannel(chan->hEdma[i]);
  967.     }
  968.     /* delay */
  969.     for(i = 0; i < 100000; i ++);
  971.     /* clear any pending over-run interrupt */
  972.     if(chan->chanNum == 0) {
  973.         base[_VP_VPIS_OFFSET] |= _VP_VPIS_COVRA_MASK;
  974.     }else {
  975.         base[_VP_VPIS_OFFSET] |= _VP_VPIS_COVRB_MASK;
  976.     }    
  977.     /* enable event generation */
  978.     cbase[_VP_VCACTL_OFFSETA] &= ~(_VP_VCACTL_BLKCAP_MASK);
  980.     /* enable over-run interrupt */
  981.     base[_VP_VPIE_OFFSET] |= _VP_VPIE_COVRA_MASK << (chan->chanNum * 16);
  983.     return IOM_COMPLETED;
  984. }
  987. /*
  988.  *  ======== _setVIntCb ========
  989.  *  setup video port interrupt call-back
  990.  */
  991. static Int _setVIntCb(Ptr chanp, Ptr args)
  992. {      
  993.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  994.     PortObj* port = &portObjs[chan->portNum];
  995.     volatile Int *base = (volatile Int *)port->base;
  996.     volatile Int *cBase = (volatile Int *)chan->base;
  997.     VPORT_VIntCbParams* vIntCbParams = (void *)args;
  998.     Int mask = vIntCbParams->vIntMask;
  999.     Uns vif2 = 0, vInt2 = 0, vif1 = 0, vInt1 = 0, fscl2 = 0;
  1000.     
  1001.     
  1002.     /* check to see if vertical interrupt is enabled */
  1003.     if(mask & VPORT_INT_VINT1) {
  1004.         vif1 = 1;
  1005.         vInt1 = vIntCbParams->vIntLine;
  1006.     }
  1007.     if(mask & VPORT_INT_VINT2) {
  1008.         vif2 = 1;
  1009.         vInt2 = vIntCbParams->vIntLine;    
  1010.     }
  1011.     fscl2 = vif2 & (~ vif1);
  1012.     /* setup vertical interrupt */
  1013.     cBase[_VP_VCAVINT_OFFSETA] = VP_VCAVINT_RMK(vif2,fscl2, 
  1014.         vInt2, vif1, vInt1);
  1015.     
  1016.     if(chan->chanNum == 1) {
  1017.         mask <<= 16;    /* channel B */
  1018.     }
  1019.     chan->vIntMask = mask;
  1020.     if(mask) {
  1021.         mask |= 1; /* turn on video port interrupt */
  1022.         IRQ_map(IRQ_EVT_VINT0 + chan->portNum, vIntCbParams->irqId);    
  1023.         HWI_dispatchPlug(vIntCbParams->irqId, (Fxn)captureISR, -1, NULL);
  1024.         IRQ_disable(IRQ_EVT_VINT0 + chan->portNum);
  1025.         IRQ_clear(IRQ_EVT_VINT0 + chan->portNum);
  1026.     }
  1027.     base[_VP_VPIE_OFFSET] |= mask;  /* register write */    
  1028.     chan->vIntFxn = vIntCbParams->vIntCbFxn;    
  1029.     chan->vIntCbArg = vIntCbParams->cbArg;
  1030.     return IOM_COMPLETED;   
  1031. }      
  1032. static void _delay(Int delayTime)
  1033. {
  1034.     asm("loop1: BDEC loop1, A4");
  1035.     asm(" NOP 5");
  1037. }
  1039. /*
  1040.  *  ======== _startVPCapture ========
  1041.  *  start video port capture operation
  1042.  */
  1043. static Int _startVPCapture(Ptr chanp)
  1044. {
  1045.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  1046.     PortObj* port = &portObjs[chan->portNum];
  1047.     volatile Int *base = (volatile Int *)port->base;
  1048.     volatile Int *cbase = (volatile Int *)chan->base;    
  1050.     /* enable channel */
  1051.     cbase[_VP_VCACTL_OFFSETA] |= VP_VCACTL_VCEN_ENABLE << _VP_VCACTL_VCEN_SHIFT;
  1053.     _delay(20000000);
  1054.     /* clear the block capture event mask bit to enable */
  1055.     /* generating capture events                        */
  1056.     cbase[_VP_VCACTL_OFFSETA] &= ~ (_VP_VCACTL_BLKCAP_MASK);
  1058.     /* enable interrupt generation in video port level */
  1059.     base[_VP_VPIE_OFFSET] |= VP_VPIE_VIE_ENABLE << _VP_VPIE_VIE_SHIFT;
  1060.     base[_VP_VPIS_OFFSET] |= 0XFFFFFFFF;
  1061.     /* clear any pending video port interrupt */
  1062.     IRQ_clear(IRQ_EVT_VINT0 + chan->portNum);
  1063.     /* enable corresponding video port interrupt in chip-level*/
  1064.     IRQ_enable(IRQ_EVT_VINT0 + chan->portNum);
  1065.     
  1066.     return IOM_COMPLETED;
  1067. }
  1069. /*
  1070.  *  ======== _stopVPCapture ========
  1071.  *  stop video port capture operation
  1072.  */
  1073. static Int _stopVPCapture(Ptr chanp)
  1074. {
  1075.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  1076.     PortObj* port = &portObjs[chan->portNum];
  1077.     volatile Int *cbase = (volatile Int *)chan->base;    
  1078.     volatile Int *base = (volatile Int *)port->base;
  1080.     /* block events generation */
  1081.     cbase[_VP_VCACTL_OFFSETA] &= (_VP_VCACTL_BLKCAP_MASK);
  1083.     /* disable channel */
  1084.     cbase[_VP_VCACTL_OFFSETA] &= 
  1085.         ~ (VP_VCACTL_VCEN_ENABLE << _VP_VCACTL_VCEN_SHIFT);
  1087.     /* disable interrupt generation in video port level */
  1088.     base[_VP_VPIE_OFFSET] &= ~ (VP_VPIE_VIE_ENABLE << _VP_VPIE_VIE_SHIFT);
  1089.     base[_VP_VPIS_OFFSET] |= 0XFFFFFFFF;
  1090.     
  1091.     /* disble corresponding video port interrupt in chip-level*/
  1092.     IRQ_disable(IRQ_EVT_VINT0 + chan->portNum);
  1094.     /* clear any pending video port interrupt */
  1095.     IRQ_clear(IRQ_EVT_VINT0 + chan->portNum);
  1096.     
  1097.     EDMA_intDisable(chan->tcc[0]);
  1098.     EDMA_intClear(chan->tcc[0]);
  1100.     EDMA_intDisable(chan->tcc[1]);
  1101.     EDMA_intClear(chan->tcc[1]);
  1103.     return IOM_COMPLETED;
  1104. }
  1108. /*
  1109.  *  ======== captureISR ========
  1110.  */
  1111. static void captureISR(Int portNum)
  1112. {
  1113.     volatile Int *base =  
  1114.         (volatile Int *)portObjs[portNum].base;
  1115.     Int vpis = base[_VP_VPIS_OFFSET];
  1116.     Int mask = vpis;
  1117.     _VPORT_ChanObj* chanObjs = portObjs[portNum].chanObj;
  1118.         
  1119.     if(vpis & chanObjs[0].vIntMask && chanObjs[0].vIntFxn != INV) {
  1120.         chanObjs[0].vIntFxn(chanObjs[0].vIntCbArg, vpis);
  1121.         mask &=  chanObjs[0].vIntMask;
  1122.     }else if(vpis & chanObjs[1].vIntMask && chanObjs[1].vIntFxn != INV) {
  1123.         chanObjs[1].vIntFxn(chanObjs[1].vIntCbArg, (vpis >> 16));
  1124.         mask &=  chanObjs[1].vIntMask;
  1125.     }
  1126.     /* clear interrupts that has been handled */
  1127.     base[_VP_VPIS_OFFSET] |= mask;
  1128. }