开通博客赚积分
发布资源赚积分
分类

源码开发语言/平台
当前位置：首页 > 源码/资料 > 嵌入式/单片机编程 > DSP编程 > 查看源码
vportdis.c
资源名称：DSP-C6000-DM642DEMO.rar　[点击查看]
上传用户：dahaojd
上传日期：2008-01-29
资源大小：14357k
文件大小：42k
源码类别：

DSP编程

开发平台：

C/C++

vportdis.c：源码内容
  1. /*
  2.  *  Copyright 2003 by Texas Instruments Incorporated.
  3.  *  All rights reserved. Property of Texas Instruments Incorporated.
  4.  *  Restricted rights to use, duplicate or disclose this code are
  5.  *  granted through contract.
  6.  *  
  7.  */
  8. /* "@(#) DDK 1.10.00.23 07-02-03 (ddk-b12)" */
  9. /* DSP/BIOS standard include files */
  10. #include <std.h>
  11. #include <mem.h>
  12. #include <que.h>    
  13. #include <tsk.h>
  15. /* Chip-support library include files */
  16. #include <csl.h>
  17. #include <csl_edma.h>
  18. #include <csl_vphal.h>         
  19. #include <csl_irq.h>
  20. #include <csl_cache.h>
  21. #include <csl_dat.h>
  23. /* IOM/GIO driver model include files */
  24. #include <iom.h>
  25. #include <fvid.h>                       
  27. /* video driver specif-ic include files */
  28. #include <vport.h>
  29. #include <vportdis.h>
  30. #include <edc.h>
  31. #include "_vport.h"
  33. /* debug include files */
  34. /* to minimize code size and cycle count overhead of the driver */             
  35. /* error checking is only performed at debug time               */
  36. #include <assert.h>
  39. /* mini-driver API functions */
  40. static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams);
  41. static Int mdControlChan(Ptr chanp, Uns cmd, Ptr args);
  42. static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
  43.         Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg);
  44. static Int mdDeleteChan(Ptr chanp);
  45. static Int mdSubmitChan(Ptr chanp, IOM_Packet *packet);
  48. /* local functions */
  49. static Int _configChan(Ptr chanp, Ptr args);
  50. static Int _configEDMA(Ptr chanp, VPORTDIS_Params *params);
  51. static Int _configPort(Ptr chanp, Ptr args);
  52. static Int _configRegs(Ptr chanp, VPORTDIS_Params *params);
  53. static void displayEdmaISR(Int tcc);
  54. static void displayISR(int portNum);
  55. static Int _displayStart(Ptr chanp);
  56. static Int _displayStop(Ptr chanp);
  57. static Int _dundRecover(Ptr chanp);
  58. static Int _getlastActiveLine(VPORTDIS_Params* params);
  59. static Int _setVIntCb(Ptr chanp, Ptr args);
  62. /* global and static variables */
  63. IOM_Fxns VPORTDIS_Fxns = {
  64.     mdBindDev,    
  65.     (IOM_TmdUnBindDev)IOM_mdNotImpl,
  66.     mdControlChan,
  67.     mdCreateChan,
  68.     mdDeleteChan,
  69.     mdSubmitChan
  70. };
  72. /**************************************************************
  73.  * Static allocation and initialization of port objects       *
  74.  * as display supports only 1 channel, the same channel       *
  75.  * object for capture is used here for the whoel port         *
  76.  **************************************************************/
  77. _VPORT_ChanObj chanObjs[_VP_PORT_CNT] = {
  78.     {0, 0, 0, _VP_BASE_PORT0, EDMA_CHA_VP0EVTYA, EDMA_CHA_VP0EVTUA, 
  79.         EDMA_CHA_VP0EVTVA, _VP_YDSTA0_ADDR, _VP_CBDST0_ADDR, _VP_CRDST0_ADDR}, 
  80.     {0, 1, 0, _VP_BASE_PORT1, EDMA_CHA_VP1EVTYA, EDMA_CHA_VP1EVTUA, 
  81.         EDMA_CHA_VP1EVTVA,  _VP_YDSTA1_ADDR, _VP_CBDST1_ADDR, _VP_CRDST1_ADDR}, 
  82.     {0, 2, 0, _VP_BASE_PORT2, EDMA_CHA_VP2EVTYA, EDMA_CHA_VP2EVTUA, 
  83.         EDMA_CHA_VP2EVTVA, _VP_YDSTA2_ADDR, _VP_CBDST2_ADDR, _VP_CRDST2_ADDR },
  84. };     
  88. /*
  89.  *  ======== mdBindDev ========
  90.  *  Register all external devices to video port display driver 
  91.  */
  92. static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams)
  93. {
  94.    Int portNum = devid;
  95.    volatile Int i;
  96.    volatile Int* base = (volatile Int *)chanObjs[portNum].base;                       
  97.    
  98.    assert(portNum < _VP_PORT_CNT);
  99.    base[_VP_VPCTL_OFFSET] = 
  100.              VP_VPCTL_VPRST_RESET << _VP_VPCTL_VPRST_SHIFT;
  101.    for(i = 0; i < 100000; i ++);      
  102.     *devp = &chanObjs[portNum];                                                                                           
  103.    return mdControlChan(&chanObjs[portNum], 
  104.            VPORT_CMD_CONFIG_PORT, devParams);
  105. }
  108. /*
  109.  *  ======== mdControlChan ========
  110.  */
  111. static Int mdControlChan(Ptr chanp, Uns cmd, Ptr args)
  112. {
  113.     Int retVal = IOM_COMPLETED;
  114.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  115.     
  116.     /* command dispatcher */
  117.     switch (cmd){
  118.         case VPORT_CMD_START:
  119.         retVal = _displayStart(chanp);
  120.         break;
  121.         case VPORT_CMD_STOP:
  122.         retVal = _displayStop(chanp);
  123.         break;
  124.         case VPORT_CMD_CONFIG_CHAN:
  125.         retVal = _configChan(chanp, args);
  126.         break;
  127.         
  128.         case VPORT_CMD_SET_VINTCB:
  129.         _setVIntCb(chanp, args);
  130.         break;
  131.         case VPORT_CMD_DUND_RECOVER:
  132.         retVal = _dundRecover(chanp);
  133.         break;
  134.         case VPORT_CMD_CONFIG_PORT:
  135.         retVal = _configPort(chanp, args);
  136.         break;
  137.         default:
  138.         if(chan->edcFxns!=INV) {
  139.             retVal =  chan->edcFxns->ctrl(chan->edcHandle, 
  140.                 cmd-VPORT_CMD_EDC_BASE,(Arg)args);
  141.         }else {
  142.             retVal = IOM_ENOTIMPL;
  143.         }
  144.    }    
  145.    return retVal;
  146. }              
  149. /*
  150.  *  ======== mdCreateChan ========
  151.  *  create a channel
  152.  */
  153. static Int  mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
  154.               Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg)
  155. {
  156.     _VPORT_ChanObj* chan;
  157.     Int retVal = IOM_COMPLETED;   
  158.     Int j;     
  160.     if(mode != IOM_OUTPUT){
  161.         return IOM_EBADARGS;
  162.     }
  163.     
  164.     chan = (_VPORT_ChanObj *)devp;
  165.     if(chan->edcFxns != INV) {
  166.         /* open external device */
  167.         chan->edcHandle 
  168.            = chan->edcFxns->open(name, (Arg)INV);
  169.     } 
  170.     if(! (chan->status & _VPORT_OPENED)) {
  171.         chan->status |= _VPORT_OPENED;
  172.         
  173.         chan->vIntMask = 0;
  174.         QUE_new(&chan->qIn);
  175.         QUE_new(&chan->qOut);
  176.         chan->cbFxn = cbFxn;
  177.         chan->vIntFxn = (VPORT_IntCallBack)INV;
  178.         chan->queEmpty = FALSE;   
  179.         chan->cbArg = (Arg)cbArg;
  180.         chan->packetIOM = INV;     
  181.         chan->vIntCbArg = (Int)INV;        
  182.         chan->bufSz = 0;
  184.         /* allocate EDMA PaRAM and RLD entries */
  185.         for(j = 0; j < _VPORT_NUM_EDMA_CHANS 
  186.           && retVal == IOM_COMPLETED; j ++ ) {
  187.             if((chan->hEdma[j] = 
  188.              EDMA_open(chan->edmaChanNum[j], EDMA_OPEN_RESET)) == EDMA_HINV
  189.              || (chan->hRld[4 * j] = EDMA_allocTable(-1)) == EDMA_HINV 
  190.              || (chan->hRld[4 * j + 1] =EDMA_allocTable(-1)) == EDMA_HINV 
  191.              || (chan->hRld[4 * j + 2] =EDMA_allocTable(-1)) == EDMA_HINV 
  192.              || (chan->hRld[4 * j + 3] =EDMA_allocTable(-1)) == EDMA_HINV 
  193.              ||  (chan->tcc[j] = EDMA_intAlloc(chan->edmaChanNum[j])) == -1){
  194.                 retVal = IOM_EALLOC;
  195.                 retVal = IOM_EALLOC;
  196.             }/* if((chan->...*/ 
  197.         }/* for(j = 0; j < NUM_EDMA_CHANS; j++) {...*/
  198.         
  199.         /* if EDMA resources are allocated successfully, go ahead */
  200.         /* and configure the channel                              */
  201.         if(retVal == IOM_COMPLETED && (void *)chanParams != INV) {
  202.             retVal = mdControlChan(chan, VPORT_CMD_CONFIG_CHAN, chanParams); 
  203.         }
  204.         if(! retVal) {
  205.              /* configured the channel successfully, return handle */
  206.              *chanp = chan;
  207.         }else {
  208.             /* failed, free all resources and return error */
  209.             mdDeleteChan(chan);
  210.             *chanp = INV;
  211.         }               
  212.     } /*if(!chan->opened) */
  213.     return retVal;
  214. }               
  216. /*
  217.  *  ======== mdDeleteChan ========
  218.  *  delete the channel
  219.  */
  221. static Int  mdDeleteChan(Ptr chanp)
  222. {
  223.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  224.     Int j;
  225.     volatile Int* base;
  226.     
  227.     if(chan->status & _VPORT_OPENED) {
  228.         chan->status = 0;
  229.         mdControlChan(chanp, VPORT_CMD_STOP, NULL);
  230.         for(j = 0; j < _VPORT_NUM_EDMA_CHANS; j ++) {
  231.             EDMA_disableChannel(chan->hEdma[j]);
  232.             EDMA_clearChannel(chan->hEdma[j]);
  233.             EDMA_close(chan->hEdma[j]);
  234.             EDMA_freeTable(chan->hRld[4 * j]);
  235.             EDMA_freeTable(chan->hRld[4 * j + 1]);
  236.             EDMA_freeTable(chan->hRld[4 * j + 2]);
  237.             EDMA_freeTable(chan->hRld[4 * j + 3]);
  238.             EDMA_intFree(chan->tcc[j]);
  239.         }      
  240.         
  241.         for(j = 0; j < chan->numFrms ; j ++) {
  242.             MEM_free(chan->segId, chan->viops[j].frame.iFrm.y1, chan->bufSz);
  243.         }        
  244.         
  245.         base = (volatile Int *)chan->base;
  246.         /* reset display */
  247.         base[_VP_VDCTL_OFFSET] |= 
  248.             VP_VDCTL_RSTCH_RESET << _VP_VDCTL_RSTCH_SHIFT;
  249.         /* reset video port */
  250.         base[_VP_VPCTL_OFFSET] |= 
  251.             VP_VPCTL_VPRST_RESET << _VP_VPCTL_VPRST_SHIFT;
  252.         
  253.         chan->status = 0;
  254.         /* close external device */
  255.         if(chan->edcFxns != INV) {
  256.             chan->edcFxns->close(chan->edcHandle);
  257.         }
  258.         
  259.     }    
  260.     return IOM_COMPLETED;
  261. }
  264. /*
  265.  *  ======== mdSubmitChan ========
  266.  */
  267. static Int  mdSubmitChan(Ptr chanp, IOM_Packet *packet)
  268. {
  270.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  271.     FVID_Frame* viop;                             
  272.     Int retVal = IOM_PENDING;
  273.     Uint32 gie = IRQ_globalDisable();     
  274.     
  275.     if(packet->cmd != FVID_ALLOC 
  276.         && packet->cmd != FVID_FREE 
  277.         && packet->cmd != FVID_EXCHANGE){        
  278.         /* other commands not supported */
  279.         return IOM_ENOTIMPL;    
  280.     }
  281.     
  282.     if(packet->cmd != FVID_ALLOC) {/* FVID_FREE or FVID_EXCHANGE */
  283.         viop = *(void **)packet->addr; /* pointer of a video I/O packet */
  284.         if(chan->queEmpty) {
  285.             /* check to make sure it is not to at the end of a frame */
  286.             /* to avoid any race condition                           */
  287.             volatile Int* base = (volatile Int *)chan->base;
  288.             short lineNum = (base[_VP_VDSTAT_OFFSET] & _VP_VDSTAT_VDYPOS_MASK)
  289.                            >> _VP_VDSTAT_VDYPOS_SHIFT;
  290.             /* make sure we are at least five lines before completion */
  291.             /* to prevent EDMA reload happening while it is being modified */
  292.             if(lineNum <= chan->lastLineNum - 5) {
  293.                 Int offset = chan->nextEDMARlds << 1;
  294.                 chan->nextViop = viop;
  295.                 /* now modify the EDMA rld entries */
  296.                 if(chan->mergeFlds){
  297.                     EDMA_RSETH(chan->hRld[offset], SRC, 
  298.                         viop->frame.iFrm.y1);
  299.                     EDMA_RSETH(chan->hRld[offset + 1], SRC, 
  300.                         viop->frame.iFrm.y2);
  301.                     if(!(chan->mode & _VPORT_MASK_RAW)){
  302.                         EDMA_RSETH(chan->hRld[4 + offset], SRC, 
  303.                           viop->frame.iFrm.cb1);     
  304.                         EDMA_RSETH(chan->hRld[5 + offset], SRC, 
  305.                           viop->frame.iFrm.cb2);                         
  306.                         EDMA_RSETH(chan->hRld[8 + offset], SRC, 
  307.                           viop->frame.iFrm.cr1);     
  308.                         EDMA_RSETH(chan->hRld[9 + offset], SRC, 
  309.                           viop->frame.iFrm.cr2);              
  310.                     }           
  311.                 } else {
  312.                     EDMA_RSETH(chan->hRld[offset], SRC, 
  313.                         viop->frame.iFrm.y1);
  314.                     if(!(chan->mode & _VPORT_MASK_RAW)){
  315.                         EDMA_RSETH(chan->hRld[4 + offset], SRC, 
  316.                           viop->frame.iFrm.cb1);     
  317.                         EDMA_RSETH(chan->hRld[8 + offset], SRC, 
  318.                           viop->frame.iFrm.cr1);                         
  319.                     }                                           
  320.                 } /* if(chan->mergeFlds) */
  321.             } else {
  322.                 QUE_enqueue(&chan->qIn, (QUE_Handle)viop);                    
  323.             }
  324.             chan->queEmpty = FALSE;                   
  325.         }
  326.         else {
  327.             QUE_enqueue(&chan->qIn, (QUE_Handle)viop);        
  328.         }
  329.         retVal = packet->status = IOM_COMPLETED;
  330.     }
  331.     if(packet->cmd != FVID_FREE) { /* FVID_ALLOC or FVID_EXCHANGE */
  332.         if(chan->packetIOM == INV){
  333.             if((viop = (FVID_Frame *)QUE_dequeue(&chan->qOut))
  334.                 !=(FVID_Frame *)&chan->qOut) {
  335.                 /* only when there is no outstanding pending request */
  336.                 *(void **)packet->addr = (void *)viop;
  337.                 packet->size = sizeof(FVID_Frame);
  338.                 retVal = packet->status = IOM_COMPLETED;
  339.             }
  340.             else {
  341.                 chan->packetIOM = packet;
  342.                 retVal = packet->status = IOM_PENDING;
  343.             }
  344.         }else retVal = IOM_EINUSE;    
  345.                     
  346.     }    
  347.     IRQ_globalRestore(gie);
  348.     return retVal;
  349. }
  352. /*
  353.  *  ========  _configChan ========
  354.  */
  355. static Int _configChan(Ptr chanp, Ptr args)
  356. {
  357.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  358.     VPORTDIS_Params*   params = (VPORTDIS_Params* )args; 
  359.     Int retVal;           
  360.     
  361.     
  362.     if(!(chan->status & _VPORT_CFGED)) {
  363.         chan->lastLineNum = _getlastActiveLine(params);
  364.         /* configure video port channel A/B control register */
  365.         _configRegs(chanp, params);
  366.         /* configure EDMA and frame buffer */
  367.         retVal = _configEDMA(chanp, params);
  368.     } else {
  369.         retVal = IOM_EINUSE;
  370.     }    
  371.     return retVal;
  372. }                     
  374. static const Int fillValue[4] = {
  375. 0, 0, 0x80808080, 0x80808080
  376. };
  377. /*
  378.  *  ======== _configEDMA ========
  379.  */
  380. static Int _configEDMA(Ptr chanp, VPORTDIS_Params *params)
  381. {
  382.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  383.     Int i;
  384.     Int j;               
  385.     EDMA_Config  cfgEdma;
  386.     Int thrld;
  387.     Int edmaChans;
  388.     Int8* curAddr;
  389.     Bool success;
  390.     
  391.     if(chan->status & _VPORT_CFGED) {
  392.         assert(params->numFrmBufs  >= 2 
  393.             && params->numFrmBufs <= VPORT_MAX_NUM_FRMBUFS);
  394.         chan->numFrms = params->numFrmBufs;
  396.         chan->segId = params->segId;
  398.         /* allocate frame buffers */
  399.         chan->bufSz = chan->yPitch * chan->numLines 
  400.               + chan->cPitch * chan->numLines * 2;
  401.         for(i = 0; i < chan->numFrms; i ++) {  
  402.             if((curAddr = MEM_alloc(params->segId,chan->bufSz, 
  403.                 params->alignment)) == MEM_ILLEGAL){
  404.                 for(j = 0; j < i ; j ++) {
  405.                     MEM_free(params->segId, chan->viops[j].frame.iFrm.y1, 
  406.                         chan->bufSz);
  407.                 }
  408.                 /* memory allocation fails */
  409.                 return IOM_EALLOC;
  410.             }    
  411.             /* field 1 */
  412.             chan->viops[i].frame.iFrm.y1 = curAddr;
  413.             curAddr += chan->numLines*chan->yPitch;
  414.             chan->viops[i].frame.iFrm.cb1 = curAddr;
  415.             curAddr += chan->numLines*chan->cPitch;
  416.             chan->viops[i].frame.iFrm.cr1 = curAddr;
  417.             curAddr += chan->numLines*chan->cPitch;
  418.             
  419.             CACHE_clean(CACHE_L2, (void *)fillValue, 16);
  420.             success = DAT_open(DAT_CHAANY, DAT_PRI_LOW, 0);          
  421.             
  422.             for( j = 0; j < chan->numLines; j ++) {
  423.                 DAT_fill(chan->viops[i].frame.iFrm.y1 + j * chan->yPitch, chan->yPitch, (Uint32 *)fillValue);
  424.                 DAT_fill(chan->viops[i].frame.iFrm.cb1 + j * chan->cPitch, chan->cPitch, (Uint32 *)&fillValue[2]);
  425.                 DAT_fill(chan->viops[i].frame.iFrm.cr1 + j * chan->cPitch, chan->cPitch, (Uint32 *)&fillValue[2]);
  426.             }
  427.             if(success) {
  428.                 DAT_close();
  429.             }
  430.             /* field 2 */
  431.             if(params->fldOp == VPORT_FLDOP_FLD2) {
  432.                 chan->viops[i].frame.iFrm.y2 = chan->viops[i].frame.iFrm.y1;
  433.                 chan->viops[i].frame.iFrm.cb2 = chan->viops[i].frame.iFrm.cb1;
  434.                 chan->viops[i].frame.iFrm.cr2 = chan->viops[i].frame.iFrm.cr1;
  435.             } else if(chan->mergeFlds) {
  436.                 chan->viops[i].frame.iFrm.y2 = chan->viops[i].frame.iFrm.y1
  437.                     + chan->yPitch;
  438.                 chan->viops[i].frame.iFrm.cb2 = chan->viops[i].frame.iFrm.cb1
  439.                     + chan->cPitch;
  440.                 chan->viops[i].frame.iFrm.cr2 = chan->viops[i].frame.iFrm.cr1
  441.                     + chan->cPitch;
  442.             }else {
  443.                 chan->viops[i].frame.iFrm.y2 = chan->viops[i].frame.iFrm.y1
  444.                     + (chan->numLinesFld1*chan->yPitch);
  445.                 chan->viops[i].frame.iFrm.cb2 = chan->viops[i].frame.iFrm.cb1
  446.                     + (chan->numLinesFld1*chan->cPitch);
  447.                 chan->viops[i].frame.iFrm.cr2 = chan->viops[i].frame.iFrm.cr1
  448.                     + (chan->numLinesFld1*chan->cPitch);            
  449.             }    
  450.             if(i > 0) {
  451.                 /* don't put the first 1 viop into the queue */
  452.                 QUE_enqueue(&chan->qOut, (QUE_Handle)&chan->viops[i]);
  453.             }
  454.         }
  455.         chan->nextViop = &chan->viops[0];
  456.         chan->curViop = &chan->viops[0];
  457.         chan->queEmpty = TRUE;
  458.         CACHE_clean(CACHE_L2ALL, NULL, NULL);
  459.     
  461.         if(chan->mode & _VPORT_MASK_RAW) edmaChans = 1;
  462.         else edmaChans = 3;
  464.         for(i = 0; i < edmaChans; i ++) {
  465.             Int optFld1 = EDMA_OPT_RMK(
  466.                   params->edmaPri,
  467.                   EDMA_OPT_ESIZE_32BIT,
  468.                   EDMA_OPT_2DS_YES, 
  469.                   EDMA_OPT_SUM_INC,
  470.                   EDMA_OPT_2DD_NO,
  471.                   EDMA_OPT_DUM_NONE,
  472.                   EDMA_OPT_TCINT_NO,
  473.                   EDMA_OPT_TCC_OF(0), 
  474.                   EDMA_OPT_TCCM_OF(0),
  475.                   EDMA_OPT_ATCINT_NO,
  476.                   EDMA_OPT_ATCC_DEFAULT,
  477.                   EDMA_OPT_PDTS_DISABLE,
  478.                   EDMA_OPT_PDTD_DISABLE,
  479.                   EDMA_OPT_LINK_YES,
  480.                   EDMA_OPT_FS_NO
  481.             );
  482.             Int optFld2a = EDMA_OPT_RMK(
  483.                 
  484.                   params->edmaPri,
  485.                   EDMA_OPT_ESIZE_32BIT,
  486.                   EDMA_OPT_2DS_YES, 
  487.                   EDMA_OPT_SUM_INC,
  488.                   EDMA_OPT_2DD_NO,
  489.                   EDMA_OPT_DUM_NONE,
  490.                   (i == 0 ? EDMA_OPT_TCINT_YES:EDMA_OPT_TCINT_NO),
  491.                   EDMA_OPT_TCC_OF(i == 0 ? chan->tcc[0] & 0x0f : 0), 
  492.                   EDMA_OPT_TCCM_OF(i == 0 ? chan->tcc[0] >> 4 : 0),
  493.                   EDMA_OPT_ATCINT_NO,
  494.                   EDMA_OPT_ATCC_DEFAULT,
  495.                   EDMA_OPT_PDTS_DISABLE,
  496.                   EDMA_OPT_PDTD_DISABLE,
  497.                   EDMA_OPT_LINK_YES,
  498.                   EDMA_OPT_FS_NO
  499.             );
  500.             Int optFld2b = EDMA_OPT_RMK(
  501.                 
  502.                   params->edmaPri,
  503.                   EDMA_OPT_ESIZE_32BIT,
  504.                   EDMA_OPT_2DS_YES, 
  505.                   EDMA_OPT_SUM_INC,
  506.                   EDMA_OPT_2DD_NO,
  507.                   EDMA_OPT_DUM_NONE,
  508.                   (i == 0 ? EDMA_OPT_TCINT_YES:EDMA_OPT_TCINT_NO),
  509.                   EDMA_OPT_TCC_OF(i == 0 ? chan->tcc[1] & 0x0f : 0), 
  510.                   EDMA_OPT_TCCM_OF(i == 0 ? chan->tcc[1] >> 4 : 0),
  511.                   EDMA_OPT_ATCINT_NO,
  512.                   EDMA_OPT_ATCC_DEFAULT,
  513.                   EDMA_OPT_PDTS_DISABLE,
  514.                   EDMA_OPT_PDTD_DISABLE,
  515.                   EDMA_OPT_LINK_YES,
  516.                   EDMA_OPT_FS_NO
  517.             );
  519.             thrld = (i == 0)? chan->yThrld:chan->cThrld;
  520.             cfgEdma.dst = EDMA_DST_RMK(chan->edmaAddr[i]);
  521.             if(chan->mergeFlds) {
  522.                 /* to merge the two fields together */
  523.                 /* EDMA is configured to transfer only field 1 initially */
  524.                 /* line pitch is twice the line size */
  525.                 /* this requires that the threlhold is the same as line size*/
  527.                 /* PaRAM and reload Entries */
  529.                 /* first field */
  530.                 cfgEdma.opt = optFld1;
  531.                 cfgEdma.cnt = EDMA_CNT_RMK(
  532.                     (chan->numEventsFld1) - 1, (thrld << 1));
  533.                 cfgEdma.idx = EDMA_IDX_RMK(thrld << 4, 0);
  534.                 /* hard code the field 1 & 2 of the first     */
  535.                 /* frame buffer as current and reload buffers */
  536.                 cfgEdma.src = EDMA_SRC_RMK(
  537.                     *((Int *)(&chan->viops[0].frame.iFrm.y1) + i));
  538.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4*i + 1]);
  539.                 EDMA_config(chan->hEdma[i], &cfgEdma);
  540.                 EDMA_config(chan->hRld[4 * i], &cfgEdma);
  541.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4*i + 3]);
  542.                 EDMA_config(chan->hRld[4 * i + 2], &cfgEdma);
  543.                 
  544.                 /* second field */
  545.                 cfgEdma.opt = optFld2a;
  546.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i + 2]);
  547.                 cfgEdma.cnt = EDMA_CNT_RMK(
  548.                     (chan->numEvents-chan->numEventsFld1) - 1, (thrld << 1));
  549.                 cfgEdma.src = EDMA_SRC_RMK(
  550.                     *((Int *)(&chan->viops[0].frame.iFrm.y2) + i));
  551.                 EDMA_config(chan->hRld[4 * i + 1], &cfgEdma); 
  552.                 cfgEdma.opt = optFld2b;
  553.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4*i]);
  554.                 EDMA_config(chan->hRld[4 * i + 3], &cfgEdma);
  555.                 
  556.             }else {/* if fields are not merged, configure EDMA to transfer */
  557.                    /* for both field1 and field 2                          */
  558.                    /* the line pitch is just the line size                 */
  559.                 cfgEdma.opt = optFld2a;
  560.                 cfgEdma.cnt = EDMA_CNT_RMK((chan->numEvents) - 1, (thrld << 1));
  561.                 cfgEdma.idx = EDMA_IDX_RMK(thrld << 3, 0);
  562.                 /* hard code the first frame buffer as current  */
  563.                 /*and reload buffers */
  564.                 cfgEdma.src = EDMA_SRC_RMK(
  565.                     *((Int *)(&chan->viops[0].frame.iFrm.y1) + i));
  566.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i + 2]);
  567.                 EDMA_config(chan->hEdma[i], &cfgEdma);
  568.                 cfgEdma.src = EDMA_SRC_RMK(
  569.                     *((Int *)(&chan->viops[0].frame.iFrm.y1) + i));
  570.                 EDMA_config(chan->hRld[4 * i], &cfgEdma);
  571.                 cfgEdma.opt = optFld2b;
  572.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i]);
  573.                 EDMA_config(chan->hRld[4 * i + 2], &cfgEdma);
  574.             }
  575.         }
  576.         chan->nextEDMARlds = 1;        
  577.         
  578.         /* enable EDMA channel */        
  579.         if(!(chan->mode & _VPORT_MASK_RAW)) {
  580.             EDMA_disableChannel(chan->hEdma[1]);
  581.             EDMA_clearChannel(chan->hEdma[1]);
  582.             EDMA_enableChannel(chan->hEdma[1]);
  583.             EDMA_disableChannel(chan->hEdma[2]);
  584.             EDMA_clearChannel(chan->hEdma[2]);
  585.             EDMA_enableChannel(chan->hEdma[2]);
  586.         }   
  587.           
  588.         /*
  589.          * The EDMA interrupt dispatcher will be called by the
  590.          * BIOS HWI interrupt dispatcher.
  591.          */
  592.         IRQ_map(IRQ_EVT_EDMAINT, params->irqId);
  593.         HWI_dispatchPlug(params->irqId, (Fxn)EDMA_intDispatcher, -1, NULL);
  596.         EDMA_disableChannel(chan->hEdma[0]);
  597.         EDMA_clearChannel(chan->hEdma[0]);
  598.         EDMA_enableChannel(chan->hEdma[0]);
  600.         EDMA_intClear(chan->tcc[0]);
  601.         EDMA_intEnable(chan->tcc[0]);
  602.         EDMA_intHook(chan->tcc[0], displayEdmaISR);     
  603.         
  604.         EDMA_intClear(chan->tcc[1]);
  605.         EDMA_intEnable(chan->tcc[1]);
  606.         EDMA_intHook(chan->tcc[1], displayEdmaISR);     
  607.         
  609.         chan->status |= _VPORT_READY;
  610.         IRQ_enable(IRQ_EVT_EDMAINT);
  611.     }   
  612.     return IOM_COMPLETED;
  614. }
  617. /*
  618.  *  ======== _configPort ========
  619.  */
  620. static Int _configPort(Ptr chanp, Ptr args)
  621. {
  622.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  623.     VPORT_PortParams* portParams = (VPORT_PortParams*)args; 
  624.     volatile Int* base = (volatile Int *)chan->base;  
  627.     /* reset video port */
  628.     base[_VP_VPCTL_OFFSET] = 
  629.          VP_VPCTL_VPRST_RESET << _VP_VPCTL_VPRST_SHIFT;
  631.     /* enable video port */
  632.     base[_VP_PCR_OFFSET] |= 
  633.          VP_PCR_PEREN_ENABLE << _VP_PCR_PEREN_SHIFT;
  634.             
  635.     base[_VP_VDCTL_OFFSET] = 
  636.          (Int)VP_VDCTL_RSTCH_RESET << _VP_VDCTL_RSTCH_SHIFT;
  637.     
  639.     /* configure video port control register */
  640.     base[_VP_VPCTL_OFFSET] = VP_VPCTL_RMK(0,0,1,portParams->vc3Polarity,
  641.         portParams->vc2Polarity,portParams->vc1Polarity,0,1,0);
  643.     /* enable video port */
  644.     base[_VP_VPCTL_OFFSET] |= (VP_VPCTL_VPHLT_CLEAR << _VP_VPCTL_VPHLT_SHIFT);
  645.     chan->edcFxns = portParams->edcTbl[0];
  646.     return IOM_COMPLETED;
  647. }
  648.                      
  650. /*
  651.  *  ======== _configRegs ========
  652.  * configure video port registers for display 
  653.  */
  654. static  Int _configRegs(Ptr chanp, VPORTDIS_Params* params)
  655. {
  656.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  657.     volatile Int* base = (volatile Int *)chan->base;                          
  658.     Int numPixels, numLines, numCPixels;
  659.     Int vdCtl;
  660.     Int nh1 = 0, nh2 = 0, nv1 = 0, nv2 = 0;    
  661.     
  662.     
  663.     if(chan->status & _VPORT_OPENED) {
  664.         /* configure display settings  */
  665.         chan->status |= _VPORT_CFGED;
  667.         vdCtl = VP_VDCTL_RMK(0,1,0,((params->extCtl&4) >> 2),
  668.             ((params->extCtl&2)>>1), params->extCtl&1,params->vctl3Config,
  669.             params->vctl2Config,params->vctl1Config,0, params->bpk10Bit,
  670.             params->rgbX,0,params->defValEn,params->resmpl,
  671.             params->scale, 1,((params->fldOp & 4) >> 2),
  672.             ((params->fldOp & 2) >> 1), 
  673.             (params->fldOp & 1), 
  674.             params->dmode);
  676.         numLines = 0;
  677.         numPixels = 0;
  678.         if(params->fldOp != VPORT_FLDOP_FLD2){
  679.             // progressive scan, or field 1 or frame
  680.             numPixels = params->imgHSizeFld1;
  681.             numLines = params->imgVSizeFld1;
  682.         } 
  683.         chan->numLinesFld1 = numLines;
  684.         if(params->fldOp == VPORT_FLDOP_FLD2 || 
  685.            params->fldOp == VPORT_FLDOP_FRAME){
  686.             if(!numPixels) numPixels = params->imgHSizeFld2;
  687.             numLines += params->imgVSizeFld2;
  688.         }
  689.         chan->numLines = numLines;
  691.         base[_VP_VDCTL_OFFSET] = vdCtl;
  693.         base[_VP_VDFRMSZ_OFFSET]   = 
  694.             VP_VDFRMSZ_RMK(params->frmVSize, params->frmHSize);
  695.         base[_VP_VDHBLNK_OFFSET]   = 
  696.             VP_VDHBLNK_RMK(params->hBlnkStop, !(params->dmode&_VPORT_MASK_RAW), 
  697.             params->hBlnkStart);
  698.         
  699.         base[_VP_VDVBLKS1_OFFSET]  = 
  700.             VP_VDVBLKS1_RMK(params->vBlnkYStartFld1, params->vBlnkXStartFld1);
  701.         base[_VP_VDVBLKE1_OFFSET]  = 
  702.             VP_VDVBLKE1_RMK(params->vBlnkYStopFld1, params->vBlnkXStopFld1);
  703.         base[_VP_VDVBLKS2_OFFSET]  = 
  704.             VP_VDVBLKS2_RMK(params->vBlnkYStartFld2, params->vBlnkXStartFld2);
  705.         base[_VP_VDVBLKE2_OFFSET]  = 
  706.             VP_VDVBLKE2_RMK(params->vBlnkYStopFld2, params->vBlnkXStopFld2);
  708.         base[_VP_VDVBIT1_OFFSET]   = 
  709.             VP_VDVBIT1_RMK(params->vBlnkYStopFld1, params->vBlnkYStartFld1);
  710.         base[_VP_VDVBIT2_OFFSET] = 
  711.             VP_VDVBIT1_RMK(params->vBlnkYStopFld2, params->vBlnkYStartFld2);
  712.         
  713.         if(params->imgHOffsetFld1<0) {
  714.             nh1 = 1;
  715.             params->imgHOffsetFld1 = -params->imgHOffsetFld1;
  716.         }
  717.         if(params->imgHOffsetFld2<0) {
  718.             nh2 = 1;
  719.             params->imgHOffsetFld2 = -params->imgHOffsetFld2;
  720.         }
  721.         if(params->imgVOffsetFld1<0) {
  722.             nv1 = 1;
  723.             params->imgVOffsetFld1 = -params->imgVOffsetFld1;
  724.         }
  725.         if(params->imgHOffsetFld2<0) {
  726.             nv2 = 1;
  727.             params->imgVOffsetFld2 = -params->imgVOffsetFld2;
  728.         }
  729.         
  730.         base[_VP_VDIMGOFF1_OFFSET] = 
  731.             VP_VDIMGOFF1_RMK(nv1, params->imgVOffsetFld1, nh1, 
  732.             params->imgHOffsetFld1);
  733.         base[_VP_VDIMGSZ1_OFFSET]  = 
  734.             VP_VDIMGSZ1_RMK(params->imgVSizeFld1, params->imgHSizeFld1);
  735.         base[_VP_VDIMGOFF2_OFFSET] = 
  736.             VP_VDIMGOFF2_RMK(nv2, params->imgVOffsetFld2, nh2, 
  737.             params->imgHOffsetFld2);
  738.         base[_VP_VDIMGSZ2_OFFSET]  = 
  739.             VP_VDIMGSZ2_RMK(params->imgVSizeFld2, params->imgHSizeFld2);
  741.         base[_VP_VDFLDT1_OFFSET]   = 
  742.             VP_VDFLDT1_RMK(params->yStartFld1, params->xStartFld1);  
  743.         base[_VP_VDFLDT2_OFFSET]   = 
  744.             VP_VDFLDT2_RMK(params->yStartFld2, params->xStartFld2); 
  745.         base[_VP_VDFBIT_OFFSET]   = 
  746.             VP_VDFBIT_RMK(params->yStartFld2, params->yStartFld1);
  747.         
  748.         base[_VP_VDHSYNC_OFFSET]   = 
  749.             VP_VDHSYNC_RMK(params->hSyncStop, params->hSyncStart);
  750.         base[_VP_VDVSYNS1_OFFSET]  = 
  751.             VP_VDVSYNS1_RMK(params->vSyncYStartFld1, params->vSyncXStartFld1);
  752.         base[_VP_VDVSYNE1_OFFSET]  = 
  753.             VP_VDVSYNE1_RMK(params->vSyncYStopFld1, params->vSyncXStopFld1);  
  754.         base[_VP_VDVSYNS2_OFFSET]  = 
  755.             VP_VDVSYNS2_RMK(params->vSyncYStartFld2, params->vSyncXStartFld2);
  756.         base[_VP_VDVSYNE2_OFFSET]  = 
  757.             VP_VDVSYNE2_RMK(params->vSyncYStopFld2, params->vSyncXStopFld2);  
  759.         base[_VP_VDCLIP_OFFSET]    = 
  760.             VP_VDCLIP_RMK(params->cClipHigh, params->cClipLow,
  761.             params->yClipHigh, params->yClipLow);
  762.         base[_VP_VDDEFVAL_OFFSET]  = params->yDefVal |
  763.            (params->cbDefVal << 16) | (params->crDefVal << 24);
  764.         
  765.         chan->resmpl = params->resmpl;
  766.         chan->scale = params->scale;
  767.         numPixels >>= params->scale;
  768.         chan->numPixels = numPixels;
  769.         numCPixels = (params->dmode & _VPORT_MASK_RAW) ? 0 : numPixels >> 1;
  770.         
  771.         if(params->dmode & _VPORT_MASK_RAW) { /* raw mode */
  772.             chan->cPitch = 0;
  773.             if(params->dmode == VPORT_MODE_RAW_8BIT) {
  774.                 chan->yPitch = (numPixels + 7) & (~ 7);
  775.                 chan->cPitch = (numCPixels + 7) & (~ 7);
  776.             } else if(params->dmode == VPORT_MODE_RAW_10BIT) {
  777.                 if(params->bpk10Bit == VPORTDIS_BPK_10BIT_DENSE){
  778.                     chan->yPitch = (numPixels * 4 / 3 + 7) & (~ 7);
  779.                 }else {
  780.                     chan->yPitch = (numPixels * 2 + 7) & (~ 7);
  781.                 }
  782.             } else if(params->dmode == VPORT_MODE_RAW_16BIT) {
  783.                 chan->yPitch = (numPixels * 2 + 7) & (~ 7);
  784.             } else {
  785.                 chan->yPitch = (numPixels * 4 + 7) & (~ 7);
  786.             }                                                                        
  787.         } else {
  788.             if(params->dmode & _VPORT_MASK_10BIT) {
  789.                 if(params->bpk10Bit == VPORTDIS_BPK_10BIT_DENSE){
  790.                     chan->yPitch = (numPixels * 4 / 3 + 7) & (~ 7);
  791.                     chan->cPitch = (numCPixels* 4 / 3 + 7) & (~ 7);
  792.                 }else {
  793.                     chan->yPitch = (numPixels * 2 + 7) & (~ 7);
  794.                     chan->cPitch = (numCPixels * 2 + 7) & (~ 7);
  795.                 }
  796.             } else {/* 8 bit mode */
  797.                 chan->yPitch = (numPixels + 7) & (~ 7);
  798.                 chan->cPitch = (numCPixels + 7) & (~ 7);
  799.             }
  800.         }
  801.         chan->yThrld = params->thrld;       
  802.         if(params->mergeFlds && params->fldOp == VPORT_FLDOP_FRAME) {
  803.             /* frame capture and merge 2 fields into one frame */
  804.             /* make sure threshold is same as line size */
  805.             chan->yThrld = chan->yPitch >> 3;
  806.             chan->numEventsFld1 = chan->numLinesFld1;
  807.             chan->numEvents = chan->numLines;
  808.             chan->mergeFlds = TRUE;  
  809.         }else {            
  810.             /* these two asserts make sure that total transfer sizes of */
  811.             /* both the whole frame and the first field are multiples   */
  812.             /* of the threshold                                         */
  813.             assert(((chan->yPitch*chan->numLinesFld1)/(chan->yThrld << 3)) 
  814.                 *(chan->yThrld << 3) == (chan->yPitch*chan->numLinesFld1));
  815.             assert(((chan->yPitch*chan->numLines)/(chan->yThrld << 3)) 
  816.                 *(chan->yThrld << 3) == (chan->yPitch*chan->numLines));
  817.             chan->numEventsFld1 = 
  818.                 chan->yPitch * chan->numLinesFld1 / (chan->yThrld << 3);
  819.             chan->numEvents = 
  820.                 chan->yPitch * chan->numLines / (chan->yThrld << 3);
  821.             chan->mergeFlds = FALSE;
  822.         }                    
  823.         if(params->dmode & _VPORT_MASK_RAW) {
  824.             chan->cThrld = 0;
  825.         }    
  826.         else {
  827.             chan->cThrld = (chan->yThrld + 1) >> 1;
  828.         }    
  829.         base[_VP_VDTHRLD_OFFSET] = 
  830.             VP_VDTHRLD_RMK(chan->yThrld,params->incPix,chan->yThrld);
  831.         base[_VP_VDDISPEVT_OFFSET] = 
  832.             VP_VDDISPEVT_RMK((chan->numEvents-chan->numEventsFld1), 
  833.             chan->numEventsFld1 );  
  835.         
  836.         chan->mode = params->dmode;
  837.         chan->status |= _VPORT_CFGED;
  838.     }
  839.     return IOM_COMPLETED;
  841. }
  844. /*
  845.  *  ======== displayEdmaISR ========
  846.  */
  847. static void displayEdmaISR(tcc) 
  848. {
  849.     Int i;
  850.     FVID_Frame *viop, *curViop;      
  851.     Int offset;
  852.     
  853.     
  854.     /* find out the source of the edma interrupt */
  855.     for(i = 0; i < _VP_PORT_CNT; i ++) {      
  856.         _VPORT_ChanObj* chan = &chanObjs[i];
  857.         if((chan->status & _VPORT_READY) && 
  858.           (tcc == chan->tcc[0] || tcc == chan->tcc[1])){
  860.             /* re-sync tcc with activeEDMARlds */
  861.             /* they may be out of sync after interrupt over-run */
  862.             /* e.g. execution is halted at break-point */
  863.             chan->nextEDMARlds = (tcc == chan->tcc[0]) ? 0 : 1;
  864.             offset = chan->nextEDMARlds << 1;
  865.             /* update the current and next viop pointers */
  866.             curViop = chan->curViop;
  867.             chan->curViop = chan->nextViop;
  868.             if((viop = (FVID_Frame *)QUE_dequeue(&chan->qIn))
  869.                 != (FVID_Frame *)&chan->qIn) {
  870.                 /* queue IS not empty */
  871.                 chan->nextViop = viop;
  872.             }else {
  873.                 chan->queEmpty = TRUE;
  874.             }
  876.             /* Update the EDMA reload entry  */
  877.             if(chan->mergeFlds){
  878.                 EDMA_RSETH(chan->hRld[offset], SRC, 
  879.                     chan->nextViop->frame.iFrm.y1);
  880.                 EDMA_RSETH(chan->hRld[offset + 1], SRC, 
  881.                     chan->nextViop->frame.iFrm.y2);
  882.                 if(!(chan->mode & _VPORT_MASK_RAW)){
  883.                     EDMA_RSETH(chan->hRld[4 + offset], SRC, 
  884.                         chan->nextViop->frame.iFrm.cb1);     
  885.                     EDMA_RSETH(chan->hRld[5 + offset], SRC, 
  886.                         chan->nextViop->frame.iFrm.cb2);                         
  887.                     EDMA_RSETH(chan->hRld[8 + offset], SRC, 
  888.                         chan->nextViop->frame.iFrm.cr1);     
  889.                     EDMA_RSETH(chan->hRld[9 + offset], SRC, 
  890.                         chan->nextViop->frame.iFrm.cr2);                         
  891.                 }
  892.             } else {
  893.                 EDMA_RSETH(chan->hRld[offset], SRC, 
  894.                     chan->nextViop->frame.iFrm.y1);
  895.                 if(! (chan->mode & _VPORT_MASK_RAW)){
  896.                     EDMA_RSETH(chan->hRld[offset + 4], SRC, 
  897.                         chan->nextViop->frame.iFrm.cb1);
  898.                     EDMA_RSETH(chan->hRld[offset + 8], SRC, 
  899.                         chan->nextViop->frame.iFrm.cr1);
  900.                 }
  901.             }/* if(chan->mergeFlds) {*/
  902.             
  903.             if(curViop != chan->curViop) {
  904.                 if(chan->packetIOM != INV) {
  905.                     /* call the channel's callback function */
  906.                     *(void **)chan->packetIOM->addr = curViop;             
  907.                     chan->packetIOM->size = sizeof(FVID_Frame);
  908.                     chan->cbFxn((Ptr)chan->cbArg, chan->packetIOM);  
  909.                     chan->packetIOM = INV;
  910.                 }else {
  911.                     QUE_enqueue(&chan->qOut,curViop);
  912.                 }
  913.             }/*if(curViop != chan->curViop) {*/  
  914.         }/*if((chan->status & READY) && tcc == chan->tcc){*/
  915.     } /*for(i = 0; i <_VP_PORT_CNT; i++) {  */
  916. }
  919. /*
  920.  *  ======== displayISR ========
  921.  */
  922. static void displayISR(int portNum)
  923. {
  924.     volatile Int *base =  
  925.         (volatile Int *)chanObjs[portNum].base;
  926.     Int vpis = base[_VP_VPIS_OFFSET];
  927.     Int mask = vpis & chanObjs[portNum].vIntMask;
  928.         
  929.     if(mask && chanObjs[portNum].vIntFxn != INV) {
  930.         chanObjs[portNum].vIntFxn(chanObjs[portNum].cbArg, mask);
  931.     }
  932.     /* clear interrupts that has been handled */
  933.     base[_VP_VPIS_OFFSET] |= vpis;
  934. }  
  937. /*
  938.  *  ======== _displayStart ========
  939.  *  start video display
  940.  */
  941. static Int _displayStart(Ptr chanp)
  942. {
  943.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  944.     volatile Int* base = (volatile Int *)chan->base;  
  945.     volatile Int stat;
  946.     volatile Int i = 0;
  947.                                       
  948.     /* enable port and display */
  949.     base[_VP_VPCTL_OFFSET] |= VP_VPCTL_VPHLT_CLEAR << _VP_VPCTL_VPHLT_SHIFT;
  950.     base[_VP_VDCTL_OFFSET] |= VP_VDCTL_VDEN_ENABLE << _VP_VDCTL_VDEN_SHIFT;
  951.     /* wait for display counters and control signals to sync up */
  952.     do {
  953.         stat = base[_VP_VDSTAT_OFFSET];
  954.         i ++ ;
  955.     }while(!(stat & 0x70000000) && i < 1000000);
  956.     base[_VP_VDSTAT_OFFSET] = stat;
  957.     
  958.     do {
  959.         stat = base[_VP_VDSTAT_OFFSET];
  960.         i ++;
  961.     }while(!(stat & 0x70000000) && i < 1000000);
  962.     base[_VP_VDSTAT_OFFSET] = stat;
  963.     base[_VP_VDCTL_OFFSET] &= ~ (_VP_VDCTL_BLKDIS_MASK);
  964.     /* enable interrupt */
  965.     base[_VP_VPIE_OFFSET] |= VP_VPIE_VIE_ENABLE << _VP_VPIE_VIE_SHIFT;     
  966.     IRQ_clear(IRQ_EVT_VINT0 + chan->portNum);
  967.     IRQ_enable(IRQ_EVT_VINT0 + chan->portNum);
  968.     return IOM_COMPLETED;
  969. }        
  972. /*
  973.  *  ======== _displayStop ========
  974.  *  stop video display
  975.  */
  976. static Int _displayStop(Ptr chanp)
  977. {
  978.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  979.     volatile Int* base = (volatile Int *)chan->base;    
  980.     
  981.     
  982.     base[_VP_VDCTL_OFFSET] &= ~  (VP_VDCTL_VDEN_ENABLE << _VP_VDCTL_VDEN_SHIFT);
  983.     return IOM_COMPLETED;
  984. }
  987. /*
  988.  *  ======== _dundRecover ========
  989.  *  force recover from display under-run
  990.  */
  991. static Int _dundRecover(Ptr chanp)
  992. {
  993.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  994.     Int i;          
  995.     Int stat;
  996.     Int numEvents;
  997.     volatile Int* base = (volatile Int *)chan->base;  
  998.     
  999.     
  1000.     /* disable under run interrupt */
  1001.     base[_VP_VPIE_OFFSET] &= ~ (_VP_VPIE_DUND_MASK);
  1002.     /* clear any pending under-run interrupt */
  1003.     base[_VP_VPIS_OFFSET] &= ~ (_VP_VPIS_DUND_MASK);
  1005.      /* block display events */
  1006.     base[_VP_VDCTL_OFFSET] |= _VP_VDCTL_BLKDIS_MASK;
  1007.     /* Disable the edmas before settings them up */
  1008.     if(!(chan->mode & _VPORT_MASK_RAW)){
  1009.         EDMA_disableChannel(chan->hEdma[1]);
  1010.         EDMA_clearChannel(chan->hEdma[1]);
  1011.         EDMA_disableChannel(chan->hEdma[2]);
  1012.         EDMA_clearChannel(chan->hEdma[2]);
  1013.     }
  1014.     EDMA_intDisable(chan->tcc[0]);
  1015.     EDMA_intDisable(chan->tcc[1]);
  1016.     EDMA_disableChannel(chan->hEdma[0]);            
  1017.     EDMA_clearChannel(chan->hEdma[0]);
  1018.     
  1020.     if(chan->mergeFlds) {
  1021.         numEvents = chan->numEventsFld1;        
  1022.     } else {
  1023.         numEvents = chan->numEvents;
  1024.     }
  1025.     /* set up DMA parameters again */
  1026.     EDMA_RSETH(chan->hEdma[0], SRC, chan->curViop->frame.iFrm.y1);
  1027.     EDMA_RSETH(chan->hEdma[0], CNT, EDMA_CNT_RMK(numEvents - 1, 
  1028.         chan->yThrld << 1));
  1029.     if(!(chan->mode & _VPORT_MASK_RAW)){
  1030.         EDMA_RSETH(chan->hEdma[1], SRC, chan->curViop->frame.iFrm.cb1);
  1031.         EDMA_RSETH(chan->hEdma[2], SRC, chan->curViop->frame.iFrm.cr1);
  1032.         EDMA_RSETH(chan->hEdma[1], CNT, 
  1033.             EDMA_CNT_RMK(numEvents - 1, chan->cThrld << 1));
  1034.         EDMA_RSETH(chan->hEdma[2], CNT, 
  1035.             EDMA_CNT_RMK(numEvents - 1, chan->cThrld << 1));
  1036.     }    
  1037.    
  1038.     /* enable the edma events again before settings them up */
  1039.     EDMA_enableChannel(chan->hEdma[1]);
  1040.     EDMA_enableChannel(chan->hEdma[2]);          
  1041.    
  1042.     EDMA_intEnable(chan->tcc[0]);
  1043.     EDMA_intEnable(chan->tcc[1]);
  1044.     EDMA_enableChannel(chan->hEdma[0]);
  1046.     base[_VP_VDCTL_OFFSET] |= VP_VDCTL_VDEN_ENABLE << _VP_VDCTL_VDEN_SHIFT;
  1047.     /* wait for display counters and control signals to sync up */
  1048.     do {
  1049.         stat = base[_VP_VDSTAT_OFFSET];
  1050.         i ++ ;
  1051.     }while(!(stat & 0x70000000) && i < 1000000);
  1052.     base[_VP_VDSTAT_OFFSET] = stat;
  1053.     
  1054.     do {
  1055.         stat = base[_VP_VDSTAT_OFFSET];
  1056.         i ++;
  1057.     }while(!(stat & 0x70000000) && i < 1000000);
  1059.     base[_VP_VDCTL_OFFSET] &= ~(_VP_VDCTL_BLKDIS_MASK);
  1060.     /* re-enable under run interrupt */
  1061.     base[_VP_VPIE_OFFSET] |= _VP_VPIE_DUND_MASK;
  1062.     return IOM_COMPLETED;
  1064. }
  1066. /*
  1067.  *  ======== _getlastActiveLine ========
  1068.  *  get the line number of the last active line
  1069.  */
  1070. static Int _getlastActiveLine(VPORTDIS_Params* params)
  1071. {
  1072.     int lastActiveLine = -1;
  1073.     switch (params->fldOp){
  1074.         case VPORT_FLDOP_FRAME:
  1075.         case VPORT_FLDOP_FLD2:  
  1076.             lastActiveLine = params->vBlnkYStopFld2 
  1077.               + params->imgVOffsetFld2
  1078.               + params->imgVSizeFld2;
  1079.             
  1080.        break;                      
  1081.         case VPORT_FLDOP_FLD1:
  1082.         case VPORT_FLDOP_PROGRESSIVE:
  1083.             lastActiveLine = params->vBlnkYStopFld1 
  1084.               + params->imgVOffsetFld1
  1085.               + params->imgVSizeFld1;
  1086.         break;        
  1087.     }
  1088.     return lastActiveLine;
  1089. }    
  1092. /*
  1093.  *  ======== _setVIntCb ========
  1094.  *  set video port interrutp call-back
  1095.  */
  1096. static Int _setVIntCb(Ptr chanp, Ptr args)
  1097. {
  1098.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  1099.     volatile Int* base = (volatile Int *)chan->base;  
  1100.     VPORT_VIntCbParams* vIntCbParams = (void *)args;
  1101.     Int mask = vIntCbParams->vIntMask;
  1102.     Uns vif2 = 0, vInt2 = 0, vif1 = 0, vInt1 = 0;
  1105.     chan->vIntMask = mask;
  1106.     /* check to see if vertical interrupt is enabled */
  1107.     if(mask & VPORT_INT_VINT1) {
  1108.         vif1 = 1;
  1109.         vInt1 = vIntCbParams->vIntLine;
  1110.     }
  1111.     if(mask & VPORT_INT_VINT2) {
  1112.         vif2 = 1;
  1113.         vInt2 = vIntCbParams->vIntLine;    
  1114.     }
  1115.     base[_VP_VDVINT_OFFSET] = VP_VDVINT_RMK(vif2, 
  1116.         vInt2, vif1, vInt1);
  1117.     if(mask) {
  1118.         mask |= 1; /* turn on video port interrupt */
  1119.         IRQ_map(IRQ_EVT_VINT0 + chan->portNum, vIntCbParams->irqId);    
  1120.         HWI_dispatchPlug(vIntCbParams->irqId, (Fxn)displayISR, -1, NULL);
  1121.         IRQ_disable(IRQ_EVT_VINT0 + chan->portNum);
  1122.         IRQ_clear(IRQ_EVT_VINT0 + chan->portNum);
  1123.     }
  1124.     base[_VP_VPIE_OFFSET] |= mask;  /* register write */    
  1125.     chan->vIntFxn =  vIntCbParams->vIntCbFxn;       
  1126.     return IOM_COMPLETED;
  1127. }