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vportcap.c
资源名称：DSP-C6000-DM642DEMO.rar　[点击查看]
上传用户：dahaojd
上传日期：2008-01-29
资源大小：14357k
文件大小：42k
源码类别：

DSP编程

开发平台：

C/C++

vportcap.c：源码内容
  1. /*
  2.  *  Copyright 2003 by Texas Instruments Incorporated.
  3.  *  All rights reserved. Property of Texas Instruments Incorporated.
  4.  *  Restricted rights to use, duplicate or disclose this code are
  5.  *  granted through contract.
  6.  *  
  7.  */
  8. /* "@(#) DDK 1.10.00.23 07-02-03 (ddk-b12)" */
  10. /* DSP/BIOS standard include files */
  11. #include <std.h>
  12. #include <mem.h>
  13. #include <que.h>     
  14. #include <tsk.h>    
  15. #include <hwi.h>          
  16. #include <clk.h>
  18. /* Chip-support library include files */
  19. #include <csl.h>
  20. #include <csl_edma.h>
  21. #include <csl_vphal.h>         
  22. #include <csl_irq.h>
  23. #include <csl_cache.h>
  25. /* IOM/GIO driver model include files */
  26. #include <iom.h>
  27. #include <fvid.h>                       
  29. /* video driver specific include files */
  30. #include <vport.h>
  31. #include <vportcap.h>
  32. #include <edc.h>
  33. #include "_vport.h"
  35. /* debug include files */
  36. /* to minimize code size and cycle count overhead of the driver */             
  37. /* error checking is only performed at debug time               */
  38. #include <assert.h>
  40. /* type defines and data structures */
  41. /**************************************************************
  42.  *     data structure for video port object                   *
  43.  **************************************************************/
  44. typedef struct PortObj{
  45.     /* port status register, contains information on whether */
  46.     /* port is opened, configured, etc.                      */
  47.     Int     status;
  48.     /* vp base address for all register access */
  49.     Int     base;
  50.     
  51.     /* two channel objects for channel A & B.  */
  52.     /* This is only for capture operation      */
  53.     _VPORT_ChanObj chanObj[2];
  54. } PortObj;
  57. /* mini-driver API functions */
  58. static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams);
  59. static Int mdControlChan(Ptr chanp, Uns cmd, Ptr args);
  60. static Int mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
  61.         Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg);
  62. static Int mdDeleteChan(Ptr chanp);
  63. static Int mdSubmitChan(Ptr chanp, IOM_Packet *packet);
  66. /* local functions */
  67. static void captureEdmaISR(Int tcc);
  68. static void captureISR(Int portNum);
  69. static Int _configCh(Ptr chanp, VPORTCAP_Params *params);
  70. static Int _configChan(Ptr chanp, Ptr args);     
  71. static Int _configPort(Ptr chanp, Ptr args);    
  72. static Int _configTransfer(Ptr chanp,VPORTCAP_Params *params);  
  73. static Int _covrRecover(Ptr chanp);
  74. static Int _setVIntCb(Ptr chanp, Ptr args);
  75. static Int _startVPCapture(Ptr chanp);
  76. static Int _stopVPCapture(Ptr chanp);   
  78. /* global and static variables */
  79. IOM_Fxns VPORTCAP_Fxns = {
  80.     mdBindDev,    
  81.     (IOM_TmdUnBindDev)IOM_mdNotImpl,
  82.     mdControlChan,
  83.     mdCreateChan,
  84.     mdDeleteChan,
  85.     mdSubmitChan
  86. };
  88. /**************************************************************
  89.  * Static allocation and initialization of port objects       *
  90.  **************************************************************/
  91. static PortObj portObjs[_VP_PORT_CNT] = {
  92.     /* video port 0 */
  93.     {0, _VP_BASE_PORT0,
  94.     /* channel A */  
  95.         {{0, 0, 0, _VP_BASE_CHAPORT0, EDMA_CHA_VP0EVTYA, EDMA_CHA_VP0EVTUA, 
  96.         EDMA_CHA_VP0EVTVA, _VP_YSRCA0_ADDR, _VP_CBSRCA0_ADDR, 
  97.         _VP_CRSRCA0_ADDR }, 
  98.     /* channel B */  
  99.         {0, 0, 1, _VP_BASE_CHBPORT0, EDMA_CHA_VP0EVTYB, EDMA_CHA_VP0EVTUB, 
  100.         EDMA_CHA_VP0EVTVB,  _VP_YSRCB0_ADDR, _VP_CBSRCB0_ADDR, 
  101.         _VP_CRSRCB0_ADDR}}},
  103.     /* video port 1 */
  104.     {0, _VP_BASE_PORT1, 
  105.     /* channel A */  
  106.         {{0, 1, 0, _VP_BASE_CHAPORT1, EDMA_CHA_VP1EVTYA, EDMA_CHA_VP1EVTUA, 
  107.         EDMA_CHA_VP1EVTVA, _VP_YSRCA1_ADDR, _VP_CBSRCA1_ADDR, 
  108.         _VP_CRSRCA1_ADDR }, 
  109.     /* channel B */  
  110.         {0, 1, 1, _VP_BASE_CHBPORT1, EDMA_CHA_VP1EVTYB, EDMA_CHA_VP1EVTUB, 
  111.         EDMA_CHA_VP1EVTVB, _VP_YSRCB1_ADDR, _VP_CBSRCB1_ADDR, 
  112.         _VP_CRSRCB1_ADDR}}},
  114.     /* video port 2 */
  115.     {0, _VP_BASE_PORT2,
  116.     /* channel A */  
  117.         {{0, 2, 0, _VP_BASE_CHAPORT2, EDMA_CHA_VP2EVTYA, EDMA_CHA_VP2EVTUA, 
  118.          EDMA_CHA_VP2EVTVA, _VP_YSRCA2_ADDR, _VP_CBSRCA2_ADDR, 
  119.          _VP_CRSRCA2_ADDR  }, 
  120.     /* channel B */  
  121.         {0, 2, 1, _VP_BASE_CHBPORT2, EDMA_CHA_VP2EVTYB, EDMA_CHA_VP2EVTUB, 
  122.          EDMA_CHA_VP2EVTVB,  _VP_YSRCB2_ADDR, _VP_CBSRCB2_ADDR, 
  123.          _VP_CRSRCB2_ADDR }}}
  124. };
  128. /*
  129.  *  =================== mdBindDev ============================
  130.  *  Register all external devices to video port capture driver 
  131.  */
  132. static Int mdBindDev(Ptr *devp, Int devid, Ptr devParams)
  133. {
  134.     Int portNum = devid;         
  135.     volatile Int i;
  136.     volatile Int* base = (volatile Int *)portObjs[portNum].base;                       
  137.    
  138.     assert(portNum < _VP_PORT_CNT);
  139.     base[_VP_VPCTL_OFFSET] = 
  140.              VP_VPCTL_VPRST_RESET << _VP_VPCTL_VPRST_SHIFT;
  141.     for(i = 0; i < 100000; i ++);             
  142.    
  143.     *devp = &portObjs[portNum];                                                                                           
  144.     return mdControlChan(&portObjs[portNum], VPORT_CMD_CONFIG_PORT, devParams); 
  145. }
  148. /*
  149.  *  ======== mdControlChan ========
  150.  */
  151. static Int mdControlChan(Ptr chanp, Uns cmd, Ptr args)
  152. {
  153.     Int retVal = IOM_EBADMODE;
  154.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  155.     PortObj* port = &portObjs[chan->portNum];
  157.     switch (cmd) {
  158.         case VPORT_CMD_START:
  159.         retVal = _startVPCapture(chanp);
  160.         break;
  161.         case VPORT_CMD_STOP:
  162.         retVal = _stopVPCapture(chanp);
  163.         break;
  164.         case VPORT_CMD_SET_VINTCB:
  165.         retVal = _setVIntCb(chanp, args);
  166.         break;
  167.         case VPORT_CMD_CONFIG_PORT:
  168.         retVal = _configPort(chanp, args);
  169.         break;
  170.         case VPORT_CMD_COVR_RECOVER:
  171.         retVal = _covrRecover(chanp);
  172.         break;
  173.         case VPORT_CMD_CONFIG_CHAN:
  174.         if(! (port->status & _VPORT_CFGED)) {
  175.             retVal = _configChan(chanp, args);
  176.         }
  177.         break;
  178.         default: 
  179.         if(chan->edcFxns!=INV){
  180.             retVal = chan->edcFxns->ctrl(chan->edcHandle, 
  181.                 cmd-VPORT_CMD_EDC_BASE,(Arg)args);
  182.         }else {
  183.             retVal = IOM_ENOTIMPL;
  184.         } 
  185.         break;   
  186.     }
  187.     return retVal;
  188. }              
  191. /*
  192.  *  =================== mdCreateChan ============================
  193.  *  create a capture channel
  194.  */
  195. static Int  mdCreateChan(Ptr *chanp, Ptr devp, String name, Int mode,
  196.                       Ptr chanParams, IOM_TiomCallback cbFxn, Ptr cbArg)
  197. {
  198.     Int chanNum;           
  199.     volatile Int* base;
  200.     PortObj* port;
  201.     Int retVal = IOM_COMPLETED;       
  202.      
  204.     if(mode != IOM_INPUT){
  205.         return IOM_EBADARGS;
  206.     }
  207.     if(*name ++ != '/') {
  208.         return IOM_EBADARGS;
  209.     }
  210.     chanNum = *name ++ - 'A';
  212.     assert(chanNum < _VPORT_CHAN_CNT);
  213.     
  214.     port = (PortObj *)devp;
  215.     if(port->chanObj[chanNum].edcFxns != INV) {
  216.         /* open external device */
  217.         port->chanObj[chanNum].edcHandle 
  218.            = port->chanObj[chanNum].edcFxns->open(name, (Arg)INV);
  219.     } 
  220.     if(! (port->status & _VPORT_OPENED)) {
  221.         port->status |= _VPORT_OPENED;
  222.         base = (volatile Int *)port->base;                       
  223.         
  224.         /* reset both channels */
  225.         base[_VP_VCACTL_OFFSET] |= 
  226.             VP_VCACTL_RSTCH_RESET << _VP_VCACTL_RSTCH_SHIFT;
  227.         base[_VP_VCBCTL_OFFSET] |= 
  228.             VP_VCBCTL_RSTCH_RESET << _VP_VCBCTL_RSTCH_SHIFT;
  229.     } /* if(!port->opened)  */
  230.     /* initialize the channel object */
  231.     if(! (port->chanObj[chanNum].status & _VPORT_OPENED)) {
  232.         Int j;
  233.         _VPORT_ChanObj *chan = &port->chanObj[chanNum];       
  234.         chan->status |= _VPORT_OPENED;
  235.         chan->vIntMask = 0;
  236.         QUE_new(&chan->qIn);
  237.         chan->cbFxn = cbFxn;
  238.         chan->vIntFxn = (VPORT_IntCallBack)INV;
  239.         chan->queEmpty = FALSE;   
  240.         chan->cbArg = (Arg)cbArg;
  241.         chan->mrViop = INV;
  242.         chan->packetIOM = INV;     
  243.         chan->numFrms = 0;
  244.         chan->vIntCbArg = (Int)INV;
  245.         chan->bufSz = 0;
  246.         for(j = 0; j < _VPORT_NUM_EDMA_CHANS && retVal == IOM_COMPLETED; j ++){
  247.             
  248.             if( (chan->hEdma[j] = EDMA_open(chan->edmaChanNum[j], 
  249.                 EDMA_OPEN_RESET))==EDMA_HINV
  250.             ||  (chan->hRld[4 * j] = EDMA_allocTable(-1))==EDMA_HINV
  251.             ||  (chan->hRld[4 * j + 1] = EDMA_allocTable(-1))==EDMA_HINV
  252.             ||  (chan->hRld[4 * j + 2] = EDMA_allocTable(-1))==EDMA_HINV
  253.             ||  (chan->hRld[4 * j + 3] = EDMA_allocTable(-1))==EDMA_HINV
  254.             ||  (chan->tcc[j] = EDMA_intAlloc(chan->edmaChanNum[j])) == -1){
  255.                 retVal = IOM_EALLOC;
  256.             }/* if((port->...*/ 
  257.         }/* for(j = 0; j < NUM_EDMA_CHANS; j++) {...*/
  258.         if( retVal == IOM_COMPLETED && (void *)chanParams != INV) {
  259.             retVal = mdControlChan(&port->chanObj[chanNum], 
  260.                 VPORT_CMD_CONFIG_CHAN, chanParams); 
  261.         }
  262.         if(retVal == IOM_COMPLETED) {
  263.              /* configure the channel */
  264.              *chanp = &port->chanObj[chanNum];
  265.         }else {
  266.             mdDeleteChan(&port->chanObj);
  267.             *chanp = INV;                     
  268.         }               
  269.     } /*if(!chan->opened) */
  270.     return retVal;
  271. }               
  274. /*
  275.  *  =================== mdDeleteChan ============================
  276.  *  delete the capture channel
  277.  */
  279. static Int  mdDeleteChan(Ptr chanp)
  280. {
  281.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  282.     PortObj* port = &portObjs[chan->portNum];
  283.     Int j;
  284.     volatile Int* base;
  285.     
  286.     if(chan->status & _VPORT_OPENED) {
  287.         chan->status = 0;
  288.         mdControlChan(chanp, VPORT_CMD_STOP, NULL);
  289.         for(j = 0; j < _VPORT_NUM_EDMA_CHANS; j ++) {
  290.             EDMA_disableChannel(chan->hEdma[j]);
  291.             EDMA_clearChannel(chan->hEdma[j]);
  292.             EDMA_close(chan->hEdma[j]);
  293.             EDMA_freeTable(chan->hRld[4 * j]);
  294.             EDMA_freeTable(chan->hRld[4 * j + 1]);
  295.             EDMA_freeTable(chan->hRld[4 * j + 2]);
  296.             EDMA_freeTable(chan->hRld[4 * j + 3]);
  297.             EDMA_intFree(chan->tcc[j]);
  298.         }
  299.         for(j = 0; j < chan->numFrms ; j ++) {
  300.             MEM_free(chan->segId, chan->viops[j].frame.iFrm.y1, chan->bufSz);
  301.         }        
  302.         /* close external device */
  303.         if(chan->edcFxns != INV) {
  304.             chan->edcFxns->close(chan->edcHandle);
  305.         }
  306.     }    
  307.     
  308.     if(! (port->chanObj[0].status & _VPORT_OPENED) 
  309.        && ! (port->chanObj[1].status & _VPORT_OPENED)) {
  310.         base = (volatile Int *)port->base;
  311.         /* reset both channels */
  312.         base[_VP_VCACTL_OFFSET] |= 
  313.             VP_VCACTL_RSTCH_RESET << _VP_VCACTL_RSTCH_SHIFT;
  314.         base[_VP_VCBCTL_OFFSET] |= 
  315.             VP_VCBCTL_RSTCH_RESET << _VP_VCBCTL_RSTCH_SHIFT;
  317.         /* reset video port */
  318.         base[_VP_VPCTL_OFFSET] |= 
  319.             VP_VPCTL_VPRST_RESET << _VP_VPCTL_VPRST_SHIFT;
  320.         port->status = 0;
  321.     }
  322.     return IOM_COMPLETED;
  323. }
  326. /*
  327.  *  ======== mdSubmitChan ========
  328.  */
  329. static Int  mdSubmitChan(Ptr chanp, IOM_Packet *packet)
  330. {
  332.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  333.     FVID_Frame* viop;                             
  334.     Uint32 gie = IRQ_globalDisable();
  335.     Int retVal = IOM_PENDING;  
  336.     Int offset = chan->nextEDMARlds << 1;
  337.     Bool nextViopChanged = FALSE;             
  338.     Bool notToLate = TRUE;
  339.     volatile Int* cBase = (volatile Int *)chan->base;
  340.     Int capStatReg = cBase[_VP_VCASTAT_OFFSETA];
  341.     short lineNum;
  342.     
  343.      
  344.     /* get the current line number being captured */
  345.     lineNum = (capStatReg & _VP_VCASTAT_VCYPOS_MASK)
  346.                            >> _VP_VCASTAT_VCYPOS_SHIFT;
  347.             
  348.     /* account for field/frame operation modes */ 
  349.     lineNum += chan->numLinesFld1 
  350.         * ((capStatReg & _VP_VCASTAT_VCFLD_MASK) >> _VP_VCASTAT_VCFLD_SHIFT);    
  352.     /* make sure we are not too close to the end of a frame */
  353.     notToLate = (lineNum < (chan->lastLineNum - 5));
  355.     assert(chan->status & _VPORT_READY);
  356.     if(packet->cmd != FVID_ALLOC 
  357.         && packet->cmd != FVID_FREE 
  358.         && packet->cmd != FVID_EXCHANGE){    
  359.         /* other commands not supported */
  360.         return IOM_ENOTIMPL;    
  361.     }
  362.     
  363.     if(packet->cmd != FVID_ALLOC) {/* FVID_FREE or FVID_EXCHANGE */
  364.         viop = *(void **)packet->addr; /* pointer of a video I/O packet */
  365.         if(chan->queEmpty && notToLate) {
  366.             /* don't put it into queue, update the rld register directly */
  367.             chan->nextViop = viop; 
  368.             nextViopChanged = TRUE;
  369.         } 
  370.         else {               
  371.             QUE_enqueue(&chan->qIn, (QUE_Handle)viop);    
  372.         }
  373.         chan->queEmpty = FALSE;
  374.         retVal = packet->status = IOM_COMPLETED;
  375.     }
  376.     if(packet->cmd != FVID_FREE) {/* FVID_ALLOC or FVID_EXCHANGE */
  377.         if(chan->mrViop != INV) {
  378.             /* only when there is no outstanding pending request */
  379.             if(chan->packetIOM == INV){
  380.                 if(chan->nextViop != chan->mrViop){
  381.                     *(void **)packet->addr = (void *)chan->mrViop;
  382.                     chan->mrViop = INV;
  383.                     packet->size = sizeof(FVID_Frame);
  384.                     retVal = packet->status = IOM_COMPLETED;                
  385.                 } else {
  386.                     if (notToLate) {
  387.                         *(void **)packet->addr = (void *)chan->mrViop;
  388.                         chan->mrViop = INV;
  389.                         packet->size = sizeof(FVID_Frame);
  390.                         retVal = packet->status = IOM_COMPLETED;
  391.                         /* If queue is already empty, it means the driver currently*/
  392.                         /* only owns one frame, which is the current frame. So make*/
  393.                         /* the next frame the same as the current one              */
  394.                         chan->nextViop = chan->curViop;
  395.                     } else {
  396.                         chan->mrViop = INV; /* too late, just recycle the mrViop */                    
  397.                         chan->packetIOM = packet;
  398.                         retVal = packet->status = IOM_PENDING;
  399.                     }
  400.                 }
  401.             }
  402.             else retVal = IOM_EINUSE;    
  403.         } else {
  404.             chan->packetIOM = packet;
  405.             retVal = packet->status = IOM_PENDING;
  406.         }        
  407.     }    
  408.     if(nextViopChanged) {
  409.         /* now modify the EDMA rld entries */
  410.         if(chan->mergeFlds){
  411.             EDMA_RSETH(chan->hRld[offset], DST, 
  412.                 chan->nextViop->frame.iFrm.y1);
  413.             EDMA_RSETH(chan->hRld[offset + 1], DST, 
  414.                 chan->nextViop->frame.iFrm.y2);
  415.             EDMA_RSETH(chan->hRld[4 + offset], DST, 
  416.                 chan->nextViop->frame.iFrm.cb1);     
  417.             EDMA_RSETH(chan->hRld[5 + offset], DST, 
  418.                 chan->nextViop->frame.iFrm.cb2);                         
  419.             EDMA_RSETH(chan->hRld[8 + offset], DST, 
  420.                 chan->nextViop->frame.iFrm.cr1);     
  421.             EDMA_RSETH(chan->hRld[9 + offset], DST, 
  422.                 chan->nextViop->frame.iFrm.cr2);              
  423.         } else {
  424.             EDMA_RSETH(chan->hRld[offset], DST, 
  425.                 chan->nextViop->frame.iFrm.y1);
  426.             EDMA_RSETH(chan->hRld[4 + offset], DST, 
  427.                 chan->nextViop->frame.iFrm.cb1);     
  428.             EDMA_RSETH(chan->hRld[8 + offset], DST, 
  429.                 chan->nextViop->frame.iFrm.cr1);                         
  430.         } /* if(chan->mergeFlds) */            
  431.     }    
  432.     IRQ_globalRestore(gie);
  433.     return retVal;
  434. }
  437. /*
  438.  *  ======== _captureEdmaISR ========
  439.  *  EDMA ISR
  440.  */
  441. static void captureEdmaISR(Int tcc) 
  442. {
  443.     Int i, j;
  444.     Int offset;
  445.     FVID_Frame *viop, *curViop;      
  446.     
  447.     
  448.     /* find out the source of the edma interrupt */
  449.     for(j = 0; j < _VP_PORT_CNT; j ++) {
  450.         for(i = 0; i < _VPORT_CHAN_CNT; i ++ ){ /* loop through two channels */
  451.             _VPORT_ChanObj* chan = &portObjs[j].chanObj[i];    
  452.             if((chan->status & _VPORT_READY)
  453.               && (tcc == chan->tcc[0] || tcc == chan->tcc[1])){
  455.                 /* re-sync tcc with activeEDMARlds */
  456.                 /* they may be out of sync after interrupt over-run */
  457.                 /* e.g. execution is halted at break-point */
  458.                 chan->nextEDMARlds = (tcc == chan->tcc[0]) ? 0 : 1;
  459.                 offset = chan->nextEDMARlds << 1;
  461.                 /* update the current and next viop pointers */
  462.                 curViop = chan->curViop;
  463.                 chan->curViop = chan->nextViop;             
  464.                 
  465.                 /* update the most recent viop */
  466.                 if(curViop != chan->mrViop  && chan->mrViop != INV) {
  467.                       QUE_enqueue(&chan->qIn, chan->mrViop);
  468.                 } 
  469.                 chan->mrViop = curViop;
  471.                 if((viop = (FVID_Frame *)QUE_dequeue(&chan->qIn))
  472.                     !=(FVID_Frame *)&chan->qIn) {
  473.                     /* queue IS not empty */
  474.                     chan->nextViop = viop;
  475.                 }else {
  476.                     if(chan->packetIOM == INV) {
  477.                         /* in queue is empty, but no request is pending */
  478.                         /* recycle the current VIOP back                */
  479.                         /* but still set it as the most recent VIOP     */
  480.                         chan->nextViop = curViop;
  481.                     }
  482.                     chan->queEmpty = TRUE;
  483.                 }                              
  485.                 /* call the channel's callback function */
  486.                 if(curViop != chan->curViop) {
  487.                     if(chan->packetIOM != INV) {
  488.                          /* call the channel's callback function */
  489.                          *(void **)chan->packetIOM->addr = curViop;             
  490.                          chan->packetIOM->size = sizeof(FVID_Frame);
  491.                          chan->cbFxn((Ptr)chan->cbArg, chan->packetIOM);   
  492.                          chan->packetIOM = INV;
  493.                          chan->mrViop = INV;
  494.                     }else if(chan->queEmpty){
  495.                         chan->nextViop = chan->mrViop;
  496.                     }
  497.                 }else {
  498.                     chan->mrViop = INV;
  499.                 }        
  500.                 /* Update the EDMA reload entry  */
  501.                 if(chan->mergeFlds){
  502.                     EDMA_RSETH(chan->hRld[offset], DST, 
  503.                         chan->nextViop->frame.iFrm.y1);
  504.                     EDMA_RSETH(chan->hRld[offset + 1], DST, 
  505.                         chan->nextViop->frame.iFrm.y2);
  506.                     EDMA_RSETH(chan->hRld[4 + offset], DST, 
  507.                         chan->nextViop->frame.iFrm.cb1);     
  508.                     EDMA_RSETH(chan->hRld[5 + offset], DST, 
  509.                         chan->nextViop->frame.iFrm.cb2);                         
  510.                     EDMA_RSETH(chan->hRld[8 + offset], DST, 
  511.                         chan->nextViop->frame.iFrm.cr1);     
  512.                     EDMA_RSETH(chan->hRld[9 + offset], DST, 
  513.                         chan->nextViop->frame.iFrm.cr2);                         
  514.                 }else {
  515.                     EDMA_RSETH(chan->hRld[offset], DST, 
  516.                         chan->nextViop->frame.iFrm.y1);
  517.                     EDMA_RSETH(chan->hRld[offset + 4], DST, 
  518.                         chan->nextViop->frame.iFrm.cb1);
  519.                     EDMA_RSETH(chan->hRld[offset + 8], DST, 
  520.                         chan->nextViop->frame.iFrm.cr1);
  521.                 }/* if(chan->mergeFlds) {*/
  524.             }    
  525.         }
  526.     }
  527. }
  530. /*
  531.  *  ======== _configCh ========
  532.  *  configure video port channel settings
  533.  */
  534. static Int _configCh(
  535.         Ptr                 chanp, 
  536.         VPORTCAP_Params  *params
  537.         )
  538. {
  539.     _VPORT_ChanObj* chan= (_VPORT_ChanObj *)chanp;
  540.     volatile Int vpCtl, vcCtl, fld1Strt, fld2Strt, fld1Stop, fld2Stop;
  541.     volatile Int* base = (volatile Int *)chan->base;                         
  542.     Int retVal = IOM_COMPLETED;
  543.     Int numPixels, numLines, numCPixels;  
  544.     
  545.     
  546.     if(chan->status & _VPORT_OPENED) {
  547.         /* configure channel A capture settings  */
  548.         vcCtl = VP_VCACTL_RMK(0,1,0,params->fldInv, 
  549.             params->extCtl, params->fldDect, params->vCtRst,
  550.             params->hCtRst, 0, params->bpk10Bit, 0, 0, 
  551.             params->resmpl,params->scale,1,
  552.             ((params->fldOp & 4) >> 2), 
  553.             ((params->fldOp & 2) >> 1), 
  554.             (params->fldOp & 1), 
  555.             params->cmode);
  557.         fld1Strt = params->fldXStrt1 + (params->fldYStrt1 << 16);
  558.         fld1Stop = params->fldXStop1 + (params->fldYStop1 << 16);
  559.         fld2Strt = params->fldXStrt2 + (params->fldYStrt2 << 16);
  560.         fld2Stop = params->fldXStop2 + (params->fldYStop2 << 16);
  561.         if(params->fldOp == VPORT_FLDOP_FRAME) {
  562.             assert(params->fldXStop1 == params->fldXStop2);
  563.             assert(params->fldXStrt1 == params->fldXStrt2);
  564.         }   
  565.         base[_VP_VCACTL_OFFSETA]   = vcCtl;
  566.         base[_VP_VCASTRT1_OFFSETA] = fld1Strt;
  567.         base[_VP_VCASTOP1_OFFSETA] = fld1Stop;
  568.         base[_VP_VCASTRT2_OFFSETA] = fld2Strt;
  569.         base[_VP_VCASTOP2_OFFSETA] = fld2Stop;
  570.         numPixels = params->fldXStop1 - params->fldXStrt1 + 1;/* line size */
  571.         numLines = 0;
  572.         
  573.         if(params->fldOp != VPORT_FLDOP_FLD2){
  574.             numLines += params->fldYStop1 - params->fldYStrt1 + 1;
  575.         }
  576.         chan->numLinesFld1 = numLines;
  577.         
  578.         if(params->fldOp == VPORT_FLDOP_FLD2
  579.           || params->fldOp == VPORT_FLDOP_FRAME){
  580.             numLines += params->fldYStop2 - params->fldYStrt2 + 1;
  581.         }
  582.         chan->resmpl = params->resmpl;
  583.         chan->scale = params->scale;
  584.         chan->numLines = numLines;
  585.         numPixels >>= params->scale;
  586.         numCPixels = numPixels >> 1;
  587.         /* set both field1 and field2 threshold to the line size */
  588.         chan->numPixels = numPixels;
  589.         chan->lastLineNum = chan->numLines;        
  590.         if(params->cmode & _VPORT_MASK_10BIT){
  591.             /* 10-bit BT.656 or 20-bit Y/C mode */
  592.             if( params->bpk10Bit == VPORTCAP_BPK_10BIT_ZERO_EXTENDED
  593.              || params->bpk10Bit == VPORTCAP_BPK_10BIT_SIGN_EXTENDED){
  594.                 chan->yPitch = (numPixels *2 + 7) & (~ 7);
  595.                 chan->cPitch = (numCPixels *2 + 7) & (~ 7);
  596.             }else {
  597.                 chan->yPitch = (numPixels * 4 / 3 + 7) & (~ 7);
  598.                 chan->cPitch = (numCPixels* 4 / 3 + 7) & (~ 7);
  599.             }
  600.         } else {/* 8-bit BT.656 or 16-bit Y/C mode */
  601.             chan->yPitch = (numPixels + 7) & (~ 7);
  602.             chan->cPitch = (numCPixels + 7) & (~ 7);
  603.         }     
  604.         chan->yThrld = params->thrld;
  605.         if(params->mergeFlds && params->fldOp == VPORT_FLDOP_FRAME) { 
  606.             /* merge field comments */
  607.             /* frame capture and merge 2 fields into one frame */
  608.             /* set threshold is same as line size */
  609.             chan->yThrld = chan->yPitch >> 3;
  610.             chan->numEventsFld1 = chan->numLinesFld1;
  611.             chan->numEvents = chan->numLines;
  612.             chan->mergeFlds = TRUE;  
  613.         }else {            
  614.             assert(((chan->yPitch*chan->numLinesFld1) / (chan->yThrld << 3)) 
  615.                 *(chan->yThrld << 3) == (chan->yPitch * chan->numLinesFld1));
  616.             assert(((chan->yPitch * chan->numLines) / (chan->yThrld << 3)) 
  617.                 *(chan->yThrld << 3) == (chan->yPitch * chan->numLines));
  618.             chan->numEventsFld1 = 
  619.                 chan->yPitch * chan->numLinesFld1 / (chan->yThrld << 3);
  620.             chan->numEvents = 
  621.                 chan->yPitch * chan->numLines / (chan->yThrld << 3);
  622.             chan->mergeFlds = FALSE;
  623.         }            
  625.         chan->cThrld = (chan->yThrld + 1) >> 1;
  627.         base[_VP_VCATHRLD_OFFSETA] = VP_VCATHRLD_RMK(chan->yThrld,chan->yThrld);
  628.         base[_VP_VCAEVTCT_OFFSETA] = VP_VCAEVTCT_RMK(
  629.             (chan->numEvents-chan->numEventsFld1), chan->numEventsFld1 );  
  630.         
  631.         chan->status|=_VPORT_CFGED;
  632.         retVal = IOM_COMPLETED;
  633.     }    
  634.     return retVal;
  636. }
  639. /*
  640.  *  ======== _configChan ========
  641.  *  configure channel settings
  642.  */
  643. static Int _configChan(Ptr chanp, Ptr args)
  644. {
  645.     VPORTCAP_Params*   params = (VPORTCAP_Params*)args; 
  646.     
  647.     
  648.     /* configure video port channel A/B control register */
  649.     _configCh(chanp, params);
  651.     /* configure EDMA and frame buffer */
  652.     _configTransfer(chanp, params);
  653.     return IOM_COMPLETED;
  654. }
  657. /*
  658.  *  ======== _configPort ========
  659.  *  configure port level registers
  660.  */
  661. static Int _configPort(Ptr chanp, Ptr args)
  662. {
  663.     PortObj* port = (PortObj *)chanp;
  664.     volatile Int *base = (volatile Int *)port->base; 
  665.     /* configure video port control register */
  666.     VPORT_PortParams* portParams = (VPORT_PortParams*)args; 
  667.     
  668.     
  669.     /* enable video port */
  670.     base[_VP_PCR_OFFSET] |= VP_PCR_PEREN_ENABLE << _VP_PCR_PEREN_SHIFT;
  671.                 
  672.     /* reset video port */
  673.     base[_VP_VPCTL_OFFSET] |= 
  674.         VP_VPCTL_VPRST_RESET << _VP_VPCTL_VPRST_SHIFT;
  676.     base[_VP_VPCTL_OFFSET] = VP_VPCTL_RMK(0,0,0,portParams->vc3Polarity,
  677.         portParams->vc2Polarity,portParams->vc1Polarity,0,0,
  678.         portParams->dualChanEnable);
  679.     
  680.     /* enable video port */
  681.     base[_VP_VPCTL_OFFSET] |= (VP_VPCTL_VPHLT_CLEAR << _VP_VPCTL_VPHLT_SHIFT);
  682.     port->chanObj[0].edcFxns = portParams->edcTbl[0];
  683.     port->chanObj[1].edcFxns = portParams->edcTbl[1];
  684.     
  685.     IRQ_clear(IRQ_EVT_EDMAINT);
  686.     return IOM_COMPLETED;
  688. }
  691. /*
  692.  *  ======== _configTransfer ========
  693.  *  configure channel EDMA settings
  694.  */
  695. static Int _configTransfer(
  696.         Ptr                 chanp, 
  697.         VPORTCAP_Params  *params
  698.         )
  699. {
  700.     _VPORT_ChanObj* chan = (_VPORT_ChanObj *)chanp;
  701.     Int i;
  702.     EDMA_Config  cfgEdma;
  703.     Int thrld;
  704.     Int8* curAddr;
  705.     
  706.     if(chan->status & _VPORT_CFGED) {
  707.      
  708.         assert(params->numFrmBufs >= 2 && params->numFrmBufs 
  709.                 <= VPORT_MAX_NUM_FRMBUFS);
  710.         QUE_new(&chan->qIn);     
  711.         chan->queEmpty = FALSE;   
  712.         chan->mrViop = INV;
  713.         chan->packetIOM = INV;     
  714.         chan->segId = params->segId;
  715.         
  716.         EDMA_intDisable(chan->tcc[0]);
  717.         EDMA_intDisable(chan->tcc[1]);
  718.         
  719.         if(chan->numFrms == 0) {
  720.             chan->numFrms = params->numFrmBufs;
  722.             /* allocate frame buffer */
  723.             chan->bufSz = chan->yPitch * chan->numLines 
  724.                   + chan->cPitch * chan->numLines * 2;
  725.             for(i = 0; i < chan->numFrms; i ++) {                    
  726.                 if((curAddr = MEM_calloc(params->segId,chan->bufSz, 
  727.                     params->alignment)) == MEM_ILLEGAL){
  728.                     return IOM_EALLOC;
  729.                 }    
  730.                 /* field 1 */
  731.                 chan->viops[i].frame.iFrm.y1 = curAddr;
  732.                 curAddr += chan->numLines*chan->yPitch;
  733.                 chan->viops[i].frame.iFrm.cb1 = curAddr;
  734.                 curAddr += chan->numLines*chan->cPitch;
  735.                 chan->viops[i].frame.iFrm.cr1 = curAddr;
  736.                 curAddr += chan->numLines*chan->cPitch;
  737.                 /* field 2 */    
  738.                 if(params->fldOp == VPORT_FLDOP_FLD2) {
  739.                     chan->viops[i].frame.iFrm.y2 = 
  740.                         chan->viops[i].frame.iFrm.y1;
  741.                     chan->viops[i].frame.iFrm.cb2 = 
  742.                         chan->viops[i].frame.iFrm.cb1;
  743.                     chan->viops[i].frame.iFrm.cr2 = 
  744.                         chan->viops[i].frame.iFrm.cr1;
  745.                 }
  746.                 else if(! chan->mergeFlds) {
  747.                     chan->viops[i].frame.iFrm.y2 = 
  748.                       chan->viops[i].frame.iFrm.y1
  749.                         + chan->numLinesFld1*chan->yPitch;
  750.                     chan->viops[i].frame.iFrm.cb2 = 
  751.                       chan->viops[i].frame.iFrm.cb1
  752.                         + (chan->numLinesFld1*chan->cPitch);
  753.                     chan->viops[i].frame.iFrm.cr2 = 
  754.                       chan->viops[i].frame.iFrm.cr1
  755.                         + (chan->numLinesFld1*chan->cPitch);
  756.                 }else {
  757.                     chan->viops[i].frame.iFrm.y2 = 
  758.                       chan->viops[i].frame.iFrm.y1 + chan->yPitch;
  759.                     chan->viops[i].frame.iFrm.cb2 = 
  760.                       chan->viops[i].frame.iFrm.cb1 + chan->cPitch;
  761.                     chan->viops[i].frame.iFrm.cr2 = 
  762.                       chan->viops[i].frame.iFrm.cr1 + chan->cPitch;            
  763.                 }    
  764.                 if(i > 1) {
  765.                     /* don't put the first 2 viop into the queue */
  766.                     QUE_enqueue(&chan->qIn, (QUE_Handle)&chan->viops[i]);
  767.                 }
  769.             }
  770.         }    
  771.         CACHE_clean(CACHE_L2ALL, 0, 0);
  772.         chan->curViop = &chan->viops[0];
  773.         chan->nextViop = &chan->viops[1]; 
  774.         for(i = 0; i < _VPORT_NUM_EDMA_CHANS; i ++) {
  775.             Int optFld1 = EDMA_OPT_RMK(
  776.                 params->edmaPri,
  777.                 EDMA_OPT_ESIZE_32BIT,
  778.                 EDMA_OPT_2DS_NO,
  779.                 EDMA_OPT_SUM_NONE,
  780.                 EDMA_OPT_2DD_YES,
  781.                 EDMA_OPT_DUM_INC,
  782.                 EDMA_OPT_TCINT_NO,
  783.                 EDMA_OPT_TCC_OF(0), 
  784.                 EDMA_OPT_TCCM_OF(0),
  785.                 EDMA_OPT_ATCINT_NO,    
  786.                 EDMA_OPT_ATCC_DEFAULT,
  787.                 EDMA_OPT_PDTS_DISABLE,
  788.                 EDMA_OPT_PDTD_DISABLE,
  789.                 EDMA_OPT_LINK_YES,
  790.                 EDMA_OPT_FS_NO
  791.             );
  792.     
  793.             Int optFld2a = EDMA_OPT_RMK(
  794.                 params->edmaPri,
  795.                 EDMA_OPT_ESIZE_32BIT,
  796.                 EDMA_OPT_2DS_NO,
  797.                 EDMA_OPT_SUM_NONE,
  798.                 EDMA_OPT_2DD_YES,
  799.                 EDMA_OPT_DUM_INC,
  800.                 (i == 0 ? EDMA_OPT_TCINT_YES:EDMA_OPT_TCINT_NO),
  801.                 EDMA_OPT_TCC_OF(i == 0 ? chan->tcc[0] & 0x0f : 0), 
  802.                 EDMA_OPT_TCCM_OF(i == 0 ? chan->tcc[0] >> 4 : 0),
  803.                 EDMA_OPT_ATCINT_NO,    
  804.                 EDMA_OPT_ATCC_DEFAULT,
  805.                 EDMA_OPT_PDTS_DISABLE,
  806.                 EDMA_OPT_PDTD_DISABLE,
  807.                 EDMA_OPT_LINK_YES,
  808.                 EDMA_OPT_FS_NO
  809.             );
  810.             Int optFld2b = EDMA_OPT_RMK(
  811.                 params->edmaPri,
  812.                 EDMA_OPT_ESIZE_32BIT,
  813.                 EDMA_OPT_2DS_NO,
  814.                 EDMA_OPT_SUM_NONE,
  815.                 EDMA_OPT_2DD_YES,
  816.                 EDMA_OPT_DUM_INC,
  817.                 (i == 0 ? EDMA_OPT_TCINT_YES:EDMA_OPT_TCINT_NO),
  818.                 EDMA_OPT_TCC_OF(i == 0 ? chan->tcc[1] & 0x0f : 0), 
  819.                 EDMA_OPT_TCCM_OF(i == 0 ? chan->tcc[1] >> 4 : 0),
  820.                 EDMA_OPT_ATCINT_NO,    
  821.                 EDMA_OPT_ATCC_DEFAULT,
  822.                 EDMA_OPT_PDTS_DISABLE,
  823.                 EDMA_OPT_PDTD_DISABLE,
  824.                 EDMA_OPT_LINK_YES,
  825.                 EDMA_OPT_FS_NO
  826.             );
  828.             thrld = (i == 0) ? chan->yThrld : chan->cThrld;
  829.             cfgEdma.src = EDMA_SRC_RMK(chan->edmaAddr[i]);
  830.             if(chan->mergeFlds) {
  831.                 /* to merge the two fields together */
  832.                 /* EDMA is configured to transfer only field 1 initially */
  833.                 /* line pitch is twice the line size */
  834.                 /* this requires that the threlhold is the same as line size */
  835.                 
  836.                 /* first field */
  837.                 cfgEdma.cnt = 
  838.                   EDMA_CNT_RMK((chan->numEventsFld1) - 1, (thrld << 1));
  839.                 cfgEdma.idx = EDMA_IDX_RMK(thrld << 4, 0);
  840.     
  841.                 /* hard code the first two frames as current and reload buffers */                
  842.                 /* first field */
  843.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i + 1]);
  844.                 cfgEdma.opt = optFld1;
  845.                 cfgEdma.dst = 
  846.                   EDMA_DST_RMK(*((Int *)(&chan->viops[0].frame.iFrm.y1) + i));
  847.                 EDMA_config(chan->hEdma[i], &cfgEdma);
  848.                 EDMA_config(chan->hRld[4 * i], &cfgEdma); 
  849.                 cfgEdma.dst = 
  850.                   EDMA_DST_RMK(*((Int *)(&chan->viops[1].frame.iFrm.y1) + i));
  851.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i + 3]);
  852.                 EDMA_config(chan->hRld[4 * i + 2], &cfgEdma);
  854.                 /* second field */
  855.                 cfgEdma.opt = optFld2a;
  856.                 cfgEdma.cnt = 
  857.                   EDMA_CNT_RMK((chan->numEvents-chan->numEventsFld1) - 1, 
  858.                    (thrld << 1));
  859.                 cfgEdma.dst = 
  860.                   EDMA_DST_RMK(*((Int *)(&chan->viops[0].frame.iFrm.y2) + i));
  861.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i + 2]);
  862.                 EDMA_config(chan->hRld[4 * i + 1], &cfgEdma); 
  863.                 cfgEdma.opt = optFld2b;
  864.                 cfgEdma.dst = 
  865.                   EDMA_DST_RMK(*((Int *)(&chan->viops[1].frame.iFrm.y2) + i));
  866.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i]);
  867.                 EDMA_config(chan->hRld[4 * i + 3], &cfgEdma);
  868.                 
  869.             }else {/* if fields are not merged, configure EDMA to transfer */
  870.                    /* for both field1 and field 2                          */
  871.                    /* the line pitch is just the line size                 */
  872.                 cfgEdma.opt = optFld2a;
  873.                 cfgEdma.cnt = EDMA_CNT_RMK((chan->numEvents) - 1, (thrld << 1));
  874.                 cfgEdma.idx = EDMA_IDX_RMK(thrld << 3, 0);
  875.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i + 2]);
  876.                 /* hard code the first and second frame buffer as current  */
  877.                 /* and reload buffers */
  878.                 cfgEdma.dst = EDMA_DST_RMK(
  879.                     *((Int *)(&chan->viops[0].frame.iFrm.y1) + i));
  880.                 EDMA_config(chan->hEdma[i], &cfgEdma);
  881.                 EDMA_config(chan->hRld[4 * i], &cfgEdma);
  883.                 cfgEdma.opt = optFld2b;
  884.                 cfgEdma.rld = EDMA_RLD_RMK(0, chan->hRld[4 * i]);
  885.                 cfgEdma.dst = EDMA_DST_RMK(
  886.                     *((Int *)(&chan->viops[1].frame.iFrm.y1) + i));
  887.                 EDMA_config(chan->hRld[4 * i + 2], &cfgEdma);
  888.             }
  889.         }
  890.         chan->nextEDMARlds = 1;        
  891.         /* enable EDMA channel */
  892.         /*
  893.          * The EDMA interrupt dispatcher will be called by the
  894.          * BIOS HWI interrupt dispatcher.
  895.          */
  896.         IRQ_map(IRQ_EVT_EDMAINT, params->irqId);
  897.         HWI_dispatchPlug(params->irqId, (Fxn)EDMA_intDispatcher, -1, NULL);
  898.         
  899.         EDMA_intClear(chan->tcc[0]);
  900.         EDMA_intHook(chan->tcc[0], captureEdmaISR);       
  901.         EDMA_intEnable(chan->tcc[0]);
  902.         EDMA_intClear(chan->tcc[1]);
  903.         EDMA_intHook(chan->tcc[1], captureEdmaISR);       
  904.         EDMA_intEnable(chan->tcc[1]);
  905.         for(i = 0; i < _VPORT_NUM_EDMA_CHANS; i ++) {
  906.             EDMA_disableChannel(chan->hEdma[i]);
  907.             EDMA_clearChannel(chan->hEdma[i]);
  908.             EDMA_enableChannel(chan->hEdma[i]);
  909.         }    
  910.         chan->status |= _VPORT_READY;
  911.         IRQ_enable(IRQ_EVT_EDMAINT);
  912.         
  913.     }   
  914.     return IOM_COMPLETED;
  916. }
  918. /*
  919.  *  ======== _covrRecover ========
  920.  *  force recover from FIFO over-run
  921.  */
  922. static Int _covrRecover(Ptr chanp)
  923. {
  924.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  925.     PortObj* port = &portObjs[chan->portNum];
  926.     volatile Int *base = (volatile Int *)port->base;
  927.     volatile Int *cbase = (volatile Int *)chan->base;    
  928.     Int numEvents;
  929.     volatile Int i;                                            
  930.     
  931.     
  932.     /* disable over-run interrupt */
  933.     base[_VP_VPIE_OFFSET] &= ~(_VP_VPIE_COVRA_MASK<<(chan->chanNum*16));
  934.     /* block capture events */
  935.     cbase[_VP_VCACTL_OFFSETA] |= _VP_VCACTL_BLKCAP_MASK;
  937.     /* Disable the edmas before settings them up */
  938.     EDMA_intDisable(chan->tcc[0]);
  939.     EDMA_intDisable(chan->tcc[1]);
  940.     for(i = 0; i < _VPORT_NUM_EDMA_CHANS; i ++) {
  941.         EDMA_disableChannel(chan->hEdma[i]);
  942.         EDMA_clearChannel(chan->hEdma[i]);
  943.     }
  944.     if(chan->mergeFlds) {
  945.         numEvents = chan->numEventsFld1;        
  946.     } else {
  947.         numEvents = chan->numEvents;
  948.     }
  950.     /* set up DMA parameters again */
  951.     EDMA_RSETH(chan->hEdma[0], DST, chan->curViop->frame.iFrm.y1);
  952.     EDMA_RSETH(chan->hEdma[1], DST, chan->curViop->frame.iFrm.cb1);
  953.     EDMA_RSETH(chan->hEdma[2], DST, chan->curViop->frame.iFrm.cr1);
  954.     EDMA_RSETH(chan->hEdma[0], CNT, EDMA_CNT_RMK(numEvents - 1, 
  955.         (chan->yThrld << 1)));
  956.     EDMA_RSETH(chan->hEdma[1], CNT, EDMA_CNT_RMK(numEvents - 1, 
  957.         (chan->cThrld << 1)));
  958.     EDMA_RSETH(chan->hEdma[2], CNT, EDMA_CNT_RMK(numEvents - 1, 
  959.         (chan->cThrld<<1)));
  961.     /* enable the edma events again before settings them up */
  962.     EDMA_intEnable(chan->tcc[0]);
  963.     EDMA_intEnable(chan->tcc[1]);
  964.     for(i = 0;i < 3;i ++) {
  965.         EDMA_enableChannel(chan->hEdma[i]);
  966.     }
  967.     /* delay */
  968.     for(i = 0; i < 100000; i ++);
  970.     /* clear any pending over-run interrupt */
  971.     if(chan->chanNum == 0) {
  972.         base[_VP_VPIS_OFFSET] |= _VP_VPIS_COVRA_MASK;
  973.     }else {
  974.         base[_VP_VPIS_OFFSET] |= _VP_VPIS_COVRB_MASK;
  975.     }    
  976.     /* enable event generation */
  977.     cbase[_VP_VCACTL_OFFSETA] &= ~(_VP_VCACTL_BLKCAP_MASK);
  979.     /* enable over-run interrupt */
  980.     base[_VP_VPIE_OFFSET] |= _VP_VPIE_COVRA_MASK << (chan->chanNum * 16);
  982.     return IOM_COMPLETED;
  983. }
  986. /*
  987.  *  ======== _setVIntCb ========
  988.  *  setup video port interrupt call-back
  989.  */
  990. static Int _setVIntCb(Ptr chanp, Ptr args)
  991. {      
  992.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  993.     PortObj* port = &portObjs[chan->portNum];
  994.     volatile Int *base = (volatile Int *)port->base;
  995.     volatile Int *cBase = (volatile Int *)chan->base;
  996.     VPORT_VIntCbParams* vIntCbParams = (void *)args;
  997.     Int mask = vIntCbParams->vIntMask;
  998.     Uns vif2 = 0, vInt2 = 0, vif1 = 0, vInt1 = 0, fscl2 = 0;
  999.     
  1000.     
  1001.     /* check to see if vertical interrupt is enabled */
  1002.     if(mask & VPORT_INT_VINT1) {
  1003.         vif1 = 1;
  1004.         vInt1 = vIntCbParams->vIntLine;
  1005.     }
  1006.     if(mask & VPORT_INT_VINT2) {
  1007.         vif2 = 1;
  1008.         vInt2 = vIntCbParams->vIntLine;    
  1009.     }
  1010.     fscl2 = vif2 & (~ vif1);
  1011.     /* setup vertical interrupt */
  1012.     cBase[_VP_VCAVINT_OFFSETA] = VP_VCAVINT_RMK(vif2,fscl2, 
  1013.         vInt2, vif1, vInt1);
  1014.     
  1015.     if(chan->chanNum == 1) {
  1016.         mask <<= 16;    /* channel B */
  1017.     }
  1018.     chan->vIntMask = mask;
  1019.     if(mask) {
  1020.         mask |= 1; /* turn on video port interrupt */
  1021.         IRQ_map(IRQ_EVT_VINT0 + chan->portNum, vIntCbParams->irqId);    
  1022.         HWI_dispatchPlug(vIntCbParams->irqId, (Fxn)captureISR, -1, NULL);
  1023.         IRQ_disable(IRQ_EVT_VINT0 + chan->portNum);
  1024.         IRQ_clear(IRQ_EVT_VINT0 + chan->portNum);
  1025.     }
  1026.     base[_VP_VPIE_OFFSET] |= mask;  /* register write */    
  1027.     chan->vIntFxn = vIntCbParams->vIntCbFxn;    
  1028.     chan->vIntCbArg = vIntCbParams->cbArg;
  1029.     return IOM_COMPLETED;   
  1030. }      
  1031. static void _delay(Int delayTime)
  1032. {
  1033.     asm("loop1: BDEC loop1, A4");
  1034.     asm(" NOP 5");
  1036. }
  1038. /*
  1039.  *  ======== _startVPCapture ========
  1040.  *  start video port capture operation
  1041.  */
  1042. static Int _startVPCapture(Ptr chanp)
  1043. {
  1044. //    volatile int i = 0;
  1045. //    volatile int j = 0;
  1046. //    volatile int k = 0;
  1047.     
  1048.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  1049.     PortObj* port = &portObjs[chan->portNum];
  1050.     volatile Int *base = (volatile Int *)port->base;
  1051.     volatile Int *cbase = (volatile Int *)chan->base;    
  1053.     /* enable channel */
  1054.     cbase[_VP_VCACTL_OFFSETA] |= VP_VCACTL_VCEN_ENABLE << _VP_VCACTL_VCEN_SHIFT;
  1056.     _delay(20000000);
  1057.     /* clear the block capture event mask bit to enable */
  1058.     /* generating capture events                        */
  1059. cbase[_VP_VCACTL_OFFSETA] &= ~ (_VP_VCACTL_BLKCAP_MASK);
  1061. //test
  1062. /* while((base[10]&0x00000fff)!=0x000007fc)
  1063. {
  1064. i++;
  1065. }
  1066. j = i;
  1067. while((base[10]&0x00000fff)!=0x00000400)
  1068. {
  1069. i++;
  1070. }
  1071. k = i;
  1072. while((base[10]&0x00000fff)!=0x00000400)
  1073. {
  1074. i++;
  1075. }
  1076. */
  1077. /* while((cbase[_VP_VCASTAT_OFFSETA]&0x0FFF0000)!=0x01080000)
  1078. {
  1079. i++;
  1080. }
  1081. */
  1083. // _delay(20000000);
  1084.     /* enable interrupt generation in video port level */
  1087.     base[_VP_VPIE_OFFSET] |= VP_VPIE_VIE_ENABLE << _VP_VPIE_VIE_SHIFT;
  1088.     base[_VP_VPIS_OFFSET] |= 0XFFFFFFFF;
  1091.     /* clear any pending video port interrupt */
  1092.     IRQ_clear(IRQ_EVT_VINT0 + chan->portNum);
  1093.     /* enable corresponding video port interrupt in chip-level*/
  1094.     IRQ_enable(IRQ_EVT_VINT0 + chan->portNum);
  1095.     
  1096.     return IOM_COMPLETED;
  1097. }
  1099. /*
  1100.  *  ======== _stopVPCapture ========
  1101.  *  stop video port capture operation
  1102.  */
  1103. static Int _stopVPCapture(Ptr chanp)
  1104. {
  1105.     _VPORT_ChanObj* chan = (_VPORT_ChanObj* )chanp;
  1106.     PortObj* port = &portObjs[chan->portNum];
  1107.     volatile Int *cbase = (volatile Int *)chan->base;    
  1108.     volatile Int *base = (volatile Int *)port->base;
  1110.     /* block events generation */
  1111.     cbase[_VP_VCACTL_OFFSETA] &= (_VP_VCACTL_BLKCAP_MASK);
  1113.     /* disable channel */
  1114.     cbase[_VP_VCACTL_OFFSETA] &= 
  1115.         ~ (VP_VCACTL_VCEN_ENABLE << _VP_VCACTL_VCEN_SHIFT);
  1117.     /* disable interrupt generation in video port level */
  1118.     base[_VP_VPIE_OFFSET] &= ~ (VP_VPIE_VIE_ENABLE << _VP_VPIE_VIE_SHIFT);
  1119.     base[_VP_VPIS_OFFSET] |= 0XFFFFFFFF;
  1120.     
  1121.     /* disble corresponding video port interrupt in chip-level*/
  1122.     IRQ_disable(IRQ_EVT_VINT0 + chan->portNum);
  1124.     /* clear any pending video port interrupt */
  1125.     IRQ_clear(IRQ_EVT_VINT0 + chan->portNum);
  1126.     
  1127.     EDMA_intDisable(chan->tcc[0]);
  1128.     EDMA_intClear(chan->tcc[0]);
  1130.     EDMA_intDisable(chan->tcc[1]);
  1131.     EDMA_intClear(chan->tcc[1]);
  1133.     return IOM_COMPLETED;
  1134. }
  1138. /*
  1139.  *  ======== captureISR ========
  1140.  */
  1141. static void captureISR(Int portNum)
  1142. {
  1143.     volatile Int *base =  
  1144.         (volatile Int *)portObjs[portNum].base;
  1145.     Int vpis = base[_VP_VPIS_OFFSET];
  1146.     Int mask = vpis;
  1147.     _VPORT_ChanObj* chanObjs = portObjs[portNum].chanObj;
  1148.         
  1149.     if(vpis & chanObjs[0].vIntMask && chanObjs[0].vIntFxn != INV) {
  1150.         chanObjs[0].vIntFxn(chanObjs[0].vIntCbArg, vpis);
  1151.         mask &=  chanObjs[0].vIntMask;
  1152.     }else if(vpis & chanObjs[1].vIntMask && chanObjs[1].vIntFxn != INV) {
  1153.         chanObjs[1].vIntFxn(chanObjs[1].vIntCbArg, (vpis >> 16));
  1154.         mask &=  chanObjs[1].vIntMask;
  1155.     }
  1156.     /* clear interrupts that has been handled */
  1157.     base[_VP_VPIS_OFFSET] |= mask;
  1158. }