dm642init.asm
上传用户：dahaojd
上传日期：2008-01-29
资源大小：14357k
文件大小：23k
- ;******************************************************************************
- ;* TMS320C6x C/C++ Codegen PC Version 4.36 *
- ;* Date/Time created: Wed Mar 22 15:36:30 2006 *
- ;******************************************************************************
- ;******************************************************************************
- ;* GLOBAL FILE PARAMETERS *
- ;* *
- ;* Architecture : TMS320C64xx *
- ;* Optimization : Enabled at level 3 *
- ;* Optimizing for : Speed *
- ;* Based on options: -o3, no -ms *
- ;* Endian : Little *
- ;* Interrupt Thrshld : Disabled *
- ;* Memory Model : Large *
- ;* Calls to RTS : Far *
- ;* Pipelining : Enabled *
- ;* Speculative Load : Enabled *
- ;* Memory Aliases : Presume not aliases (optimistic) *
- ;* Debug Info : No Debug Info *
- ;* *
- ;******************************************************************************
- .asg A15, FP
- .asg B14, DP
- .asg B15, SP
- .global $bss
- .sect ".cinit"
- .align 8
- .field IR_1,32
- .field _LinkStr+0,32
- .field SL1,32 ; _LinkStr[0] @ 0
- .field SL2,32 ; _LinkStr[1] @ 32
- .field SL3,32 ; _LinkStr[2] @ 64
- .field SL4,32 ; _LinkStr[3] @ 96
- .field SL5,32 ; _LinkStr[4] @ 128
- IR_1: .set 20
- .sect ".text"
- _LinkStr: .usect ".far",20,8
- _bMacAddr: .usect ".far",8,8
- ; c:tic6000cgtoolsbinopt6x.exe -t -DI0 -v6400 -q -O3 C:DOCUME~1ZHAOQI~1LOCALS~1TempTI2720_2 C:DOCUME~1ZHAOQI~1LOCALS~1TempTI2720_5 -w C:/ICETEK-DM642-C V2.22/jpeg_motion/obj/
- .sect ".text"
- .global _dm642_init
- ;******************************************************************************
- ;* FUNCTION NAME: _dm642_init *
- ;* *
- ;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
- ;* B7,B8,B9,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
- ;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
- ;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
- ;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,B0,B1,B2,B3,B4,B5,B6, *
- ;* B7,B8,B9,SP,A16,A17,A18,A19,A20,A21,A22,A23,A24, *
- ;* A25,A26,A27,A28,A29,A30,A31,B16,B17,B18,B19,B20, *
- ;* B21,B22,B23,B24,B25,B26,B27,B28,B29,B30,B31 *
- ;* Local Frame Size : 0 Args + 0 Auto + 4 Save = 4 byte *
- ;******************************************************************************
- _dm642_init:
- ;** --------------------------------------------------------------------------*
- MVKL .S1 0x1848200,A3 ; |350|
- MVKH .S1 0x1848200,A3 ; |350|
- LDW .D1T1 *A3,A3 ; |350|
- MVKL .S2 0x1848200,B4 ; |350|
- MVKL .S2 0x1848200,B5 ; |351|
- MVKH .S2 0x1848200,B4 ; |350|
- MVKH .S2 0x1848200,B5 ; |351|
- OR .D1 1,A3,A3 ; |350|
- STW .D2T1 A3,*B4 ; |350|
- LDW .D2T2 *B5,B4 ; |351|
- NOP 3
- STW .D2T2 B3,*SP--(8) ; |38|
- AND .D2 1,B4,B0 ; |351|
- [ B0] B .S1 L4 ; |351|
- [!B0] MVKL .S1 0x1848200,A3 ; |351| (P) <0,0>
- [!B0] MVKH .S1 0x1848200,A3 ; |351| (P) <0,1>
- [ B0] MVKL .S1 0x1848204,A3 ; |350|
- || [!B0] LDW .D1T1 *A3,A4 ; |351| (P) <0,2> ^
- [ B0] MVKH .S1 0x1848204,A3 ; |350|
- [ B0] LDW .D1T1 *A3,A3 ; |350|
- ; BRANCH OCCURS ; |351|
- ;** --------------------------------------------------------------------------*
- MVK .D2 0x1,B0
- NOP 1
- AND .D1 1,A4,A0 ; |351| (P) <0,7> ^
- || MVKL .S1 0x1848200,A3 ; |351| (P) <1,0>
- ;*----------------------------------------------------------------------------*
- ;* SOFTWARE PIPELINE INFORMATION
- ;*
- ;* Loop source line : 351
- ;* Loop closing brace source line : 351
- ;* Known Minimum Trip Count : 1
- ;* Known Max Trip Count Factor : 1
- ;* Loop Carried Dependency Bound(^) : 7
- ;* Unpartitioned Resource Bound : 2
- ;* Partitioned Resource Bound(*) : 2
- ;* Resource Partition:
- ;* A-side B-side
- ;* .L units 0 0
- ;* .S units 2* 1
- ;* .D units 1 0
- ;* .M units 0 0
- ;* .X cross paths 0 0
- ;* .T address paths 1 0
- ;* Long read paths 0 0
- ;* Long write paths 0 0
- ;* Logical ops (.LS) 0 0 (.L or .S unit)
- ;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
- ;* Bound(.L .S .LS) 1 1
- ;* Bound(.L .S .D .LS .LSD) 2* 1
- ;*
- ;* Searching for software pipeline schedule at ...
- ;* ii = 7 Schedule found with 3 iterations in parallel
- ;*
- ;* Register Usage Table:
- ;* +-----------------------------------------------------------------+
- ;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
- ;* |00000000001111111111222222222233|00000000001111111111222222222233|
- ;* |01234567890123456789012345678901|01234567890123456789012345678901|
- ;* |--------------------------------+--------------------------------|
- ;* 0: |* ** |* |
- ;* 1: | ** |* |
- ;* 2: | * |* |
- ;* 3: | * |* |
- ;* 4: | * |* |
- ;* 5: | * |* |
- ;* 6: | * |* |
- ;* +-----------------------------------------------------------------+
- ;*
- ;* Done
- ;*
- ;* Loop is interruptible
- ;* Collapsed epilog stages : 2
- ;* Prolog not removed
- ;* Collapsed prolog stages : 0
- ;*
- ;* Minimum required memory pad : 0 bytes
- ;*
- ;* Minimum safe trip count : 1
- ;*----------------------------------------------------------------------------*
- ;* SETUP CODE
- ;*
- ;* MVK 0x1,B0
- ;* ZERO A4
- ;*
- ;* SINGLE SCHEDULED ITERATION
- ;*
- ;* C38:
- ;* 0 MVKL .S1 0x1848200,A3 ; |351|
- ;* 1 MVKH .S1 0x1848200,A3 ; |351|
- ;* 2 [ B0] LDW .D1T1 *A3,A4 ; |351| ^
- ;* 3 NOP 4
- ;* 7 AND .D1 1,A4,A0 ; |351| ^
- ;* 8 [ A0] ZERO .D2 B0 ; ^
- ;* 9 [ B0] B .S2 C38 ; |351|
- ;* 10 NOP 5
- ;* ; BRANCH OCCURS ; |351|
- ;*----------------------------------------------------------------------------*
- L1: ; PIPED LOOP PROLOG
- ;** --------------------------------------------------------------------------*
- L2: ; PIPED LOOP KERNEL
- [ A0] ZERO .D2 B0 ; <0,8> ^
- || MVKH .S1 0x1848200,A3 ; |351| <1,1>
- [ B0] BNOP .S2 L2,4 ; |351| <0,9>
- || [ B0] LDW .D1T1 *A3,A4 ; |351| <1,2> ^
- AND .D1 1,A4,A0 ; |351| <1,7> ^
- || MVKL .S1 0x1848200,A3 ; |351| <2,0>
- ;** --------------------------------------------------------------------------*
- L3: ; PIPED LOOP EPILOG
- ;** --------------------------------------------------------------------------*
- MVKL .S1 0x1848204,A3 ; |350|
- MVKH .S1 0x1848204,A3 ; |350|
- LDW .D1T1 *A3,A3 ; |350|
- ;** --------------------------------------------------------------------------*
- L4:
- MVKL .S2 0x1848204,B5 ; |350|
- MVKL .S2 0x1848204,B4 ; |351|
- MVKH .S2 0x1848204,B5 ; |350|
- MVKH .S2 0x1848204,B4 ; |351|
- OR .D1 1,A3,A3 ; |350|
- STW .D2T1 A3,*B5 ; |350|
- LDW .D2T2 *B4,B4 ; |351|
- NOP 4
- AND .D2 1,B4,B0 ; |351|
- [ B0] B .S1 L8 ; |351|
- [!B0] MVKL .S1 0x1848204,A3 ; |351| (P) <0,0>
- [!B0] MVKH .S1 0x1848204,A3 ; |351| (P) <0,1>
- [ B0] MVKL .S1 _EVMDM642_init,A3 ; |44|
- || [!B0] LDW .D1T1 *A3,A4 ; |351| (P) <0,2> ^
- [ B0] MVKH .S1 _EVMDM642_init,A3 ; |44|
- NOP 1
- ; BRANCH OCCURS ; |351|
- ;** --------------------------------------------------------------------------*
- MVK .D2 0x1,B0
- MVKL .S1 0x1848204,A3 ; |351| (P) <1,0>
- AND .D1 1,A4,A0 ; |351| (P) <0,7> ^
- ;*----------------------------------------------------------------------------*
- ;* SOFTWARE PIPELINE INFORMATION
- ;*
- ;* Loop source line : 351
- ;* Loop closing brace source line : 351
- ;* Known Minimum Trip Count : 1
- ;* Known Max Trip Count Factor : 1
- ;* Loop Carried Dependency Bound(^) : 7
- ;* Unpartitioned Resource Bound : 2
- ;* Partitioned Resource Bound(*) : 2
- ;* Resource Partition:
- ;* A-side B-side
- ;* .L units 0 0
- ;* .S units 2* 1
- ;* .D units 1 0
- ;* .M units 0 0
- ;* .X cross paths 0 0
- ;* .T address paths 1 0
- ;* Long read paths 0 0
- ;* Long write paths 0 0
- ;* Logical ops (.LS) 0 0 (.L or .S unit)
- ;* Addition ops (.LSD) 1 1 (.L or .S or .D unit)
- ;* Bound(.L .S .LS) 1 1
- ;* Bound(.L .S .D .LS .LSD) 2* 1
- ;*
- ;* Searching for software pipeline schedule at ...
- ;* ii = 7 Schedule found with 3 iterations in parallel
- ;*
- ;* Register Usage Table:
- ;* +-----------------------------------------------------------------+
- ;* |AAAAAAAAAAAAAAAAAAAAAAAAAAAAAAAA|BBBBBBBBBBBBBBBBBBBBBBBBBBBBBBBB|
- ;* |00000000001111111111222222222233|00000000001111111111222222222233|
- ;* |01234567890123456789012345678901|01234567890123456789012345678901|
- ;* |--------------------------------+--------------------------------|
- ;* 0: |* ** |* |
- ;* 1: | ** |* |
- ;* 2: | * |* |
- ;* 3: | * |* |
- ;* 4: | * |* |
- ;* 5: | * |* |
- ;* 6: | * |* |
- ;* +-----------------------------------------------------------------+
- ;*
- ;* Done
- ;*
- ;* Loop is interruptible
- ;* Collapsed epilog stages : 2
- ;* Prolog not removed
- ;* Collapsed prolog stages : 0
- ;*
- ;* Minimum required memory pad : 0 bytes
- ;*
- ;* Minimum safe trip count : 1
- ;*----------------------------------------------------------------------------*
- ;* SETUP CODE
- ;*
- ;* MVK 0x1,B0
- ;* ZERO A4
- ;*
- ;* SINGLE SCHEDULED ITERATION
- ;*
- ;* C16:
- ;* 0 MVKL .S1 0x1848204,A3 ; |351|
- ;* 1 MVKH .S1 0x1848204,A3 ; |351|
- ;* 2 [ B0] LDW .D1T1 *A3,A4 ; |351| ^
- ;* 3 NOP 4
- ;* 7 AND .D1 1,A4,A0 ; |351| ^
- ;* 8 [ A0] ZERO .D2 B0 ; ^
- ;* 9 [ B0] B .S2 C16 ; |351|
- ;* 10 NOP 5
- ;* ; BRANCH OCCURS ; |351|
- ;*----------------------------------------------------------------------------*
- L5: ; PIPED LOOP PROLOG
- ;** --------------------------------------------------------------------------*
- L6: ; PIPED LOOP KERNEL
- [ A0] ZERO .D2 B0 ; <0,8> ^
- || MVKH .S1 0x1848204,A3 ; |351| <1,1>
- [ B0] BNOP .S2 L6,4 ; |351| <0,9>
- || [ B0] LDW .D1T1 *A3,A4 ; |351| <1,2> ^
- AND .D1 1,A4,A0 ; |351| <1,7> ^
- || MVKL .S1 0x1848204,A3 ; |351| <2,0>
- ;** --------------------------------------------------------------------------*
- L7: ; PIPED LOOP EPILOG
- ;** --------------------------------------------------------------------------*
- MVKL .S1 _EVMDM642_init,A3 ; |44|
- MVKH .S1 _EVMDM642_init,A3 ; |44|
- NOP 1
- ;** --------------------------------------------------------------------------*
- L8:
- CALL .S2X A3 ; |44|
- ADDKPC .S2 RL0,B3,4 ; |44|
- RL0: ; CALL OCCURS ; |44|
- MVKL .S1 _EVMDM642_LED_init,A3 ; |45|
- MVKH .S1 _EVMDM642_LED_init,A3 ; |45|
- NOP 1
- CALL .S2X A3 ; |45|
- ADDKPC .S2 RL1,B3,4 ; |45|
- RL1: ; CALL OCCURS ; |45|
- LDW .D2T2 *++SP(8),B3 ; |53|
- NOP 2
- MVKL .S1 0x141015a,A5 ; |49|
- MVKH .S1 0x141015a,A5 ; |49|
- RET .S2 B3 ; |53|
- MVKL .S2 0x1410444,B4 ; |49|
- MVKH .S2 0x1410444,B4 ; |49|
- MVKL .S2 _bMacAddr,B5 ; |49|
- MV .D1X B4,A4 ; |49|
- || MVKH .S2 _bMacAddr,B5 ; |49|
- STDW .D2T1 A5:A4,*B5 ; |49|
- ; BRANCH OCCURS ; |53|
- .sect ".text"
- .global _DM642EMAC_linkStatus
- ;******************************************************************************
- ;* FUNCTION NAME: _DM642EMAC_linkStatus *
- ;* *
- ;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,B0,B1,B2,B3,B4,B5, *
- ;* B6,B7,B8,B9,B13,SP,A16,A17,A18,A19,A20,A21,A22, *
- ;* A23,A24,A25,A26,A27,A28,A29,A30,A31,B16,B17,B18, *
- ;* B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30, *
- ;* B31 *
- ;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,B0,B1,B2,B3,B4,B5, *
- ;* B6,B7,B8,B9,B13,SP,A16,A17,A18,A19,A20,A21,A22, *
- ;* A23,A24,A25,A26,A27,A28,A29,A30,A31,B16,B17,B18, *
- ;* B19,B20,B21,B22,B23,B24,B25,B26,B27,B28,B29,B30, *
- ;* B31 *
- ;* Local Frame Size : 8 Args + 0 Auto + 8 Save = 16 byte *
- ;******************************************************************************
- _DM642EMAC_linkStatus:
- ;** --------------------------------------------------------------------------*
- MVKL .S2 _printf,B4 ; |82|
- || MVKL .S1 _LinkStr,A3 ; |82|
- || MV .D1X B4,A5 ; |81|
- MVKH .S2 _printf,B4 ; |82|
- || MVKH .S1 _LinkStr,A3 ; |82|
- CALL .S2 B4 ; |82|
- || LDW .D1T1 *+A3[A5],A3 ; |82|
- STW .D2T1 A10,*SP--(16) ; |81|
- MVKL .S2 SL6+0,B5 ; |82|
- STW .D2T2 B13,*+SP(12) ; |81|
- || MVKH .S2 SL6+0,B5 ; |82|
- STW .D2T2 B5,*+SP(4) ; |82|
- ADDKPC .S2 RL2,B3,0 ; |82|
- || STW .D2T1 A3,*+SP(8) ; |82|
- || MV .L2 B3,B13 ; |81|
- || MV .D1 A4,A10 ; |81|
- RL2: ; CALL OCCURS ; |82|
- MVKL .S2 _MDIO_phyRegWrite,B5 ; |86|
- MVKH .S2 _MDIO_phyRegWrite,B5 ; |86|
- CALL .S2 B5 ; |86|
- MVK .S2 0x14,B4 ; |86|
- MVKL .S1 0xd5d0,A6 ; |86|
- ADDKPC .S2 RL3,B3,0 ; |86|
- MV .D1 A10,A4 ; |86|
- MVKH .S1 0xd5d0,A6 ; |86|
- RL3: ; CALL OCCURS ; |86|
- MV .D2 B13,B3 ; |87|
- RET .S2 B3 ; |87|
- || LDW .D2T2 *+SP(12),B13 ; |87|
- LDW .D2T1 *++SP(16),A10 ; |87|
- NOP 4
- ; BRANCH OCCURS ; |87|
- .sect ".text"
- .global _DM642EMAC_getConfig
- ;******************************************************************************
- ;* FUNCTION NAME: _DM642EMAC_getConfig *
- ;* *
- ;* Regs Modified : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B2,B3,B4,*
- ;* B5,B6,B7,B8,B9,B10,B13,SP,A16,A17,A18,A19,A20, *
- ;* A21,A22,A23,A24,A25,A26,A27,A28,A29,A30,A31,B16, *
- ;* B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28, *
- ;* B29,B30,B31 *
- ;* Regs Used : A0,A1,A2,A3,A4,A5,A6,A7,A8,A9,A10,A11,B0,B1,B2,B3,B4,*
- ;* B5,B6,B7,B8,B9,B10,B13,SP,A16,A17,A18,A19,A20, *
- ;* A21,A22,A23,A24,A25,A26,A27,A28,A29,A30,A31,B16, *
- ;* B17,B18,B19,B20,B21,B22,B23,B24,B25,B26,B27,B28, *
- ;* B29,B30,B31 *
- ;* Local Frame Size : 32 Args + 0 Auto + 16 Save = 48 byte *
- ;******************************************************************************
- _DM642EMAC_getConfig:
- ;** --------------------------------------------------------------------------*
- STW .D2T2 B10,*SP--(48) ; |63|
- MVKL .S1 _bMacAddr,A10 ; |64|
- || STDW .D2T1 A11:A10,*+SP(40) ; |63|
- MVKH .S1 _bMacAddr,A10 ; |64|
- LDBU .D1T2 *A10,B5 ; |64|
- || MVKL .S1 SL7+0,A3 ; |64|
- MVKH .S1 SL7+0,A3 ; |64|
- STW .D2T1 A3,*+SP(4) ; |64|
- LDBU .D1T1 *+A10(1),A8 ; |64|
- LDBU .D1T1 *+A10(2),A5 ; |64|
- || STW .D2T2 B13,*+SP(36) ; |63|
- LDBU .D1T1 *+A10(3),A3 ; |64|
- || MVKL .S2 _printf,B5 ; |64|
- || STW .D2T2 B5,*+SP(8) ; |64|
- MVKH .S2 _printf,B5 ; |64|
- || LDBU .D1T1 *+A10(4),A6 ; |64|
- CALL .S2 B5 ; |64|
- || LDBU .D1T1 *+A10(5),A7 ; |64|
- STW .D2T1 A8,*+SP(12) ; |64|
- STW .D2T1 A5,*+SP(16) ; |64|
- STW .D2T1 A3,*+SP(20) ; |64|
- STW .D2T1 A6,*+SP(24) ; |64|
- || MV .S2 B4,B10 ; |63|
- ADDKPC .S2 RL4,B3,0 ; |64|
- || STW .D2T1 A7,*+SP(28) ; |64|
- || MV .L2 B3,B13 ; |63|
- || MV .D1 A4,A11 ; |63|
- RL4: ; CALL OCCURS ; |64|
- MVKL .S2 _mmCopy,B5 ; |69|
- MVKH .S2 _mmCopy,B5 ; |69|
- CALL .S2 B5 ; |69|
- ADDKPC .S2 RL5,B3,1 ; |69|
- MV .D1 A11,A4 ; |69|
- MV .D2X A10,B4 ; |69|
- MVK .S1 0x6,A6 ; |69|
- RL5: ; CALL OCCURS ; |69|
- LDW .D2T2 *+SP(36),B13 ; |71|
- || MV .S2 B13,B3 ; |71|
- MVK .S2 15,B4 ; |70|
- || LDDW .D2T1 *+SP(40),A11:A10 ; |71|
- RET .S2 B3 ; |71|
- || STW .D2T2 B4,*B10 ; |70|
- LDW .D2T2 *++SP(48),B10 ; |71|
- NOP 4
- ; BRANCH OCCURS ; |71|
- ;******************************************************************************
- ;* STRINGS *
- ;******************************************************************************
- .sect ".const"
- SL1: .string "No Link",0
- SL2: .string "10Mb/s Half Duplex",0
- SL3: .string "10Mb/s Full Duplex",0
- SL4: .string "100Mb/s Half Duplex",0
- SL5: .string "100Mb/s Full Duplex",0
- SL6: .string "Link Status: %s",10,0
- SL7: .string "Using MAC Address: %02x-%02x-%02x-%02x-%02x-%02x",10,0
- ;******************************************************************************
- ;* UNDEFINED EXTERNAL REFERENCES *
- ;******************************************************************************
- .global _printf
- .global _mmCopy
- .global _EVMDM642_init
- .global _EVMDM642_LED_init
- .global _MDIO_phyRegWrite
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