DSP编程

开发平台：

C/C++

fpga_loader.cdb：源码内容

prop Set :: (if ($1 < 1 || $1 > 3) {self.error(" Minimum: 1 ECLKOUT cycle - Maximum : 3 ECLKOUT cycles")} else {self.TA2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst MTYPE3_SETUP :: = (if (!CSL.CHIP_6712) {"32-bit async. interf."} else {" 8-bit async. interf."}) {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 8-bit async. interf.,16-bit async. interf.,32-bit async. interf., 8-bit SDRAM,16-bit SDRAM,32-bit SDRAM, 8-bit SBSRAM,16-bit SBSRAM,32-bit SBSRAM"
prop Label :: "Memory Type (MTYPE)"
prop JSName :: "emifCectl3Mtype"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 == " 8-bit async. interf." || $1 == "16-bit async. interf.") {self.error("Memory type available for 6211/671x only")} else {if ($1 == " 8-bit SDRAM" || $1 == "16-bit SDRAM") {self.error("Memory type available for 6211/671x only")} else {if ($1 == " 8-bit SBSRAM" || $1 == "16-bit SBSRAM") {self.error("Memory type available for 6211/671x only")} else {self.MTYPE3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"}}}} else {if (CSL.CHIP_6712 && ($1 == "32-bit SBSRAM" || $1 == "32-bit SDRAM" || $1 == "32-bit async. interf.")) {self.error(" 6712 supports 16-bit EMIF only")} else {self.MTYPE3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"}})
}
inst RDSTRB3_SETUP :: 63 {
prop Label :: "Read Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifCectl3ReadStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycles")} else {self.RDSTRB3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst RDSETUP3_SETUP :: 15 {
prop Label :: "Read Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifCectl3ReadSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.RDSETUP3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst RDHLD3_SETUP :: 3 {
prop Label :: "Read Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifCectl3ReadHold"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycles")} else {self.RDHLD3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"}} else {if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.RDHLD3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"}})
}
inst WRSTRB3_SETUP :: 63 {
prop Label :: "Write Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifCectl3WriteStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycles")} else {self.WRSTRB3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst WRSETUP3_SETUP :: 15 {
prop Label :: "Write Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifCectl3WriteSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.WRSETUP3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst WRHLD3_SETUP :: 3 {
prop Label :: "Write Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifCectl3WriteHold"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycles")} else {self.WRHLD3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"}} else {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycles")} else {self.WRHLD3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"}})
}
inst TA3_SETUP :: 3 {
prop Label :: "Turn around time (TA) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifCectl3Ta"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && (if (CSL.C11_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 1 || $1 > 3) {self.error(" Minimum: 1 ECLKOUT cycle - Maximum : 3 ECLKOUT cycles")} else {self.TA3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst TRC_SETUP :: 15 {
prop Label :: "TRC = trc/(clk period-1) (TRC) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdctlTrc"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error("Minimum TRC = 0 - Maximum TRC = 15 ")} else {self.TRC_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok"})
}
inst TRP_SETUP :: 8 {
prop Label :: "TRP = trp/(clk period-1) (TRP) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdctlTrp"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error("Minimum TRP = 0 - Maximum TRP= 15 ")} else {self.TRP_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok"})
}
inst TRCD_SETUP :: self.TRCD_Init {
prop Label :: "TRCD = trcd/(clk period-1) (TRCD) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdctlTrcd"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error("Minimum TRCD = 0 - Maximum TRCD= 15 ")} else {self.TRCD_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok"})
}
inst INIT_SETUP :: "Initialize" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Initialize,No effect"
prop Label :: "Initialization of all SDRAMs (INIT)"
prop JSName :: "emifSdctlInit"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.INIT_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst RFEN_SETUP :: "Enable" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Enable,Disable"
prop Label :: "SDRAM Refresh Enable (RFEN)"
prop JSName :: "emifSdctlRfen"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.RFEN_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst SDWID_SETUP :: "Four 8-bit SDRAMs" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Four 8-bit SDRAMs,Two 16-bit SDRAMs"
prop Label :: "Width Select (SDWID)"
prop JSName :: "emifSdctlSdwid"
prop Visible :: if ((!CSL.C11_SUPPORT)) {1} else {0}
prop Writable :: if (CSL.EMIF_SUPPORT) && ((!CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.SDWID_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst PERIOD_SETUP1 :: 64 {
prop Label :: "Refresh Period (CLKOUT2 cycles)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdtimClk2Period"
prop Visible :: if ((!CSL.C11_SUPPORT)) {1} else {0}
prop Writable :: if (CSL.EMIF_SUPPORT) && ((!CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 1 || $1 > 4095) {self.error("Refresh Period range [1..4095] clk. cycl.")} else {self.PERIOD_SETUP1 = $1, self.SDTIM_VALUE = self.SDTIM_VALUE_update(), "ok"})
}
inst SDCSZ_SETUP :: " 9 addresses" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 9 addresses, 8 addresses,10 addresses"
prop Label :: "Column Size (SDCSZ)"
prop JSName :: "emifSdctlSdcsz"
prop Visible :: if ((CSL.C11_SUPPORT)) {1} else {0}
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.SDCSZ_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst SDRSZ_SETUP :: "11 addresses" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "11 addresses,12 addresses,13 addresses"
prop Label :: "Row Size (SDRSZ)"
prop JSName :: "emifSdctlSdrsz"
prop Visible :: if ((CSL.C11_SUPPORT)) {1} else {0}
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.SDRSZ_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst SDBSZ_SETUP :: "Two banks" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Two banks,Four banks"
prop Label :: "Bank Size (SDBSZ)"
prop JSName :: "emifSdctlSdbsz"
prop Visible :: if ((CSL.C11_SUPPORT)) {1} else {0}
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.SDBSZ_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst PERIOD_SETUP2 :: 1500 {
prop Label :: "Refresh Period (ECLKOUT cycles)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdtimEclkPeriod"
prop Visible :: if ((CSL.C11_SUPPORT)) {1} else {0}
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 1 || $1 > 4096) {self.error("1 cyc. < PERIOD < 4096 cyc. ")} else {self.PERIOD_SETUP2 = $1, self.SDTIM_VALUE = self.SDTIM_VALUE_update(), "ok"})
}
inst XRFR_SETUP :: 1 {
prop Label :: "Extra Refreshes Ctrl. (XRFR)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdctlXrfr"
prop Visible :: if ((CSL.C11_SUPPORT)) {1} else {0}
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 < Extra refreshes < 4 ")} else {self.XRFR_SETUP = $1, self.SDTIM_VALUE = self.SDTIM_VALUE_update(), "ok"})
}
inst TCL_SETUP :: 3 {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "CAS Latency (TCL)"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextTcl"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 2 || $1 > 3) {self.error("TCL : 2 or 3 ECLKOUT cycles ")} else {self.TCL_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst TRAS_SETUP :: 8 {
prop Label :: "tras = TRAS + 1 (ECLKOUT cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextTras"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 8) {self.error("1 ECLKOUT cycle < tras < 8 ECLKOUT cycles ")} else {self.TRAS_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst TRRD_SETUP :: 3 {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop Label :: "trrd = TRRD (2 or 3 ECLKOUT cyc.)"
prop JSName :: "emifSdextTrrd"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 2 || $1 > 3) {self.error("TRRD : 2 or 3 ECLKOUT cycles ")} else {self.TRRD_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst TWR_SETUP :: 2 {
prop Label :: "twr = TWR + 1 (ECLKOUT cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextTwr"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 ECLKOUT cycle < twr < 4 ECLKOUT cycles ")} else {self.TWR_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst THZP_SETUP :: 3 {
prop Label :: "thzp = THZP + 1 (ECLKOUT cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextThzp"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 ECLKOUT cycle < thzp < 4 ECLKOUT cycles ")} else {self.THZP_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst RD2RD_SETUP :: 2 {
prop Label :: "READ-To-READ (ECLKOUT cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextRd2rd"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 2) {self.error("1 < # of ECLKOUT cycles < 2 ")} else {self.RD2RD_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst RD2DEAC_SETUP :: 4 {
prop Label :: "READ-To-DEAC/DEAB (ECLKOUT cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextRd2deac"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 < # of ECLKOUT cycles < 4 ")} else {self.RD2DEAC_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst RD2WR_SETUP :: 6 {
prop Label :: "READ-To-WRITE (ECLKOUT cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextRd2wr"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 8) {self.error("1 < # of ECLKOUT cycles < 8 ")} else {self.RD2WR_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst R2WDQM_SETUP :: 4 {
prop Label :: "READ-To-WRITE with Interrupt (BEx cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextR2wdqm"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 < # of Bex cycles < 4 ")} else {self.R2WDQM_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst WR2WR_SETUP :: 2 {
prop Label :: "WRITE-To-WRITE (ECLKOUT cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextWr2wr"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 2) {self.error("1 < # of ECLKOUT cycles < 2 ")} else {self.WR2WR_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst WR2DEAC_SETUP :: 2 {
prop Label :: "WRITE-To-DEAC/DEAB (ECLKOUT cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextWr2deac"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 < # of ECLKOUT cycles < 4 ")} else {self.WR2DEAC_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst WR2RD_SETUP :: 2 {
prop Label :: "WRITE-To-READ (# of ECLKOUT cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifSdextWr2rd"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && ((CSL.C11_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 2) {self.error("1 < # of ECLKOUT cycles < 2 ")} else {self.WR2RD_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst GBLCTL_VALUE :: self.GBLCTL_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "Global Control Reg. (GBLCTL) "
prop Format :: "0x%08X"
prop JSName :: "emifGblctl"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: (if (CSL.C11_SUPPORT) {$a = $1 & 0xFFFFC000, if ($a != 0) {self.error("Bit field(bit[14..31]) is reserved")} else {$b = $1 & 0x00000007, if ($b != 0) {self.error("Bit field(bit[0..2]) is reserved")} else {self.GBLCTL_VALUE = $1 | 0x0003000 | 0x00000060, self.GBLCTL_SETUP_update($1 | 0x0003000 | 0x00000060), "ok"}}} else {if (CSL.CHIP_6202 || CSL.CHIP_6203 || CSL.CHIP_6204 || CSL.CHIP_6205) {$c = $1 & 0xFFFFC000, if ($c != 0) {self.error("Bit field(bit[14..31]) is reserved")} else {$d = $1 & 0x00000800, if ($d != 0) {self.error("Bit field 11 is reserved")} else {$e = $1 & 0x00000004, if ($e != 0) {self.error("Bit field 2 is reserved")} else {self.GBLCTL_VALUE = $1 | 0x0003000, self.GBLCTL_SETUP_update($1 | 0x0003000), "ok"}}}} else {if (CSL.CHIP_6201 || CSL.CHIP_6701) {$f = $1 & 0xFFFFC000, if ($f != 0) {self.error("Bit field(bit[14..31]) is reserved")} else {$g = $1 & 0x00000800, if ($g != 0) {self.error("Bit field 11 is reserved")} else {self.GBLCTL_VALUE = $1 | 0x0003000, self.GBLCTL_SETUP_update($1 | 0x0003000), "ok"}}} }})
}
inst CECTL0_VALUE :: self.CECTL0_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE0 Space Control Reg. (CECTL0) "
prop Format :: "0x%08X"
prop JSName :: "emifCectl0"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x00000070, if ($a == 0x00000070 || $a == 0x00000050 || $a == 0x00000060) {self.error("Undefined Memory type for CE Spaces - See CEx Space Pages")} else {if (CSL.C11_SUPPORT) {$b = $1 & 0x000000F0, if ($b == 0x000000C0 || $b == 0x000000D0 || $b == 0x000000E0 || $b == 0x000000F0) {self.error("Undefined Memory type for CEx Spaces - See CEx Space Pages")} else {$g = $1 & 0x00000008, if ($g != 0) {self.error("Bit field 3 is reserved")} else {self.CECTL0_VALUE = $1, self.CECTL0_SETUP_update($1), "ok"}}} else {$c = $1 & 0x00000070, if ($c == 0x00000000 || $c == 0x00000010) {self.error("Undefined Memory type for CE0 Space - See CE0 Space Page")} else {$d = $1 & 0x0000C000, if ($d != 0) {self.error("Bit field(bit[14..15]) is reserved")} else {$e = $1 & 0x00000080, if ($e != 0) {self.error("Bit field 7 is reserved")} else {$f = $1 & 0x0000000C, if ($f != 0) {self.error("Bit field(bit[2..3]) is reserved")} else {self.CECTL0_VALUE = $1, self.CECTL0_SETUP_update($1), "ok"}}}}}})
}
inst CECTL1_VALUE :: self.CECTL1_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE1 Space Control Reg. (CECTL1) "
prop Format :: "0x%08X"
prop JSName :: "emifCectl1"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x00000070, if ($a == 0x00000070 || $a == 0x00000050 || $a == 0x00000060) {self.error("Undefined Memory type for CE Spaces - See CEx Space Pages")} else {if (CSL.C11_SUPPORT) {$b = $1 & 0x000000F0, if ($b == 0x000000C0 || $b == 0x000000D0 || $b == 0x000000E0 || $b == 0x000000F0) {self.error("Undefined Memory type for CEx Spaces - See CEx Space Pages")} else {$g = $1 & 0x00000008, if ($g != 0) {self.error("Bit field 3 is reserved")} else {self.CECTL1_VALUE = $1, self.CECTL1_SETUP_update($1), "ok"}}} else {$c = $1 & 0x00000070, if ($c == 0x00000030) {self.error("Undefined Memory type for CE1 Space - See CE1 Space Page")} else {$d = $1 & 0x0000C000, if ($d != 0) {self.error("Bit field(bit[14..15]) is reserved")} else {$e = $1 & 0x00000080, if ($e != 0) {self.error("Bit field 7 is reserved")} else {$f = $1 & 0x0000000C, if ($f != 0) {self.error("Bit field(bit[2..3]) is reserved")} else {self.CECTL1_VALUE = $1, self.CECTL1_SETUP_update($1), "ok"}}}}}})
}
inst CECTL2_VALUE :: self.CECTL2_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE2 Space Control Reg. (CECTL2) "
prop Format :: "0x%08X"
prop JSName :: "emifCectl2"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x00000070, if ($a == 0x00000070 || $a == 0x00000050 || $a == 0x00000060) {self.error("Undefined Memory type for CE Spaces - See CEx Space Pages")} else {if (CSL.C11_SUPPORT) {$b = $1 & 0x000000F0, if ($b == 0x000000C0 || $b == 0x000000D0 || $b == 0x000000E0 || $b == 0x000000F0) {self.error("Undefined Memory type for CEx Spaces - See CEx Space Pages")} else {$g = $1 & 0x00000008, if ($g != 0) {self.error("Bit field 3 is reserved")} else {self.CECTL2_VALUE = $1, self.CECTL2_SETUP_update($1), "ok"}}} else {$c = $1 & 0x00000070, if ($c == 0x00000000 || $c == 0x00000010) {self.error("Undefined Memory type for CE2 Space - See CE2 Space Page")} else {$d = $1 & 0x0000C000, if ($d != 0) {self.error("Bit field(bit[14..15]) is reserved")} else {$e = $1 & 0x00000080, if ($e != 0) {self.error("Bit field 7 is reserved")} else {$f = $1 & 0x0000000C, if ($f != 0) {self.error("Bit field(bit[2..3]) is reserved")} else {self.CECTL2_VALUE = $1, self.CECTL2_SETUP_update($1), "ok"}}}}}})
}
inst CECTL3_VALUE :: self.CECTL3_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE3 Space Control Reg. (CECTL3) "
prop Format :: "0x%08X"
prop JSName :: "emifCectl3"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x00000070, if ($a == 0x00000070 || $a == 0x00000050 || $a == 0x00000060) {self.error("Undefined Memory type for CE Spaces - See CEx Space Pages")} else {if (CSL.C11_SUPPORT) {$b = $1 & 0x000000F0, if ($b == 0x000000C0 || $b == 0x000000D0 || $b == 0x000000E0 || $b == 0x000000F0) {self.error("Undefined Memory type for CEx Spaces - See CEx Space Pages")} else {$g = $1 & 0x00000008, if ($g != 0) {self.error("Bit field 3 is reserved")} else {self.CECTL3_VALUE = $1, self.CECTL3_SETUP_update($1), "ok"}}} else {$c = $1 & 0x00000070, if ($c == 0x00000000 || $c == 0x00000010) {self.error("Undefined Memory type for CE3 Space - See CE3 Space Page")} else {$d = $1 & 0x0000C000, if ($d != 0) {self.error("Bit field(bit[14..15]) is reserved")} else {$e = $1 & 0x00000080, if ($e != 0) {self.error("Bit field 7 is reserved")} else {$f = $1 & 0x0000000C, if ($f != 0) {self.error("Bit field(bit[2..3]) is reserved")} else {self.CECTL3_VALUE = $1, self.CECTL3_SETUP_update($1), "ok"}}}}}})
}
inst SDCTL_VALUE :: self.SDCTL_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "SDRAM Control Reg.(SDCTL) "
prop Format :: "0x%08X"
prop JSName :: "emifSdctl"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x0c000000, if ($a == 0x0c000000) {self.error("Undefined Value for Colum Size field SDCSZ")} else {$b = $1 & 0x30000000, if ($b == 0x30000000) {self.error("Undefined Value for Row Size field SDRSZ")} else {self.SDCTL_VALUE = $1, self.SDCTL_SETUP_update($1), "ok"}})
}
inst SDTIM_VALUE :: self.SDTIM_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "SDRAM Timing Reg.(SDTIM) "
prop Format :: "0x%08X"
prop JSName :: "emifSdtim"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: (self.SDTIM_VALUE = $1, self.SDTIM_SETUP_update($1), "ok")
}
inst SDEXT_VALUE :: self.SDEXT_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "SDRAM Extended Reg.(SDEXT) "
prop Format :: "0x%08X"
prop JSName :: "emifSdext"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && (CSL.C11_SUPPORT) {1} else {0}
prop NoGen :: 0
prop cGen :: if (CSL.C11_SUPPORT) {1} else {0}
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: (self.SDEXT_VALUE = $1, self.SDEXT_SETUP_update($1), "ok")
}
}
type hEmif {
prop IsContainedIn :: EMIFFOLDER
prop name :: "hEmif"
prop Label :: "EMIF Resource Manager"
prop JSName :: "HEMIF"
prop NoGen :: 1
prop GlobalPropertyPage :: "{980E6520-6246-11d4-B5CC-0050DA2E2CC0}"
prop InstancePropertyPage :: "{980E6521-6246-11d4-B5CC-0050DA2E2CC0}"
prop GlobalIcon :: 163
prop InstanceIcon :: 164
prop GlobalHelpTopic :: (1042)
prop cGen :: 1
global EMIF_INIT_ENABLE :: 0 {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "Enable Pre-Initialization"
prop JSName :: "emifEnablePreInit"
prop Visible :: 1
prop Writable :: (CSL.EMIF_SUPPORT) && 1
prop NoGen :: 0
prop Set :: ($a = 0, scan ($b; emifCfg) {$a = $a + 1}, if ($1 == 1 && $a == 1 && self.EMIF_INIT == EMIF_NOTHING) {" You must create a new configuration object"} else {self.EMIF_INIT_ENABLE = $1, if ($1 == 0) {self.EMIF_INIT = EMIF_NOTHING} , "ok"})
}
global EMIF_INIT :: EMIF_NOTHING {
prop Type :: "{7BA2DA00-5A53-11d0-9BFE-0000C0AC14C7}"
prop MemberType :: emifCfg
prop Label :: " Pre-Initialize with"
prop JSName :: "emifPreInit"
prop Visible :: 1
prop Writable :: if (CSL.EMIF_SUPPORT) && (self.EMIF_INIT_ENABLE == 1) {1} else {0}
}
}
object EMIF_NOTHING :: emifCfg {
param iComment :: "<add comments here>"
param iIsUsed :: 0
param iId :: 0
param iDelUser :: "USER"
param iDelMsg :: "ok"
param NOHOLD_SETUP :: "Enable Hold"
param RBTR8_SETUP :: "until High-Priority"
param SSCRT_SETUP :: "1/2 CPU clock"
param CLK2EN_SETUP :: "Enabled to clock"
param CLK1EN_SETUP :: "Enabled to clock"
param SSCEN_SETUP :: "Enabled to clock"
param SDCEN_SETUP :: "Enabled to clock"
param RDSTRB0_SETUP :: 63
param RDSETUP0_SETUP :: 15
param RDHLD0_SETUP :: 3
param WRSTRB0_SETUP :: 63
param WRSETUP0_SETUP :: 15
param WRHLD0_SETUP :: 3
param TA0_SETUP :: 3
param RDSTRB1_SETUP :: 63
param RDSETUP1_SETUP :: 15
param RDHLD1_SETUP :: 3
param WRSTRB1_SETUP :: 63
param WRSETUP1_SETUP :: 15
param WRHLD1_SETUP :: 3
param TA1_SETUP :: 3
param RDSTRB2_SETUP :: 63
param RDSETUP2_SETUP :: 15
param RDHLD2_SETUP :: 3
param WRSTRB2_SETUP :: 63
param WRSETUP2_SETUP :: 15
param WRHLD2_SETUP :: 3
param TA2_SETUP :: 3
param RDSTRB3_SETUP :: 63
param RDSETUP3_SETUP :: 15
param RDHLD3_SETUP :: 3
param WRSTRB3_SETUP :: 63
param WRSETUP3_SETUP :: 15
param WRHLD3_SETUP :: 3
param TA3_SETUP :: 3
param TRC_SETUP :: 15
param TRP_SETUP :: 8
param TRCD_SETUP :: 8
param INIT_SETUP :: "Initialize"
param RFEN_SETUP :: "Enable"
param SDWID_SETUP :: "Four 8-bit SDRAMs"
param PERIOD_SETUP1 :: 64
param SDCSZ_SETUP :: " 9 addresses"
param SDRSZ_SETUP :: "11 addresses"
param SDBSZ_SETUP :: "Two banks"
param PERIOD_SETUP2 :: 1500
param XRFR_SETUP :: 1
param TCL_SETUP :: 3
param TRAS_SETUP :: 8
param TRRD_SETUP :: 3
param TWR_SETUP :: 2
param THZP_SETUP :: 3
param RD2RD_SETUP :: 2
param RD2DEAC_SETUP :: 4
param RD2WR_SETUP :: 6
param R2WDQM_SETUP :: 4
param WR2WR_SETUP :: 2
param WR2DEAC_SETUP :: 2
param WR2RD_SETUP :: 2
param GBLCTL_VALUE :: 12408
param CECTL0_VALUE :: -49373
param CECTL1_VALUE :: -49373
param CECTL2_VALUE :: -49373
param CECTL3_VALUE :: -49373
param SDCTL_VALUE :: 59305984
param SDTIM_VALUE :: 64
param SDEXT_VALUE :: 1564479
}
type EMIFAFOLDER {
isa ModuleFolder
prop IsContainedIn :: CSL
prop name :: "EMIFA"
prop Label :: "EMIFA - External Memory Interface A (64x devices only)"
prop NoGen :: 1
prop GlobalPropertyPage :: "{980E6530-6246-11d4-B5CC-0050DA2E2CC0}"
prop InstancePropertyPage :: "{980E6531-6246-11d4-B5CC-0050DA2E2CC0}"
prop GlobalIcon :: 163
prop InstanceIcon :: 164
prop GlobalHelpTopic :: (1043)
global gUser :: "USER" {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gSetOf :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gNumOf :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gDirty :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gInitFlag :: 1 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gInit :: = ($a = 0, $b = 0, scan ($i; self) {if ($i.IsConfObj()) {$a += 1, if (self.isFinite) {$b |= 1 << $i.iId} } }, self.gNumOf = $a, self.gSetOf = $b, if (self.gInitFlag == 0) {self.localInit()} , self.gInitFlag = 1) {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
}
type emifaCfg {
isa ObjectMgr
prop Name :: "emifaCfg"
prop Label :: "EMIFA Configuration Manager"
prop JSName :: "EMIFA"
prop IsContainedIn :: EMIFAFOLDER
prop NoGen :: 1
prop maxObjs :: (32767)
prop GlobalPropertyPage :: "{980E6532-6246-11d4-B5CC-0050DA2E2CC0}"
prop InstancePropertyPage :: "{980E6533-6246-11d4-B5CC-0050DA2E2CC0}"
prop GlobalIcon :: 163
prop InstanceIcon :: 164
prop GlobalHelpTopic :: (1044)
prop InstanceHelpTopic :: (1044)
prop cGen :: CSL.EMIFA_SUPPORT
prop cStruct :: 1
prop cStructType :: "EMIFA_Config"
prop cHeaderName :: if self.gNumOf > 0 {"csl_emifa.h"} else {""}
prop cStructQual :: "far"
prop cStructName :: self
prop cConfigName :: "EMIFA_config"
prop localDelete :: (self.myDelete)
prop myDelete :: ($a = 0, scan ($b; emifaCfg) {$a = $a + 1}, if ($a == 2) {hEmifa.EMIFA_INIT_ENABLE = 0} , "ok")
prop NOHOLD_GBLCTL :: (if (self.NOHOLD_SETUP == "Disable Hold") {0x00000080} else {0x00000000})
prop CLK4EN_GBLCTL :: (if (self.CLK4EN_SETUP == "Held high") {0x00000000} else {0x00000010})
prop CLK6EN_GBLCTL :: (if (self.CLK6EN_SETUP == "Held high") {0x00000000} else {0x00000008})
prop EK1EN_GBLCTL :: (if (self.EK1EN_SETUP == "Held low") {0x00000000} else {0x00000020})
prop EK2EN_GBLCTL :: (if (self.EK2EN_SETUP == "Held low") {0x00000000} else {0x00010000})
prop EK1HZ_GBLCTL :: (if (self.EK1HZ_SETUP == "Clock during hold") {0x00000000} else {0x00000040})
prop EK2HZ_GBLCTL :: (if (self.EK2HZ_SETUP == "Clock during hold") {0x00000000} else {0x00020000})
prop EK2RATE_GBLCTL :: (if (self.EK2RATE_SETUP == "1x EMIF input clock") {0x00000000} else {if (self.EK2RATE_SETUP == "1/2x EMIF input clock") {0x00040000} else {if (self.EK2RATE_SETUP == "1/4x EMIF input clock") {0x00080000} }})
prop BRMODE_GBLCTL :: (if (self.BRMODE_SETUP == "access pending or in progress") {0x00000000} else {if (self.BRMODE_SETUP == "access/refresh pending or in progress") {0x00002000} })
prop MTYPE0_CECTL0 :: (if (self.MTYPE0_SETUP == "32-bit async. interf.") {0x00000020} else {if (self.MTYPE0_SETUP == "32-bit SDRAM") {0x00000030} else {if (self.MTYPE0_SETUP == "32-bit prog. sync. mem") {0x00000040} else {if (self.MTYPE0_SETUP == " 8-bit async. interf.") {0x00000000} else {if (self.MTYPE0_SETUP == " 8-bit SDRAM") {0x00000080} else {if (self.MTYPE0_SETUP == " 8-bit prog. sync. mem") {0x000000a0} else {if (self.MTYPE0_SETUP == "16-bit async. interf.") {0x00000010} else {if (self.MTYPE0_SETUP == "16-bit SDRAM") {0x00000090} else {if (self.MTYPE0_SETUP == "16-bit prog. sync. mem") {0x000000b0} else {if (self.MTYPE0_SETUP == "64-bit async. interf.") {0x000000c0} else {if (self.MTYPE0_SETUP == "64-bit SDRAM") {0x000000d0} else {if (self.MTYPE0_SETUP == "64-bit prog. sync. mem") {0x000000e0} }}}}}}}}}}})
prop RDSTRB0_CECTL0 :: (((self.RDSTRB0_SETUP) << 8))
prop RDSETUP0_CECTL0 :: (((self.RDSETUP0_SETUP) << 16))
prop RDHLD0_CECTL0 :: ((self.RDHLD0_SETUP))
prop WRSTRB0_CECTL0 :: (((self.WRSTRB0_SETUP) << 22))
prop WRSETUP0_CECTL0 :: (((self.WRSETUP0_SETUP) << 28))
prop WRHLD0_CECTL0 :: (if (self.WRHLD0_SETUP > 3) {((self.WRHLD0_SETUP - 4) << 20)} else {((self.WRHLD0_SETUP << 20))})
prop WRHLDMSB0_CECTL0 :: (if (self.WRHLD0_SETUP > 3) {0x00000008} else {0x00000000})
prop TA0_CECTL0 :: ((self.TA0_SETUP << 14))
prop MTYPE1_CECTL1 :: (if (self.MTYPE1_SETUP == "32-bit async. interf.") {0x00000020} else {if (self.MTYPE1_SETUP == "32-bit SDRAM") {0x00000030} else {if (self.MTYPE1_SETUP == "32-bit prog. sync. mem") {0x00000040} else {if (self.MTYPE1_SETUP == " 8-bit async. interf.") {0x00000000} else {if (self.MTYPE1_SETUP == " 8-bit SDRAM") {0x00000080} else {if (self.MTYPE1_SETUP == " 8-bit prog. sync. mem") {0x000000a0} else {if (self.MTYPE1_SETUP == "16-bit async. interf.") {0x00000010} else {if (self.MTYPE1_SETUP == "16-bit SDRAM") {0x00000090} else {if (self.MTYPE1_SETUP == "16-bit prog. sync. mem") {0x000000b0} else {if (self.MTYPE1_SETUP == "64-bit async. interf.") {0x000000c0} else {if (self.MTYPE1_SETUP == "64-bit SDRAM") {0x000000d0} else {if (self.MTYPE1_SETUP == "64-bit prog. sync. mem") {0x000000e0} }}}}}}}}}}})
prop RDSTRB1_CECTL1 :: (((self.RDSTRB1_SETUP) << 8))
prop RDSETUP1_CECTL1 :: (((self.RDSETUP1_SETUP) << 16))
prop RDHLD1_CECTL1 :: ((self.RDHLD1_SETUP))
prop WRSTRB1_CECTL1 :: (((self.WRSTRB1_SETUP) << 22))
prop WRSETUP1_CECTL1 :: (((self.WRSETUP1_SETUP) << 28))
prop WRHLD1_CECTL1 :: (if (self.WRHLD1_SETUP > 3) {((self.WRHLD1_SETUP - 4) << 20)} else {((self.WRHLD1_SETUP << 20))})
prop WRHLDMSB1_CECTL1 :: (if (self.WRHLD1_SETUP > 3) {0x00000008} else {0x00000000})
prop TA1_CECTL1 :: ((self.TA1_SETUP << 14))
prop MTYPE2_CECTL2 :: (if (self.MTYPE2_SETUP == "32-bit async. interf.") {0x00000020} else {if (self.MTYPE2_SETUP == "32-bit SDRAM") {0x00000030} else {if (self.MTYPE2_SETUP == "32-bit prog. sync. mem") {0x00000040} else {if (self.MTYPE2_SETUP == " 8-bit async. interf.") {0x00000000} else {if (self.MTYPE2_SETUP == " 8-bit SDRAM") {0x00000080} else {if (self.MTYPE2_SETUP == " 8-bit prog. sync. mem") {0x000000a0} else {if (self.MTYPE2_SETUP == "16-bit async. interf.") {0x00000010} else {if (self.MTYPE2_SETUP == "16-bit SDRAM") {0x00000090} else {if (self.MTYPE2_SETUP == "16-bit prog. sync. mem") {0x000000b0} else {if (self.MTYPE2_SETUP == "64-bit async. interf.") {0x000000c0} else {if (self.MTYPE2_SETUP == "64-bit SDRAM") {0x000000d0} else {if (self.MTYPE2_SETUP == "64-bit prog. sync. mem") {0x000000e0} }}}}}}}}}}})
prop RDSTRB2_CECTL2 :: (((self.RDSTRB2_SETUP) << 8))
prop RDSETUP2_CECTL2 :: (((self.RDSETUP2_SETUP) << 16))
prop RDHLD2_CECTL2 :: ((self.RDHLD2_SETUP))
prop WRSTRB2_CECTL2 :: (((self.WRSTRB2_SETUP) << 22))
prop WRSETUP2_CECTL2 :: (((self.WRSETUP2_SETUP) << 28))
prop WRHLD2_CECTL2 :: (if (self.WRHLD2_SETUP > 3) {((self.WRHLD2_SETUP - 4) << 20)} else {((self.WRHLD2_SETUP << 20))})
prop WRHLDMSB2_CECTL2 :: (if (self.WRHLD2_SETUP > 3) {0x00000008} else {0x00000000})
prop TA2_CECTL2 :: ((self.TA2_SETUP << 14))
prop MTYPE3_CECTL3 :: (if (self.MTYPE3_SETUP == "32-bit async. interf.") {0x00000020} else {if (self.MTYPE3_SETUP == "32-bit SDRAM") {0x00000030} else {if (self.MTYPE3_SETUP == "32-bit prog. sync. mem") {0x00000040} else {if (self.MTYPE3_SETUP == " 8-bit async. interf.") {0x00000000} else {if (self.MTYPE3_SETUP == " 8-bit SDRAM") {0x00000080} else {if (self.MTYPE3_SETUP == " 8-bit prog. sync. mem") {0x000000a0} else {if (self.MTYPE3_SETUP == "16-bit async. interf.") {0x00000010} else {if (self.MTYPE3_SETUP == "16-bit SDRAM") {0x00000090} else {if (self.MTYPE3_SETUP == "16-bit prog. sync. mem") {0x000000b0} else {if (self.MTYPE3_SETUP == "64-bit async. interf.") {0x000000c0} else {if (self.MTYPE3_SETUP == "64-bit SDRAM") {0x000000d0} else {if (self.MTYPE3_SETUP == "64-bit prog. sync. mem") {0x000000e0} }}}}}}}}}}})
prop RDSTRB3_CECTL3 :: (((self.RDSTRB3_SETUP) << 8))
prop RDSETUP3_CECTL3 :: (((self.RDSETUP3_SETUP) << 16))
prop RDHLD3_CECTL3 :: ((self.RDHLD3_SETUP))
prop WRSTRB3_CECTL3 :: (((self.WRSTRB3_SETUP) << 22))
prop WRSETUP3_CECTL3 :: (((self.WRSETUP3_SETUP) << 28))
prop WRHLD3_CECTL3 :: (if (self.WRHLD3_SETUP > 3) {((self.WRHLD3_SETUP - 4) << 20)} else {((self.WRHLD3_SETUP << 20))})
prop WRHLDMSB3_CECTL3 :: (if (self.WRHLD3_SETUP > 3) {0x00000008} else {0x00000000})
prop TA3_CECTL3 :: ((self.TA3_SETUP << 14))
prop SYNCRL0_CESEC0 :: (if (self.SYNCRL0_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCRL0_SETUP == "1 cycle") {0x00000001} else {if (self.SYNCRL0_SETUP == "2 cycles") {0x00000002} else {0x00000003}}})
prop SYNCWL0_CESEC0 :: (if (self.SYNCWL0_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCWL0_SETUP == "1 cycle") {0x00000004} else {if (self.SYNCWL0_SETUP == "2 cycles") {0x00000008} else {0x0000000c}}})
prop CEEXT0_CESEC0 :: (if (self.CEEXT0_SETUP == "Inactive") {0x00000000} else {0x0000010})
prop RENEN0_CESEC0 :: (if (self.RENEN0_SETUP == "ADS Mode") {0x00000000} else {0x0000020})
prop SNCCLK0_CESEC0 :: (if (self.SNCCLK0_SETUP == "Sync. to ECLKOUT1") {0x00000000} else {0x0000040})
prop SYNCRL1_CESEC1 :: (if (self.SYNCRL1_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCRL1_SETUP == "1 cycle") {0x00000001} else {if (self.SYNCRL1_SETUP == "2 cycles") {0x00000002} else {0x00000003}}})
prop SYNCWL1_CESEC1 :: (if (self.SYNCWL1_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCWL1_SETUP == "1 cycle") {0x00000004} else {if (self.SYNCWL1_SETUP == "2 cycles") {0x00000008} else {0x0000000c}}})
prop CEEXT1_CESEC1 :: (if (self.CEEXT1_SETUP == "Inactive") {0x00000000} else {0x0000010})
prop RENEN1_CESEC1 :: (if (self.RENEN1_SETUP == "ADS Mode") {0x00000000} else {0x0000020})
prop SNCCLK1_CESEC1 :: (if (self.SNCCLK1_SETUP == "Sync. to ECLKOUT1") {0x00000000} else {0x0000040})
prop SYNCRL2_CESEC2 :: (if (self.SYNCRL2_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCRL2_SETUP == "1 cycle") {0x00000001} else {if (self.SYNCRL2_SETUP == "2 cycles") {0x00000002} else {0x00000003}}})
prop SYNCWL2_CESEC2 :: (if (self.SYNCWL2_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCWL2_SETUP == "1 cycle") {0x00000004} else {if (self.SYNCWL2_SETUP == "2 cycles") {0x00000008} else {0x0000000c}}})
prop CEEXT2_CESEC2 :: (if (self.CEEXT2_SETUP == "Inactive") {0x00000000} else {0x0000010})
prop RENEN2_CESEC2 :: (if (self.RENEN2_SETUP == "ADS Mode") {0x00000000} else {0x0000020})
prop SNCCLK2_CESEC2 :: (if (self.SNCCLK2_SETUP == "Sync. to ECLKOUT1") {0x00000000} else {0x0000040})
prop SYNCRL3_CESEC3 :: (if (self.SYNCRL3_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCRL3_SETUP == "1 cycle") {0x00000001} else {if (self.SYNCRL3_SETUP == "2 cycles") {0x00000002} else {0x00000003}}})
prop SYNCWL3_CESEC3 :: (if (self.SYNCWL3_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCWL3_SETUP == "1 cycle") {0x00000004} else {if (self.SYNCWL3_SETUP == "2 cycles") {0x00000008} else {0x0000000c}}})
prop CEEXT3_CESEC3 :: (if (self.CEEXT3_SETUP == "Inactive") {0x00000000} else {0x0000010})
prop RENEN3_CESEC3 :: (if (self.RENEN3_SETUP == "ADS Mode") {0x00000000} else {0x0000020})
prop SNCCLK3_CESEC3 :: (if (self.SNCCLK3_SETUP == "Sync. to ECLKOUT1") {0x00000000} else {0x0000040})
prop TRC_SDCTL :: ((self.TRC_SETUP << 12))
prop TRP_SDCTL :: ((self.TRP_SETUP << 16))
prop TRCD_SDCTL :: ((self.TRCD_SETUP << 20))
prop INIT_SDCTL :: (if (self.INIT_SETUP == "Initialize") {0x01000000} else {0x00000000})
prop RFEN_SDCTL :: (if (self.RFEN_SETUP == "Enable") {0x02000000} else {0x00000000})
prop SDCSZ_SDCTL :: (if (self.SDCSZ_SETUP == " 8 addresses") {0x04000000} else {if (self.SDCSZ_SETUP == "10 addresses") {0x08000000} else {0x00000000}})
prop SDRSZ_SDCTL :: (if (self.SDRSZ_SETUP == "12 addresses") {0x10000000} else {if (self.SDRSZ_SETUP == "13 addresses") {0x20000000} else {0x00000000}})
prop SDBSZ_SDCTL :: (if (self.SDBSZ_SETUP == "Four banks") {0x40000000} else {0x00000000})
prop SLFRFR_SDCTL :: (if (self.SLFRFR_SETUP == "Enable") {0x00000001} else {0x00000000})
prop PERIOD_SDTIM2 :: ((self.PERIOD_SETUP2))
prop XRFR_SDTIM :: (((self.XRFR_SETUP - 1) << 24))
prop TCL_SDEXT :: ((self.TCL_SETUP - 2))
prop TRAS_SDEXT :: (((self.TRAS_SETUP - 1) << 1))
prop TRRD_SDEXT :: ((self.TRRD_SETUP - 2) << 4)
prop TWR_SDEXT :: (((self.TWR_SETUP - 1) << 5))
prop THZP_SDEXT :: (((self.THZP_SETUP - 1) << 7))
prop RD2RD_SDEXT :: (((self.RD2RD_SETUP - 1) << 9))
prop RD2DEAC_SDEXT :: (((self.RD2DEAC_SETUP - 1) << 10))
prop RD2WR_SDEXT :: (((self.RD2WR_SETUP - 1) << 12))
prop R2WDQM_SDEXT :: (((self.R2WDQM_SETUP - 1) << 15))
prop WR2WR_SDEXT :: (((self.WR2WR_SETUP - 1) << 17))
prop WR2DEAC_SDEXT :: (((self.WR2DEAC_SETUP - 1) << 18))
prop WR2RD_SDEXT :: (((self.WR2RD_SETUP - 1) << 20))
prop GBLCTL_VALUE_update :: (0x00000004 | self.NOHOLD_GBLCTL() | self.CLK4EN_GBLCTL() | self.CLK6EN_GBLCTL() | self.EK1EN_GBLCTL() | self.EK2EN_GBLCTL() | self.EK1HZ_GBLCTL() | self.EK2HZ_GBLCTL() | self.EK2RATE_GBLCTL() | self.BRMODE_GBLCTL())
prop GBLCTL_SETUP_update :: (self.NOHOLD_SETUP = if ($1 & 0x00000080) {"Disable Hold"} else {"Enable Hold"}, self.CLK4EN_SETUP = if ($1 & 0x00000010) {"Enabled to clock"} else {"Held high"}, self.CLK6EN_SETUP = if ($1 & 0x00000008) {"Enabled to clock"} else {"Held high"}, self.EK1EN_SETUP = if ($1 & 0x00000020) {"Enabled to clock"} else {"Held low"}, self.EK2EN_SETUP = if ($1 & 0x00010000) {"Enabled to clock"} else {"Held low"}, self.EK1HZ_SETUP = if ($1 & 0x00000040) {"High-Z during hold"} else {"Clock during hold"}, self.EK2HZ_SETUP = if ($1 & 0x00020000) {"High-Z during hold"} else {"Clock during hold"}, self.BRMODE_SETUP = if ($1 & 0x00002000) {"access/refresh pending or in progress"} else {"access pending or in progress"}, $a = $1 & 0x000C0000, if ($a == 0x00080000) {self.EK2RATE_SETUP = "1/4x EMIF input clock"} else {self.EK2RATE_SETUP = if ($1 & 0x00040000) {"1/2x EMIF input clock"} else {"1x EMIF input clock"}})
prop CECTL0_VALUE_update :: (self.MTYPE0_CECTL0() | self.RDHLD0_CECTL0() | self.RDSTRB0_CECTL0() | self.RDSETUP0_CECTL0() | self.WRHLD0_CECTL0() | self.WRHLDMSB0_CECTL0() | self.WRSETUP0_CECTL0() | self.WRSTRB0_CECTL0() | self.TA0_CECTL0())
prop CECTL0_SETUP_update :: (self.MTYPE0_SETUP = ($a = ($1 & 0x000000f0), if ($a == 0x00000000) {" 8-bit async. interf."} else {if ($a == 0x00000010) {"16-bit async. interf."} else {if ($a == 0x00000020) {"32-bit async. interf."} else {if ($a == 0x00000030) {"32-bit SDRAM"} else {if ($a == 0x00000040) {"32-bit prog. sync. mem"} else {if ($a == 0x00000080) {" 8-bit SDRAM"} else {if ($a == 0x00000090) {"16-bit SDRAM"} else {if ($a == 0x000000a0) {" 8-bit prog. sync. mem"} else {if ($a == 0x000000b0) {"16-bit prog. sync. mem"} else {if ($a == 0x000000c0) {"64-bit async. interf."} else {if ($a == 0x000000d0) {"64-bit SDRAM"} else {"64-bit prog. sync. mem"}}}}}}}}}}}), self.RDHLD0_SETUP = ($1 & 0x00000007), self.RDSTRB0_SETUP = (($1 & 0x00003F00) >> 8), self.RDSETUP0_SETUP = (($1 & 0x000F0000) >> 16), self.WRHLD0_SETUP = ((($1 & 0x00300000) >> 20) + (($1 & 0x00000008) >> 1)), self.WRSTRB0_SETUP = (($1 & 0x0FC00000) >> 22), self.WRSETUP0_SETUP = (($1 >> 28) & 0xF), self.TA0_SETUP = ($1 & 0x0000c000) >> 14)
prop CECTL1_VALUE_update :: (self.MTYPE1_CECTL1() | self.RDHLD1_CECTL1() | self.RDSTRB1_CECTL1() | self.RDSETUP1_CECTL1() | self.WRHLD1_CECTL1() | self.WRHLDMSB1_CECTL1() | self.WRSETUP1_CECTL1() | self.WRSTRB1_CECTL1() | self.TA1_CECTL1())
prop CECTL1_SETUP_update :: (self.MTYPE1_SETUP = ($a = ($1 & 0x000000f0), if ($a == 0x00000000) {" 8-bit async. interf."} else {if ($a == 0x00000010) {"16-bit async. interf."} else {if ($a == 0x00000020) {"32-bit async. interf."} else {if ($a == 0x00000030) {"32-bit SDRAM"} else {if ($a == 0x00000040) {"32-bit prog. sync. mem"} else {if ($a == 0x00000080) {" 8-bit SDRAM"} else {if ($a == 0x00000090) {"16-bit SDRAM"} else {if ($a == 0x000000a0) {" 8-bit prog. sync. mem"} else {if ($a == 0x000000b0) {"16-bit prog. sync. mem"} else {if ($a == 0x000000c0) {"64-bit async. interf."} else {if ($a == 0x000000d0) {"64-bit SDRAM"} else {"64-bit prog. sync. mem"}}}}}}}}}}}), self.RDHLD1_SETUP = ($1 & 0x00000007), self.RDSTRB1_SETUP = (($1 & 0x00003F00) >> 8), self.RDSETUP1_SETUP = (($1 & 0x000F0000) >> 16), self.WRHLD1_SETUP = ((($1 & 0x00300000) >> 20) + (($1 & 0x00000008) >> 1)), self.WRSTRB1_SETUP = (($1 & 0x0FC00000) >> 22), self.WRSETUP1_SETUP = (($1 >> 28) & 0xF), self.TA1_SETUP = ($1 & 0x0000c000) >> 14)
prop CECTL2_VALUE_update :: (self.MTYPE2_CECTL2() | self.RDHLD2_CECTL2() | self.RDSTRB2_CECTL2() | self.RDSETUP2_CECTL2() | self.WRHLD2_CECTL2() | self.WRHLDMSB2_CECTL2() | self.WRSETUP2_CECTL2() | self.WRSTRB2_CECTL2() | self.TA2_CECTL2())
prop CECTL2_SETUP_update :: (self.MTYPE2_SETUP = ($a = ($1 & 0x000000f0), if ($a == 0x00000000) {" 8-bit async. interf."} else {if ($a == 0x00000010) {"16-bit async. interf."} else {if ($a == 0x00000020) {"32-bit async. interf."} else {if ($a == 0x00000030) {"32-bit SDRAM"} else {if ($a == 0x00000040) {"32-bit prog. sync. mem"} else {if ($a == 0x00000080) {" 8-bit SDRAM"} else {if ($a == 0x00000090) {"16-bit SDRAM"} else {if ($a == 0x000000a0) {" 8-bit prog. sync. mem"} else {if ($a == 0x000000b0) {"16-bit prog. sync. mem"} else {if ($a == 0x000000c0) {"64-bit async. interf."} else {if ($a == 0x000000d0) {"64-bit SDRAM"} else {"64-bit prog. sync. mem"}}}}}}}}}}}), self.RDHLD2_SETUP = ($1 & 0x00000007), self.RDSTRB2_SETUP = (($1 & 0x00003F00) >> 8), self.RDSETUP2_SETUP = (($1 & 0x000F0000) >> 16), self.WRHLD2_SETUP = ((($1 & 0x00300000) >> 20) + (($1 & 0x00000008) >> 1)), self.WRSTRB2_SETUP = (($1 & 0x0FC00000) >> 22), self.WRSETUP2_SETUP = (($1 >> 28) & 0xF), self.TA2_SETUP = ($1 & 0x0000c000) >> 14)
prop CECTL3_VALUE_update :: (self.MTYPE3_CECTL3() | self.RDHLD3_CECTL3() | self.RDSTRB3_CECTL3() | self.RDSETUP3_CECTL3() | self.WRHLD3_CECTL3() | self.WRHLDMSB3_CECTL3() | self.WRSETUP3_CECTL3() | self.WRSTRB3_CECTL3() | self.TA3_CECTL3())
prop CECTL3_SETUP_update :: (self.MTYPE3_SETUP = ($a = ($1 & 0x000000f0), if ($a == 0x00000000) {" 8-bit async. interf."} else {if ($a == 0x00000010) {"16-bit async. interf."} else {if ($a == 0x00000020) {"32-bit async. interf."} else {if ($a == 0x00000030) {"32-bit SDRAM"} else {if ($a == 0x00000040) {"32-bit prog. sync. mem"} else {if ($a == 0x00000080) {" 8-bit SDRAM"} else {if ($a == 0x00000090) {"16-bit SDRAM"} else {if ($a == 0x000000a0) {" 8-bit prog. sync. mem"} else {if ($a == 0x000000b0) {"16-bit prog. sync. mem"} else {if ($a == 0x000000c0) {"64-bit async. interf."} else {if ($a == 0x000000d0) {"64-bit SDRAM"} else {"64-bit prog. sync. mem"}}}}}}}}}}}), self.RDHLD3_SETUP = ($1 & 0x00000007), self.RDSTRB3_SETUP = (($1 & 0x00003F00) >> 8), self.RDSETUP3_SETUP = (($1 & 0x000F0000) >> 16), self.WRHLD3_SETUP = ((($1 & 0x00300000) >> 20) + (($1 & 0x00000008) >> 1)), self.WRSTRB3_SETUP = (($1 & 0x0FC00000) >> 22), self.WRSETUP3_SETUP = (($1 >> 28) & 0xF), self.TA3_SETUP = ($1 & 0x0000c000) >> 14)
prop SDCTL_VALUE_update :: (self.TRC_SDCTL() | self.TRP_SDCTL() | self.SLFRFR_SDCTL() | self.TRCD_SDCTL() | self.INIT_SDCTL() | self.RFEN_SDCTL() | self.SDCSZ_SDCTL() | self.SDRSZ_SDCTL() | self.SDBSZ_SDCTL())
prop SDCTL_SETUP_update :: (self.TRC_SETUP = ($1 & 0x0000F000) >> 12, self.TRP_SETUP = ($1 & 0x000F0000) >> 16, self.TRCD_SETUP = ($1 & 0x00F00000) >> 20, self.INIT_SETUP = ($a = ($1 & 0x01000000), if ($a == 0x01000000) {"Initialize"} else {"No effect"}), self.RFEN_SETUP = ($a = ($1 & 0x02000000), if ($a == 0x02000000) {"Enable"} else {"Disable"}), self.SDCSZ_SETUP = ($a = ($1 & 0x0c000000), if ($a == 0x04000000) {" 8 addresses"} else {if ($a == 0x08000000) {"10 addresses"} else {" 9 addresses"}}), self.SDRSZ_SETUP = ($a = ($1 & 0x30000000), if ($a == 0x10000000) {"12 addresses"} else {if ($a == 0x20000000) {"13 addresses"} else {"11 addresses"}}), self.SDBSZ_SETUP = ($a = ($1 & 0x40000000), if ($a == 0x40000000) {"Four banks"} else {"Two banks"}), self.SLFRFR_SETUP = ($a = ($1 & 0x00000001), if ($a == 0x00000001) {"Enable"} else {"Disable"}))
prop SDTIM_VALUE_update :: (self.PERIOD_SDTIM2() | self.XRFR_SDTIM() | 0x005dc000)
prop SDTIM_SETUP_update :: (self.PERIOD_SETUP2 = ($1 & 0x00000FFF), self.XRFR_SETUP = (($1 & 0x03000000) >> 24) + 1)
prop SDEXT_VALUE_update :: (self.TCL_SDEXT() | self.TRAS_SDEXT() | self.TRRD_SDEXT() | self.TWR_SDEXT() | self.THZP_SDEXT() | self.RD2RD_SDEXT() | self.RD2DEAC_SDEXT() | self.RD2WR_SDEXT() | self.R2WDQM_SDEXT() | self.WR2WR_SDEXT() | self.WR2DEAC_SDEXT() | self.WR2RD_SDEXT())
prop SDEXT_SETUP_update :: (self.TCL_SETUP = ($1 & 0x00000001) + 2, self.TRAS_SETUP = (($1 & 0x0000000E) >> 1) + 1, self.TRRD_SETUP = (($1 & 0x00000010) >> 4) + 2, self.TWR_SETUP = (($1 & 0x00000060) >> 5) + 1, self.THZP_SETUP = (($1 & 0x00000180) >> 7) + 1, self.RD2RD_SETUP = (($1 & 0x00000200) >> 9) + 1, self.RD2DEAC_SETUP = (($1 & 0x00000c00) >> 10) + 1, self.RD2WR_SETUP = (($1 & 0x00007000) >> 12) + 1, self.R2WDQM_SETUP = (($1 & 0x00018000) >> 15) + 1, self.WR2WR_SETUP = (($1 & 0x00020000) >> 17) + 1, self.WR2DEAC_SETUP = (($1 & 0x000c0000) >> 18) + 1, self.WR2RD_SETUP = (($1 & 0x00100000) >> 20) + 1)
prop CESEC0_VALUE_update :: (self.SYNCRL0_CESEC0() | self.SYNCWL0_CESEC0() | self.CEEXT0_CESEC0() | self.RENEN0_CESEC0() | self.SNCCLK0_CESEC0())
prop CESEC0_SETUP_update :: (self.SYNCRL0_SETUP = ($a = ($1 & 0x00000003), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000001) {"1 cycle"} else {if ($a == 0x00000002) {"2 cycles"} else {"3 cycles"}}}), self.SYNCWL0_SETUP = ($a = ($1 & 0x0000000C), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000004) {"1 cycle"} else {if ($a == 0x00000008) {"2 cycles"} else {"3 cycles"}}}), self.CEEXT0_SETUP = ($a = ($1 & 0x00000010), if ($a == 0x00000000) {"Inactive"} else {"Active"}), self.RENEN0_SETUP = ($a = ($1 & 0x00000020), if ($a == 0x00000000) {"ADS Mode"} else {"Read Enable Mode"}), self.SNCCLK0_SETUP = ($a = ($1 & 0x00000040), if ($a == 0x00000000) {"Sync. to ECLKOUT1"} else {"Sync. to ECLKOUT2"}))
prop CESEC1_VALUE_update :: (self.SYNCRL1_CESEC1() | self.SYNCWL1_CESEC1() | self.CEEXT1_CESEC1() | self.RENEN1_CESEC1() | self.SNCCLK1_CESEC1())
prop CESEC1_SETUP_update :: (self.SYNCRL1_SETUP = ($a = ($1 & 0x00000003), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000001) {"1 cycle"} else {if ($a == 0x00000002) {"2 cycles"} else {"3 cycles"}}}), self.SYNCWL1_SETUP = ($a = ($1 & 0x0000000C), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000004) {"1 cycle"} else {if ($a == 0x00000008) {"2 cycles"} else {"3 cycles"}}}), self.CEEXT1_SETUP = ($a = ($1 & 0x00000010), if ($a == 0x00000000) {"Inactive"} else {"Active"}), self.RENEN1_SETUP = ($a = ($1 & 0x00000020), if ($a == 0x00000000) {"ADS Mode"} else {"Read Enable Mode"}), self.SNCCLK1_SETUP = ($a = ($1 & 0x00000040), if ($a == 0x00000000) {"Sync. to ECLKOUT1"} else {"Sync. to ECLKOUT2"}))
prop CESEC2_VALUE_update :: (self.SYNCRL2_CESEC2() | self.SYNCWL2_CESEC2() | self.CEEXT2_CESEC2() | self.RENEN2_CESEC2() | self.SNCCLK2_CESEC2())
prop CESEC2_SETUP_update :: (self.SYNCRL2_SETUP = ($a = ($1 & 0x00000003), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000001) {"1 cycle"} else {if ($a == 0x00000002) {"2 cycles"} else {"3 cycles"}}}), self.SYNCWL2_SETUP = ($a = ($1 & 0x0000000C), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000004) {"1 cycle"} else {if ($a == 0x00000008) {"2 cycles"} else {"3 cycles"}}}), self.CEEXT2_SETUP = ($a = ($1 & 0x00000010), if ($a == 0x00000000) {"Inactive"} else {"Active"}), self.RENEN2_SETUP = ($a = ($1 & 0x00000020), if ($a == 0x00000000) {"ADS Mode"} else {"Read Enable Mode"}), self.SNCCLK2_SETUP = ($a = ($1 & 0x00000040), if ($a == 0x00000000) {"Sync. to ECLKOUT1"} else {"Sync. to ECLKOUT2"}))
prop CESEC3_VALUE_update :: (self.SYNCRL3_CESEC3() | self.SYNCWL3_CESEC3() | self.CEEXT3_CESEC3() | self.RENEN3_CESEC3() | self.SNCCLK3_CESEC3())
prop CESEC3_SETUP_update :: (self.SYNCRL3_SETUP = ($a = ($1 & 0x00000003), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000001) {"1 cycle"} else {if ($a == 0x00000002) {"2 cycles"} else {"3 cycles"}}}), self.SYNCWL3_SETUP = ($a = ($1 & 0x0000000C), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000004) {"1 cycle"} else {if ($a == 0x00000008) {"2 cycles"} else {"3 cycles"}}}), self.CEEXT3_SETUP = ($a = ($1 & 0x00000010), if ($a == 0x00000000) {"Inactive"} else {"Active"}), self.RENEN3_SETUP = ($a = ($1 & 0x00000020), if ($a == 0x00000000) {"ADS Mode"} else {"Read Enable Mode"}), self.SNCCLK3_SETUP = ($a = ($1 & 0x00000040), if ($a == 0x00000000) {"Sync. to ECLKOUT1"} else {"Sync. to ECLKOUT2"}))
global gUser :: "USER" {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gSetOf :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gNumOf :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gDirty :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gInitFlag :: 1 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gInit :: = ($a = 0, $b = 0, scan ($i; self) {if ($i.IsConfObj()) {$a += 1, if (self.isFinite) {$b |= 1 << $i.iId} } }, self.gNumOf = $a, self.gSetOf = $b, if (self.gInitFlag == 0) {self.localInit()} , self.gInitFlag = 1) {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
inst iComment :: if self.iDelUser == "USER" {"<add comments here>"} else {self.iDelMsg} {
prop Type :: "{21455EA3-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "comment"
prop JSName :: "comment"
prop Visible :: 1
prop Writable :: if self.iDelUser == "USER" {1} else {0}
prop NoGen :: 1
}
inst iIsUsed :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
inst iId :: 0 {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01
prop Visible :: 0
prop Writable :: 1
prop NoGen :: 1
}
inst iDelUser :: "USER" {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
inst iDelMsg :: "ok" {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
inst cConfigGen :: = ((hEmifa.EMIFA_INIT_ENABLE == 1) && (hEmifa.EMIFA_INIT == self) && (hEmifa.EMIFA_INIT != EMIFA_NOTHING)) {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop NoGen :: 1
prop Visible :: 0
}
inst cConfigArg0 :: = hEmifa.EMIFA_INIT {
prop Type :: "{21455EA3-B96A-11cf-9BFE-0000C0AC14C7}"
prop MemberType :: emifaCfg
prop Label :: "Pre-initialize Config"
prop Visible :: 0
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 0
prop cPreVal :: "&"
}
inst NOHOLD_SETUP :: "Enable Hold" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Enable Hold,Disable Hold"
prop Label :: "External HOLD disable (NOHOLD)"
prop JSName :: "emifaGblctlNoHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.NOHOLD_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst CLK4EN_SETUP :: "Enabled to clock" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Held high,Enabled to clock"
prop Label :: "CLKOUT4 Enable (CLK4EN)"
prop JSName :: "emifaGblctlClk4en"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.CLK4EN_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst CLK6EN_SETUP :: "Enabled to clock" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Held high,Enabled to clock"
prop Label :: "CLKOUT6 Enable (CLK6EN)"
prop JSName :: "emifaGblctlClk6en"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.CLK6EN_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst EK1EN_SETUP :: "Enabled to clock" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Held low,Enabled to clock"
prop Label :: "ECLKOUT1 Enable (EK1EN)"
prop JSName :: "emifaGblctlEk1en"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.EK1EN_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst EK2EN_SETUP :: "Enabled to clock" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Held low,Enabled to clock"
prop Label :: "ECLKOUT2 Enable (EK2EN)"
prop JSName :: "emifaGblctlEk2en"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.EK2EN_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst EK1HZ_SETUP :: "High-Z during hold" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Clock during hold,High-Z during hold"
prop Label :: "ECLKOUT1 High-Z Control (EK1HZ)"
prop JSName :: "emifaGblctlEk1hz"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.EK1HZ_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst EK2HZ_SETUP :: "Clock during hold" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Clock during hold,High-Z during hold"
prop Label :: "ECLKOUT2 High-Z Control (EK2HZ)"
prop JSName :: "emifaGblctlEk2hz"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.EK2HZ_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst EK2RATE_SETUP :: "1/4x EMIF input clock" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "1x EMIF input clock,1/2x EMIF input clock,1/4x EMIF input clock"
prop Label :: "ECLKOUT2 Rate (EK2RATE)"
prop JSName :: "emifaGblctlEk2rate"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.EK2RATE_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst BRMODE_SETUP :: "access/refresh pending or in progress" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "access/refresh pending or in progress,access pending or in progress"
prop Label :: "Bus Request Mode"
prop JSName :: "emifaGblctlBrmode"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.BRMODE_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst MTYPE0_SETUP :: "32-bit async. interf." {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 8-bit async. interf.,16-bit async. interf.,32-bit async. interf.,64-bit async. interf., 8-bit SDRAM,16-bit SDRAM,32-bit SDRAM,64-bit SDRAM, 8-bit prog. sync. mem,16-bit prog. sync. mem,32-bit prog. sync. mem,64-bit prog. sync. mem"
prop Label :: "Memory Type (MTYPE)"
prop JSName :: "emifaCectl0Mtype"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (self.MTYPE0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok")
}
inst RDSTRB0_SETUP :: 63 {
prop Label :: "Read Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl0ReadStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.RDSTRB0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst RDSETUP0_SETUP :: 15 {
prop Label :: "Read Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl0ReadSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.RDSETUP0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst RDHLD0_SETUP :: 3 {
prop Label :: "Read Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl0ReadHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycless")} else {self.RDHLD0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"}} else {if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.RDHLD0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"}})
}
inst WRSTRB0_SETUP :: 63 {
prop Label :: "Write Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl0WriteStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.WRSTRB0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst WRSETUP0_SETUP :: 15 {
prop Label :: "Write Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl0WriteSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.WRSETUP0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst WRHLD0_SETUP :: 3 {
prop Label :: "Write Hold Width (WRHLD-WRHLDMSB) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl0WriteHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.WRHLD0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst TA0_SETUP :: 3 {
prop Label :: "Turn around time (TA) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl0Ta"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 1 || $1 > 3) {self.error(" Minimum: 1 ECLKOU1 cycle - Maximum : 3 ECLKOU1 cycles")} else {self.TA0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst MTYPE1_SETUP :: "32-bit async. interf." {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 8-bit async. interf.,16-bit async. interf.,32-bit async. interf.,64-bit async. interf., 8-bit SDRAM,16-bit SDRAM,32-bit SDRAM,64-bit SDRAM, 8-bit prog. sync. mem,16-bit prog. sync. mem,32-bit prog. sync. mem,64-bit prog. sync. mem"
prop Label :: "Memory Type (MTYPE)"
prop JSName :: "emifaCectl1Mtype"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (self.MTYPE1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok")
}
inst RDSTRB1_SETUP :: 63 {
prop Label :: "Read Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl1ReadStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.RDSTRB1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst RDSETUP1_SETUP :: 15 {
prop Label :: "Read Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl1ReadSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.RDSETUP1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst RDHLD1_SETUP :: 3 {
prop Label :: "Read Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl1ReadHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycless")} else {self.RDHLD1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"}} else {if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.RDHLD1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"}})
}
inst WRSTRB1_SETUP :: 63 {
prop Label :: "Write Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl1WriteStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.WRSTRB1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst WRSETUP1_SETUP :: 15 {
prop Label :: "Write Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl1WriteSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.WRSETUP1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst WRHLD1_SETUP :: 3 {
prop Label :: "Write Hold Width (WRHLD - WHLDMSB) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl1WriteHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.WRHLD1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst TA1_SETUP :: 3 {
prop Label :: "Turn around time (TA) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl1Ta"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 1 || $1 > 3) {self.error(" Minimum: 1 ECLKOU1 cycle - Maximum : 3 ECLKOU1 cycles")} else {self.TA1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst MTYPE2_SETUP :: "32-bit async. interf." {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 8-bit async. interf.,16-bit async. interf.,32-bit async. interf.,64-bit async. interf., 8-bit SDRAM,16-bit SDRAM,32-bit SDRAM,64-bit SDRAM, 8-bit prog. sync. mem,16-bit prog. sync. mem,32-bit prog. sync. mem,64-bit prog. sync. mem"
prop Label :: "Memory Type (MTYPE)"
prop JSName :: "emifaCectl2Mtype"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (self.MTYPE2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok")
}
inst RDSTRB2_SETUP :: 63 {
prop Label :: "Read Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl2ReadStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.RDSTRB2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst RDSETUP2_SETUP :: 15 {
prop Label :: "Read Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl2ReadSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.RDSETUP2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst RDHLD2_SETUP :: 3 {
prop Label :: "Read Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl2ReadHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycless")} else {self.RDHLD2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"}} else {if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.RDHLD2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"}})
}
inst WRSTRB2_SETUP :: 63 {
prop Label :: "Write Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl2WriteStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.WRSTRB2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst WRSETUP2_SETUP :: 15 {
prop Label :: "Write Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl2WriteSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.WRSETUP2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst WRHLD2_SETUP :: 3 {
prop Label :: "Write Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl2WriteHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.WRHLD2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst TA2_SETUP :: 3 {
prop Label :: "Turn around time (TA) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl2Ta"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 1 || $1 > 3) {self.error(" Minimum: 1 ECLKOU1 cycle - Maximum : 3 ECLKOU1 cycles")} else {self.TA2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst MTYPE3_SETUP :: "32-bit async. interf." {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 8-bit async. interf.,16-bit async. interf.,32-bit async. interf.,64-bit async. interf., 8-bit SDRAM,16-bit SDRAM,32-bit SDRAM,64-bit SDRAM, 8-bit prog. sync. mem,16-bit prog. sync. mem,32-bit prog. sync. mem,64-bit prog. sync. mem"
prop Label :: "Memory Type (MTYPE)"
prop JSName :: "emifaCectl3Mtype"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (self.MTYPE3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok")
}
inst RDSTRB3_SETUP :: 63 {
prop Label :: "Read Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl3ReadStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.RDSTRB3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst RDSETUP3_SETUP :: 15 {
prop Label :: "Read Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl3ReadSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.RDSETUP3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst RDHLD3_SETUP :: 3 {
prop Label :: "Read Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl3ReadHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycless")} else {self.RDHLD3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"}} else {if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.RDHLD3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"}})
}
inst WRSTRB3_SETUP :: 63 {
prop Label :: "Write Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl3WriteStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.WRSTRB3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst WRSETUP3_SETUP :: 15 {
prop Label :: "Write Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl3WriteSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.WRSETUP3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst WRHLD3_SETUP :: 3 {
prop Label :: "Write Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl3WriteHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.WRHLD3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst TA3_SETUP :: 3 {
prop Label :: "Turn around time (TA) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaCectl3Ta"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 1 || $1 > 3) {self.error(" Minimum: 1 ECLKOU1 cycle - Maximum : 3 ECLKOU1 cycles")} else {self.TA3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst SYNCRL0_SETUP :: "2 cycles" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "0 cycle,1 cycle,2 cycles,3 cycles"
prop Label :: "Sync. interf. data read latency (SYNCRL)"
prop JSName :: "emifaCesec0Syncrl"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (self.SYNCRL0_SETUP = $1, self.CESEC0_VALUE = self.CESEC0_VALUE_update(), "ok")
}
inst SYNCWL0_SETUP :: "0 cycle" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "0 cycle,1 cycle,2 cycles,3 cycles"
prop Label :: "Sync. interf. data write latency (SYNCWL)"
prop Visible :: 1
prop JSName :: "emifaCesec0Syncwl"
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (self.SYNCWL0_SETUP = $1, self.CESEC0_VALUE = self.CESEC0_VALUE_update(), "ok")
}
inst CEEXT0_SETUP :: "Inactive" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Inactive,Active"
prop Label :: "CE Extension Register (CEEXT)"
prop JSName :: "emifaCesec0Ceext"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (self.CEEXT0_SETUP = $1, self.CESEC0_VALUE = self.CESEC0_VALUE_update(), "ok")
}
inst RENEN0_SETUP :: "ADS Mode" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "ADS Mode,Read Enable Mode"
prop Label :: "Read Enable Enable (RENEN)"
prop JSName :: "emifaCesec0Renen"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (self.RENEN0_SETUP = $1, self.CESEC0_VALUE = self.CESEC0_VALUE_update(), "ok")
}
inst SNCCLK0_SETUP :: "Sync. to ECLKOUT1" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Sync. to ECLKOUT1,Sync. to ECLKOUT2"
prop Label :: "Synchronization Clock (SNCCLK)"
prop JSName :: "emifaCesec0Sncclk"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (self.SNCCLK0_SETUP = $1, self.CESEC0_VALUE = self.CESEC0_VALUE_update(), "ok")
}
inst SYNCRL1_SETUP :: "2 cycles" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "0 cycle,1 cycle,2 cycles,3 cycles"
prop Label :: "Sync. interf. data read latency (SYNCRL)"
prop JSName :: "emifaCesec1Syncrl"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (self.SYNCRL1_SETUP = $1, self.CESEC1_VALUE = self.CESEC1_VALUE_update(), "ok")
}
inst SYNCWL1_SETUP :: "0 cycle" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "0 cycle,1 cycle,2 cycles,3 cycles"
prop Label :: "Sync. interf. data write latency (SYNCWL)"
prop JSName :: "emifaCesec1Syncwl"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (self.SYNCWL1_SETUP = $1, self.CESEC1_VALUE = self.CESEC1_VALUE_update(), "ok")
}
inst CEEXT1_SETUP :: "Inactive" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Inactive,Active"
prop Label :: "CE Extension Register (CEEXT)"
prop JSName :: "emifaCesec1Ceext"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (self.CEEXT1_SETUP = $1, self.CESEC1_VALUE = self.CESEC1_VALUE_update(), "ok")
}
inst RENEN1_SETUP :: "ADS Mode" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "ADS Mode,Read Enable Mode"
prop Label :: "Read Enable Enable (RENEN)"
prop JSName :: "emifaCesec1Renen"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (self.RENEN1_SETUP = $1, self.CESEC1_VALUE = self.CESEC1_VALUE_update(), "ok")
}
inst SNCCLK1_SETUP :: "Sync. to ECLKOUT1" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Sync. to ECLKOUT1,Sync. to ECLKOUT2"
prop Label :: "Synchronization Clock (SNCCLK)"
prop JSName :: "emifaCesec1Sncclk"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (self.SNCCLK1_SETUP = $1, self.CESEC1_VALUE = self.CESEC1_VALUE_update(), "ok")
}
inst SYNCRL2_SETUP :: "2 cycles" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "0 cycle,1 cycle,2 cycles,3 cycles"
prop Label :: "Sync. interf. data read latency (SYNCRL)"
prop JSName :: "emifaCesec2Syncrl"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (self.SYNCRL2_SETUP = $1, self.CESEC2_VALUE = self.CESEC2_VALUE_update(), "ok")
}
inst SYNCWL2_SETUP :: "0 cycle" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "0 cycle,1 cycle,2 cycles,3 cycles"
prop Label :: "Sync. interf. data write latency (SYNCWL)"
prop JSName :: "emifaCesec2Syncwl"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (self.SYNCWL2_SETUP = $1, self.CESEC2_VALUE = self.CESEC2_VALUE_update(), "ok")
}
inst CEEXT2_SETUP :: "Inactive" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Inactive,Active"
prop Label :: "CE Extension Register (CEEXT)"
prop JSName :: "emifaCesec2Ceext"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (self.CEEXT2_SETUP = $1, self.CESEC2_VALUE = self.CESEC2_VALUE_update(), "ok")
}
inst RENEN2_SETUP :: "ADS Mode" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "ADS Mode,Read Enable Mode"
prop Label :: "Read Enable Enable (RENEN)"
prop JSName :: "emifaCesec2Renen"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (self.RENEN2_SETUP = $1, self.CESEC2_VALUE = self.CESEC2_VALUE_update(), "ok")
}
inst SNCCLK2_SETUP :: "Sync. to ECLKOUT1" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Sync. to ECLKOUT1,Sync. to ECLKOUT2"
prop Label :: "Synchronization Clock (SNCCLK)"
prop JSName :: "emifaCesec2Sncclk"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (self.SNCCLK2_SETUP = $1, self.CESEC2_VALUE = self.CESEC2_VALUE_update(), "ok")
}
inst SYNCRL3_SETUP :: "2 cycles" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "0 cycle,1 cycle,2 cycles,3 cycles"
prop Label :: "Sync. interf. data read latency (SYNCRL)"
prop JSName :: "emifaCesec3Syncrl"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (self.SYNCRL3_SETUP = $1, self.CESEC3_VALUE = self.CESEC3_VALUE_update(), "ok")
}
inst SYNCWL3_SETUP :: "0 cycle" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "0 cycle,1 cycle,2 cycles,3 cycles"
prop Label :: "Sync. interf. data write latency (SYNCWL)"
prop JSName :: "emifaCesec3Syncwl"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (self.SYNCWL3_SETUP = $1, self.CESEC3_VALUE = self.CESEC3_VALUE_update(), "ok")
}
inst CEEXT3_SETUP :: "Inactive" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Inactive,Active"
prop Label :: "CE Extension Register (CEEXT)"
prop JSName :: "emifaCesec3Ceext"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (self.CEEXT3_SETUP = $1, self.CESEC3_VALUE = self.CESEC3_VALUE_update(), "ok")
}
inst RENEN3_SETUP :: "ADS Mode" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "ADS Mode,Read Enable Mode"
prop Label :: "Read Enable Enable (RENEN)"
prop JSName :: "emifaCesec3Renen"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (self.RENEN3_SETUP = $1, self.CESEC3_VALUE = self.CESEC3_VALUE_update(), "ok")
}
inst SNCCLK3_SETUP :: "Sync. to ECLKOUT1" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Sync. to ECLKOUT1,Sync. to ECLKOUT2"
prop Label :: "Synchronization Clock (SNCCLK)"
prop JSName :: "emifaCesec3Sncclk"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFA_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (self.SNCCLK3_SETUP = $1, self.CESEC3_VALUE = self.CESEC3_VALUE_update(), "ok")
}
inst TRC_SETUP :: 15 {
prop Label :: "TRC = trc/(eclkout1 period-1) (TRC) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdctlTrc"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error("Minimum TRC = 0 - Maximum TRC = 15 ")} else {self.TRC_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok"})
}
inst TRP_SETUP :: 8 {
prop Label :: "TRP = trp/(eclkout1 period-1) (TRP) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdctlTrp"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error("Minimum TRP = 0 - Maximum TRP= 15 ")} else {self.TRP_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok"})
}
inst TRCD_SETUP :: 4 {
prop Label :: "TRCD = trcd/(eclkout1 period-1) (TRCD) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdctlTrcd"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error("Minimum TRCD = 0 - Maximum TRCD= 15 ")} else {self.TRCD_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok"})
}
inst INIT_SETUP :: "Initialize" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Initialize,No effect"
prop Label :: "Initialization of all SDRAMs (INIT)"
prop JSName :: "emifaSdctlInit"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.INIT_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst RFEN_SETUP :: "Enable" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Enable,Disable"
prop Label :: "SDRAM Refresh Enable (RFEN)"
prop JSName :: "emifaSdctlRfen"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.RFEN_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst SDCSZ_SETUP :: " 9 addresses" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 9 addresses, 8 addresses,10 addresses"
prop Label :: "Column Size (SDCSZ)"
prop JSName :: "emifaSdctlSdcsz"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.SDCSZ_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst SDRSZ_SETUP :: "11 addresses" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "11 addresses,12 addresses,13 addresses"
prop Label :: "Row Size (SDRSZ)"
prop JSName :: "emifaSdctlSdrsz"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.SDRSZ_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst SDBSZ_SETUP :: "Two banks" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Two banks,Four banks"
prop Label :: "Bank Size (SDBSZ)"
prop JSName :: "emifaSdctlSdbsz"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.SDBSZ_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst SLFRFR_SETUP :: "Disable" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Disable,Enable"
prop Label :: "Self-refresh mode(SLFRFR)"
prop JSName :: "emifaSdctlSlfrfr"
prop Visible :: 1
prop Writable :: if ((CSL.EMIFA_SUPPORT)) {1} else {0}
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (self.SLFRFR_SETUP = $1, self.SDCTL_VALUE = self.SDCTL_VALUE_update(), "ok")
}
inst PERIOD_SETUP2 :: 1500 {
prop Label :: "Refresh Period (ECLKOU1 cycles)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdtimEclkPeriod"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 1 || $1 > 4096) {self.error("1 cyc. < PERIOD < 4096 cyc. ")} else {self.PERIOD_SETUP2 = $1, self.SDTIM_VALUE = self.SDTIM_VALUE_update(), "ok"})
}
inst XRFR_SETUP :: 1 {
prop Label :: "Extra Refreshes Ctrl. (XRFR)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdctlXrfr"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM Control"
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 < Extra refreshes < 4 ")} else {self.XRFR_SETUP = $1, self.SDTIM_VALUE = self.SDTIM_VALUE_update(), "ok"})
}
inst TCL_SETUP :: 3 {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "CAS Latency (TCL)"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextTcl"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 2 || $1 > 3) {self.error("TCL : 2 or 3 ECLKOU1 cycles ")} else {self.TCL_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst TRAS_SETUP :: 8 {
prop Label :: "tras = TRAS + 1 (ECLKOU1 cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextTras"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 8) {self.error("1 ECLKOU1 cycle < tras < 8 ECLKOU1 cycles ")} else {self.TRAS_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst TRRD_SETUP :: 3 {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop Label :: "trrd = TRRD (2 or 3 ECLKOU1 cyc.)"
prop JSName :: "emifaSdextTrrd"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 2 || $1 > 3) {self.error("TRRD : 2 or 3 ECLKOU1 cycles ")} else {self.TRRD_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst TWR_SETUP :: 2 {
prop Label :: "twr = TWR + 1 (ECLKOU1 cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextTwr"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 ECLKOU1 cycle < twr < 4 ECLKOU1 cycles ")} else {self.TWR_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst THZP_SETUP :: 3 {
prop Label :: "thzp = THZP + 1 (ECLKOU1 cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextThzp"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 ECLKOU1 cycle < thzp < 4 ECLKOU1 cycles ")} else {self.THZP_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst RD2RD_SETUP :: 2 {
prop Label :: "READ-To-READ (ECLKOU1 cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextRd2rd"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 2) {self.error("1 < # of ECLKOU1 cycles < 2 ")} else {self.RD2RD_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst RD2DEAC_SETUP :: 4 {
prop Label :: "READ-To-DEAC/DEAB (ECLKOU1 cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextRd2deac"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 < # of ECLKOU1 cycles < 4 ")} else {self.RD2DEAC_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst RD2WR_SETUP :: 6 {
prop Label :: "READ-To-WRITE (ECLKOU1 cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextRd2wr"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 8) {self.error("1 < # of ECLKOU1 cycles < 8 ")} else {self.RD2WR_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst R2WDQM_SETUP :: 3 {
prop Label :: "READ-To-WRITE with Interrupt (BEx cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextR2wdqm"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 < # of Bex cycles < 4 ")} else {self.R2WDQM_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst WR2WR_SETUP :: 2 {
prop Label :: "WRITE-To-WRITE (ECLKOU1 cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextWr2wr"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 2) {self.error("1 < # of ECLKOU1 cycles < 2 ")} else {self.WR2WR_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst WR2DEAC_SETUP :: 2 {
prop Label :: "WRITE-To-DEAC/DEAB (ECLKOU1 cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextWr2deac"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 4) {self.error("1 < # of ECLKOU1 cycles < 4 ")} else {self.WR2DEAC_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst WR2RD_SETUP :: 2 {
prop Label :: "WRITE-To-READ (# of ECLKOU1 cyc.)"
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifaSdextWr2rd"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 1
prop TabName :: "SDRAM More Opt."
prop Set :: (if ($1 < 1 || $1 > 2) {self.error("1 < # of ECLKOU1 cycles < 2 ")} else {self.WR2RD_SETUP = $1, self.SDEXT_VALUE = self.SDEXT_VALUE_update(), "ok"})
}
inst GBLCTL_VALUE :: self.GBLCTL_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "Global Control Reg. (GBLCTL) "
prop Format :: "0x%08X"
prop JSName :: "emifaGblctl"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0xFFF00000, $b = $1 & 0x0000C000, $c = $1 & 0x00001000, $d = $1 & 0x00000003, $e = $1 & 0x000C0000, if ($a != 0) {self.error("Bit field (31..20) is reserved")} else {if ($b != 0) {self.error("Bit field (15..14) is reserved")} else {if ($c != 0) {self.error("Bit field 12 is reserved")} else {if ($d != 0) {self.error("Bit field (1..0) is reserved")} else {if ($e == 0x000C0000) {self.error("Invalid input for EK2RATE bit[19:18]")} else {self.GBLCTL_VALUE = $1 | 0x0000004, self.GBLCTL_SETUP_update($1 | 0x0000004), "ok"}}}}})
}
inst CECTL0_VALUE :: self.CECTL0_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE0 Space Control Reg. (CECTL0) "
prop Format :: "0x%08X"
prop JSName :: "emifaCectl0"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x000000F0, $b = $1 & 0x0000C000, if ($a == 0x00000070 || $a == 0x000000F0 || $a == 0x00000050 || $a == 0x00000060) {self.error("Undefined Memory type for CE Spaces - See CEx Space Pages")} else {if ($b == 0x00000000) {self.error("Minimum: 1 ECLKOUT cycle - Maximum : 3 ECLKOUT cycles")} else {self.CECTL0_VALUE = $1, self.CECTL0_SETUP_update($1), "ok"}})
}
inst CECTL1_VALUE :: self.CECTL1_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE1 Space Control Reg. (CECTL1) "
prop Format :: "0x%08X"
prop JSName :: "emifaCectl1"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x000000F0, $b = $1 & 0x0000C000, if ($a == 0x00000070 || $a == 0x000000F0 || $a == 0x00000050 || $a == 0x00000060) {self.error("Undefined Memory type for CE Spaces - See CEx Space Pages")} else {if ($b == 0x00000000) {self.error("Minimum: 1 ECLKOUT cycle - Maximum : 3 ECLKOUT cycles")} else {self.CECTL1_VALUE = $1, self.CECTL1_SETUP_update($1), "ok"}})
}
inst CECTL2_VALUE :: self.CECTL2_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE2 Space Control Reg. (CECTL2) "
prop Format :: "0x%08X"
prop JSName :: "emifaCectl2"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x000000F0, $b = $1 & 0x0000C000, if ($a == 0x00000070 || $a == 0x000000F0 || $a == 0x00000050 || $a == 0x00000060) {self.error("Undefined Memory type for CE Spaces - See CEx Space Pages")} else {if ($b == 0x00000000) {self.error("Minimum: 1 ECLKOUT cycle - Maximum : 3 ECLKOUT cycles")} else {self.CECTL2_VALUE = $1, self.CECTL2_SETUP_update($1), "ok"}})
}
inst CECTL3_VALUE :: self.CECTL3_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE3 Space Control Reg. (CECTL3) "
prop Format :: "0x%08X"
prop JSName :: "emifaCectl3"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x000000F0, $b = $1 & 0x0000C000, if ($a == 0x00000070 || $a == 0x000000F0 || $a == 0x00000050 || $a == 0x00000060) {self.error("Undefined Memory type for CE Spaces - See CEx Space Pages")} else {if ($b == 0x00000000) {self.error("Minimum: 1 ECLKOUT cycle - Maximum : 3 ECLKOUT cycles")} else {self.CECTL3_VALUE = $1, self.CECTL3_SETUP_update($1), "ok"}})
}
inst SDCTL_VALUE :: self.SDCTL_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "SDRAM Control Reg.(SDCTL) "
prop Format :: "0x%08X"
prop JSName :: "emifaSdctl"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x0c000000, if ($a == 0x0c000000) {self.error("Undefined Value for Column Size field SDCSZ")} else {$b = $1 & 0x30000000, if ($b == 0x30000000) {self.error("Undefined Value for Row Size field SDRSZ")} else {$c = $1 & 0x80000000, if ($c == 0x80000000) {self.error("Bit field 31 is reserved")} else {$d = $1 & 0x00000FFE, if ($d != 0) {self.error("Bit field(bit[1..11]) is reserved")} else {self.SDCTL_VALUE = $1, self.SDCTL_SETUP_update($1), "ok"}}}})
}
inst SDTIM_VALUE :: self.SDTIM_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "SDRAM Timing Reg.(SDTIM) "
prop Format :: "0x%08X"
prop JSName :: "emifaSdtim"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0x0000FFF, if ($a == 0x00000000) {self.error("1 cyc. < PERIOD < 4096 cyc. ")} else {$b = $1 & 0xFC000000, if ($b != 0) {self.error("Bit field(bit[26..31]) is reserved")} else {self.SDTIM_VALUE = $1 | 0x005dc000, self.SDTIM_SETUP_update($1 | 0x005dc000), "ok"}})
}
inst SDEXT_VALUE :: self.SDEXT_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "SDRAM Extended Reg.(SDEXT) "
prop Format :: "0x%08X"
prop JSName :: "emifaSdext"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0xFFE00000, if ($a != 0) {self.error("Bit field(bit[21..31]) is reserved")} else {self.SDEXT_VALUE = $1, self.SDEXT_SETUP_update($1), "ok"})
}
inst CESEC0_VALUE :: self.CESEC0_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE0 Space Secondary Control Reg. (CESEC0)"
prop Format :: "0x%08X"
prop JSName :: "emifaCesec0"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0xFFFFFF80, if ($a != 0) {self.error("Bit field(bit[7..31]) is reserved")} else {self.CESEC0_VALUE = $1, self.CESEC0_SETUP_update($1), "ok"})
}
inst CESEC1_VALUE :: self.CESEC1_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE1 Space Secondary Control Reg. (CESEC1)"
prop Format :: "0x%08X"
prop JSName :: "emifaCesec1"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0xFFFFFF80, if ($a != 0) {self.error("Bit field(bit[7..31]) is reserved")} else {self.CESEC1_VALUE = $1, self.CESEC1_SETUP_update($1), "ok"})
}
inst CESEC2_VALUE :: self.CESEC2_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE2 Space Secondary Control Reg. (CESEC2)"
prop Format :: "0x%08X"
prop JSName :: "emifaCesec2"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0xFFFFFF80, if ($a != 0) {self.error("Bit field(bit[7..31]) is reserved")} else {self.CESEC2_VALUE = $1, self.CESEC2_SETUP_update($1), "ok"})
}
inst CESEC3_VALUE :: self.CESEC3_VALUE_update() {
prop Type :: "{3EE4CB80-E273-11d0-BB8F-0000C008F2E9}"
prop Label :: "CE3 Space Secondary Control Reg. (CESEC3)"
prop Format :: "0x%08X"
prop JSName :: "emifaCesec3"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT != 0) {1} else {0}
prop NoGen :: 0
prop cGen :: 1
prop cType :: "Uint32"
prop TabName :: "Advanced"
prop Set :: ($a = $1 & 0xFFFFFF80, if ($a != 0) {self.error("Bit field(bit[7..31]) is reserved")} else {self.CESEC3_VALUE = $1, self.CESEC3_SETUP_update($1), "ok"})
}
}
type hEmifa {
prop IsContainedIn :: EMIFAFOLDER
prop name :: "hEmifa"
prop Label :: "EMIF Resource Manager"
prop JSName :: "HEMIFA"
prop NoGen :: 1
prop GlobalPropertyPage :: "{980E6534-6246-11d4-B5CC-0050DA2E2CC0}"
prop InstancePropertyPage :: "{980E6535-6246-11d4-B5CC-0050DA2E2CC0}"
prop GlobalIcon :: 163
prop InstanceIcon :: 164
prop GlobalHelpTopic :: (1045)
prop cGen :: 1
global EMIFA_INIT_ENABLE :: 0 {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "Enable Pre-Initialization"
prop JSName :: "emifaEnablePreInit"
prop Visible :: 1
prop Writable :: (CSL.EMIFA_SUPPORT)
prop NoGen :: 0
prop Set :: ($a = 0, scan ($b; emifaCfg) {$a = $a + 1}, if ($1 == 1 && $a == 1 && self.EMIFA_INIT == EMIFA_NOTHING) {" You must create a new configuration object"} else {self.EMIFA_INIT_ENABLE = $1, if ($1 == 0) {self.EMIFA_INIT = EMIFA_NOTHING} , "ok"})
}
global EMIFA_INIT :: EMIFA_NOTHING {
prop Type :: "{7BA2DA00-5A53-11d0-9BFE-0000C0AC14C7}"
prop MemberType :: emifaCfg
prop Label :: " Pre-Initialize with"
prop JSName :: "emifaPreInit"
prop Visible :: 1
prop Writable :: if (CSL.EMIFA_SUPPORT) && (self.EMIFA_INIT_ENABLE == 1) {1} else {0}
}
}
object EMIFA_NOTHING :: emifaCfg {
param iComment :: "<add comments here>"
param iIsUsed :: 0
param iId :: 0
param iDelUser :: "USER"
param iDelMsg :: "ok"
param NOHOLD_SETUP :: "Enable Hold"
param CLK4EN_SETUP :: "Enabled to clock"
param CLK6EN_SETUP :: "Enabled to clock"
param EK1EN_SETUP :: "Enabled to clock"
param EK2EN_SETUP :: "Enabled to clock"
param EK1HZ_SETUP :: "High-Z during hold"
param EK2HZ_SETUP :: "Clock during hold"
param EK2RATE_SETUP :: "1/4x EMIF input clock"
param BRMODE_SETUP :: "access/refresh pending or in progress"
param MTYPE0_SETUP :: "32-bit async. interf."
param RDSTRB0_SETUP :: 63
param RDSETUP0_SETUP :: 15
param RDHLD0_SETUP :: 3
param WRSTRB0_SETUP :: 63
param WRSETUP0_SETUP :: 15
param WRHLD0_SETUP :: 3
param TA0_SETUP :: 3
param MTYPE1_SETUP :: "32-bit async. interf."
param RDSTRB1_SETUP :: 63
param RDSETUP1_SETUP :: 15
param RDHLD1_SETUP :: 3
param WRSTRB1_SETUP :: 63
param WRSETUP1_SETUP :: 15
param WRHLD1_SETUP :: 3
param TA1_SETUP :: 3
param MTYPE2_SETUP :: "32-bit async. interf."
param RDSTRB2_SETUP :: 63
param RDSETUP2_SETUP :: 15
param RDHLD2_SETUP :: 3
param WRSTRB2_SETUP :: 63
param WRSETUP2_SETUP :: 15
param WRHLD2_SETUP :: 3
param TA2_SETUP :: 3
param MTYPE3_SETUP :: "32-bit async. interf."
param RDSTRB3_SETUP :: 63
param RDSETUP3_SETUP :: 15
param RDHLD3_SETUP :: 3
param WRSTRB3_SETUP :: 63
param WRSETUP3_SETUP :: 15
param WRHLD3_SETUP :: 3
param TA3_SETUP :: 3
param SYNCRL0_SETUP :: "2 cycles"
param SYNCWL0_SETUP :: "0 cycle"
param CEEXT0_SETUP :: "Inactive"
param RENEN0_SETUP :: "ADS Mode"
param SNCCLK0_SETUP :: "Sync. to ECLKOUT1"
param SYNCRL1_SETUP :: "2 cycles"
param SYNCWL1_SETUP :: "0 cycle"
param CEEXT1_SETUP :: "Inactive"
param RENEN1_SETUP :: "ADS Mode"
param SNCCLK1_SETUP :: "Sync. to ECLKOUT1"
param SYNCRL2_SETUP :: "2 cycles"
param SYNCWL2_SETUP :: "0 cycle"
param CEEXT2_SETUP :: "Inactive"
param RENEN2_SETUP :: "ADS Mode"
param SNCCLK2_SETUP :: "Sync. to ECLKOUT1"
param SYNCRL3_SETUP :: "2 cycles"
param SYNCWL3_SETUP :: "0 cycle"
param CEEXT3_SETUP :: "Inactive"
param RENEN3_SETUP :: "ADS Mode"
param SNCCLK3_SETUP :: "Sync. to ECLKOUT1"
param TRC_SETUP :: 15
param TRP_SETUP :: 8
param TRCD_SETUP :: 4
param INIT_SETUP :: "Initialize"
param RFEN_SETUP :: "Enable"
param SDCSZ_SETUP :: " 9 addresses"
param SDRSZ_SETUP :: "11 addresses"
param SDBSZ_SETUP :: "Two banks"
param SLFRFR_SETUP :: "Disable"
param PERIOD_SETUP2 :: 1500
param XRFR_SETUP :: 1
param TCL_SETUP :: 3
param TRAS_SETUP :: 8
param TRRD_SETUP :: 3
param TWR_SETUP :: 2
param THZP_SETUP :: 3
param RD2RD_SETUP :: 2
param RD2DEAC_SETUP :: 4
param RD2WR_SETUP :: 6
param R2WDQM_SETUP :: 3
param WR2WR_SETUP :: 2
param WR2DEAC_SETUP :: 2
param WR2RD_SETUP :: 2
param GBLCTL_VALUE :: 598140
param CECTL0_VALUE :: -221
param CECTL1_VALUE :: -221
param CECTL2_VALUE :: -221
param CECTL3_VALUE :: -221
param SDCTL_VALUE :: 55111680
param SDTIM_VALUE :: 6145500
param SDEXT_VALUE :: 1531711
param CESEC0_VALUE :: 2
param CESEC1_VALUE :: 2
param CESEC2_VALUE :: 2
param CESEC3_VALUE :: 2
}
type EMIFBFOLDER {
isa ModuleFolder
prop IsContainedIn :: CSL
prop name :: "EMIFB"
prop Label :: "EMIFB - External Memory Interface B (64x devices only)"
prop NoGen :: 1
prop GlobalPropertyPage :: "{980E6530-6246-11d4-B5CC-0050DA2E2CC0}"
prop InstancePropertyPage :: "{980E6531-6246-11d4-B5CC-0050DA2E2CC0}"
prop GlobalIcon :: 163
prop InstanceIcon :: 164
prop GlobalHelpTopic :: (1043)
global gUser :: "USER" {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gSetOf :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gNumOf :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gDirty :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gInitFlag :: 1 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gInit :: = ($a = 0, $b = 0, scan ($i; self) {if ($i.IsConfObj()) {$a += 1, if (self.isFinite) {$b |= 1 << $i.iId} } }, self.gNumOf = $a, self.gSetOf = $b, if (self.gInitFlag == 0) {self.localInit()} , self.gInitFlag = 1) {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
}
type emifbCfg {
isa ObjectMgr
prop Name :: "emifbCfg"
prop Label :: "EMIFB Configuration Manager"
prop JSName :: "EMIFB"
prop IsContainedIn :: EMIFBFOLDER
prop NoGen :: 1
prop maxObjs :: (32767)
prop GlobalPropertyPage :: "{980E6532-6246-11d4-B5CC-0050DA2E2CC0}"
prop InstancePropertyPage :: "{980E6533-6246-11d4-B5CC-0050DA2E2CC0}"
prop GlobalIcon :: 163
prop InstanceIcon :: 164
prop GlobalHelpTopic :: (1044)
prop InstanceHelpTopic :: (1044)
prop cGen :: CSL.EMIFB_SUPPORT
prop cStruct :: 1
prop cStructType :: "EMIFB_Config"
prop cHeaderName :: if self.gNumOf > 0 {"csl_emifb.h"} else {""}
prop cStructQual :: "far"
prop cStructName :: self
prop cConfigName :: "EMIFB_config"
prop localDelete :: (self.myDelete)
prop myDelete :: ($a = 0, scan ($b; emifbCfg) {$a = $a + 1}, if ($a == 2) {hEmifb.EMIFB_INIT_ENABLE = 0} , "ok")
prop NOHOLD_GBLCTL :: (if (self.NOHOLD_SETUP == "Disable Hold") {0x00000080} else {0x00000000})
prop CLK4EN_GBLCTL :: (if (self.CLK4EN_SETUP == "Held high") {0x00000000} else {0x00000010})
prop CLK6EN_GBLCTL :: (if (self.CLK6EN_SETUP == "Held high") {0x00000000} else {0x00000008})
prop EK1EN_GBLCTL :: (if (self.EK1EN_SETUP == "Held low") {0x00000000} else {0x00000020})
prop EK2EN_GBLCTL :: (if (self.EK2EN_SETUP == "Held low") {0x00000000} else {0x00010000})
prop EK1HZ_GBLCTL :: (if (self.EK1HZ_SETUP == "Clock during hold") {0x00000000} else {0x00000040})
prop EK2HZ_GBLCTL :: (if (self.EK2HZ_SETUP == "Clock during hold") {0x00000000} else {0x00020000})
prop EK2RATE_GBLCTL :: (if (self.EK2RATE_SETUP == "1x EMIF input clock") {0x00000000} else {if (self.EK2RATE_SETUP == "1/2x EMIF input clock") {0x00040000} else {if (self.EK2RATE_SETUP == "1/4x EMIF input clock") {0x00080000} }})
prop BRMODE_GBLCTL :: (if (self.BRMODE_SETUP == "access pending or in progress") {0x00000000} else {if (self.BRMODE_SETUP == "access/refresh pending or in progress") {0x00002000} })
prop MTYPE0_CECTL0 :: (if (self.MTYPE0_SETUP == " 8-bit async. interf.") {0x00000000} else {if (self.MTYPE0_SETUP == " 8-bit SDRAM") {0x00000080} else {if (self.MTYPE0_SETUP == " 8-bit prog. sync. mem") {0x000000a0} else {if (self.MTYPE0_SETUP == "16-bit async. interf.") {0x00000010} else {if (self.MTYPE0_SETUP == "16-bit SDRAM") {0x00000090} else {if (self.MTYPE0_SETUP == "16-bit prog. sync. mem") {0x000000b0} }}}}})
prop RDSTRB0_CECTL0 :: (((self.RDSTRB0_SETUP) << 8))
prop RDSETUP0_CECTL0 :: (((self.RDSETUP0_SETUP) << 16))
prop RDHLD0_CECTL0 :: ((self.RDHLD0_SETUP))
prop WRSTRB0_CECTL0 :: (((self.WRSTRB0_SETUP) << 22))
prop WRSETUP0_CECTL0 :: (((self.WRSETUP0_SETUP) << 28))
prop WRHLD0_CECTL0 :: (if (self.WRHLD0_SETUP > 3) {((self.WRHLD0_SETUP - 4) << 20)} else {((self.WRHLD0_SETUP << 20))})
prop WRHLDMSB0_CECTL0 :: (if (self.WRHLD0_SETUP > 3) {0x00000008} else {0x00000000})
prop TA0_CECTL0 :: ((self.TA0_SETUP << 14))
prop MTYPE1_CECTL1 :: (if (self.MTYPE1_SETUP == " 8-bit async. interf.") {0x00000000} else {if (self.MTYPE1_SETUP == " 8-bit SDRAM") {0x00000080} else {if (self.MTYPE1_SETUP == " 8-bit prog. sync. mem") {0x000000a0} else {if (self.MTYPE1_SETUP == "16-bit async. interf.") {0x00000010} else {if (self.MTYPE1_SETUP == "16-bit SDRAM") {0x00000090} else {if (self.MTYPE1_SETUP == "16-bit prog. sync. mem") {0x000000b0} }}}}})
prop RDSTRB1_CECTL1 :: (((self.RDSTRB1_SETUP) << 8))
prop RDSETUP1_CECTL1 :: (((self.RDSETUP1_SETUP) << 16))
prop RDHLD1_CECTL1 :: ((self.RDHLD1_SETUP))
prop WRSTRB1_CECTL1 :: (((self.WRSTRB1_SETUP) << 22))
prop WRSETUP1_CECTL1 :: (((self.WRSETUP1_SETUP) << 28))
prop WRHLD1_CECTL1 :: (if (self.WRHLD1_SETUP > 3) {((self.WRHLD1_SETUP - 4) << 20)} else {((self.WRHLD1_SETUP << 20))})
prop WRHLDMSB1_CECTL1 :: (if (self.WRHLD1_SETUP > 3) {0x00000008} else {0x00000000})
prop TA1_CECTL1 :: ((self.TA1_SETUP << 14))
prop MTYPE2_CECTL2 :: (if (self.MTYPE2_SETUP == " 8-bit async. interf.") {0x00000000} else {if (self.MTYPE2_SETUP == " 8-bit SDRAM") {0x00000080} else {if (self.MTYPE2_SETUP == " 8-bit prog. sync. mem") {0x000000a0} else {if (self.MTYPE2_SETUP == "16-bit async. interf.") {0x00000010} else {if (self.MTYPE2_SETUP == "16-bit SDRAM") {0x00000090} else {if (self.MTYPE2_SETUP == "16-bit prog. sync. mem") {0x000000b0} }}}}})
prop RDSTRB2_CECTL2 :: (((self.RDSTRB2_SETUP) << 8))
prop RDSETUP2_CECTL2 :: (((self.RDSETUP2_SETUP) << 16))
prop RDHLD2_CECTL2 :: ((self.RDHLD2_SETUP))
prop WRSTRB2_CECTL2 :: (((self.WRSTRB2_SETUP) << 22))
prop WRSETUP2_CECTL2 :: (((self.WRSETUP2_SETUP) << 28))
prop WRHLD2_CECTL2 :: (if (self.WRHLD2_SETUP > 3) {((self.WRHLD2_SETUP - 4) << 20)} else {((self.WRHLD2_SETUP << 20))})
prop WRHLDMSB2_CECTL2 :: (if (self.WRHLD2_SETUP > 3) {0x00000008} else {0x00000000})
prop TA2_CECTL2 :: ((self.TA2_SETUP << 14))
prop MTYPE3_CECTL3 :: (if (self.MTYPE3_SETUP == " 8-bit async. interf.") {0x00000000} else {if (self.MTYPE3_SETUP == " 8-bit SDRAM") {0x00000080} else {if (self.MTYPE3_SETUP == " 8-bit prog. sync. mem") {0x000000a0} else {if (self.MTYPE3_SETUP == "16-bit async. interf.") {0x00000010} else {if (self.MTYPE3_SETUP == "16-bit SDRAM") {0x00000090} else {if (self.MTYPE3_SETUP == "16-bit prog. sync. mem") {0x000000b0} }}}}})
prop RDSTRB3_CECTL3 :: (((self.RDSTRB3_SETUP) << 8))
prop RDSETUP3_CECTL3 :: (((self.RDSETUP3_SETUP) << 16))
prop RDHLD3_CECTL3 :: ((self.RDHLD3_SETUP))
prop WRSTRB3_CECTL3 :: (((self.WRSTRB3_SETUP) << 22))
prop WRSETUP3_CECTL3 :: (((self.WRSETUP3_SETUP) << 28))
prop WRHLD3_CECTL3 :: (if (self.WRHLD3_SETUP > 3) {((self.WRHLD3_SETUP - 4) << 20)} else {((self.WRHLD3_SETUP << 20))})
prop WRHLDMSB3_CECTL3 :: (if (self.WRHLD3_SETUP > 3) {0x00000008} else {0x00000000})
prop TA3_CECTL3 :: ((self.TA3_SETUP << 14))
prop SYNCRL0_CESEC0 :: (if (self.SYNCRL0_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCRL0_SETUP == "1 cycle") {0x00000001} else {if (self.SYNCRL0_SETUP == "2 cycles") {0x00000002} else {0x00000003}}})
prop SYNCWL0_CESEC0 :: (if (self.SYNCWL0_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCWL0_SETUP == "1 cycle") {0x00000004} else {if (self.SYNCWL0_SETUP == "2 cycles") {0x00000008} else {0x0000000c}}})
prop CEEXT0_CESEC0 :: (if (self.CEEXT0_SETUP == "Inactive") {0x00000000} else {0x0000010})
prop RENEN0_CESEC0 :: (if (self.RENEN0_SETUP == "ADS Mode") {0x00000000} else {0x0000020})
prop SNCCLK0_CESEC0 :: (if (self.SNCCLK0_SETUP == "Sync. to ECLKOUT1") {0x00000000} else {0x0000040})
prop SYNCRL1_CESEC1 :: (if (self.SYNCRL1_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCRL1_SETUP == "1 cycle") {0x00000001} else {if (self.SYNCRL1_SETUP == "2 cycles") {0x00000002} else {0x00000003}}})
prop SYNCWL1_CESEC1 :: (if (self.SYNCWL1_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCWL1_SETUP == "1 cycle") {0x00000004} else {if (self.SYNCWL1_SETUP == "2 cycles") {0x00000008} else {0x0000000c}}})
prop CEEXT1_CESEC1 :: (if (self.CEEXT1_SETUP == "Inactive") {0x00000000} else {0x0000010})
prop RENEN1_CESEC1 :: (if (self.RENEN1_SETUP == "ADS Mode") {0x00000000} else {0x0000020})
prop SNCCLK1_CESEC1 :: (if (self.SNCCLK1_SETUP == "Sync. to ECLKOUT1") {0x00000000} else {0x0000040})
prop SYNCRL2_CESEC2 :: (if (self.SYNCRL2_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCRL2_SETUP == "1 cycle") {0x00000001} else {if (self.SYNCRL2_SETUP == "2 cycles") {0x00000002} else {0x00000003}}})
prop SYNCWL2_CESEC2 :: (if (self.SYNCWL2_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCWL2_SETUP == "1 cycle") {0x00000004} else {if (self.SYNCWL2_SETUP == "2 cycles") {0x00000008} else {0x0000000c}}})
prop CEEXT2_CESEC2 :: (if (self.CEEXT2_SETUP == "Inactive") {0x00000000} else {0x0000010})
prop RENEN2_CESEC2 :: (if (self.RENEN2_SETUP == "ADS Mode") {0x00000000} else {0x0000020})
prop SNCCLK2_CESEC2 :: (if (self.SNCCLK2_SETUP == "Sync. to ECLKOUT1") {0x00000000} else {0x0000040})
prop SYNCRL3_CESEC3 :: (if (self.SYNCRL3_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCRL3_SETUP == "1 cycle") {0x00000001} else {if (self.SYNCRL3_SETUP == "2 cycles") {0x00000002} else {0x00000003}}})
prop SYNCWL3_CESEC3 :: (if (self.SYNCWL3_SETUP == "0 cycle") {0x00000000} else {if (self.SYNCWL3_SETUP == "1 cycle") {0x00000004} else {if (self.SYNCWL3_SETUP == "2 cycles") {0x00000008} else {0x0000000c}}})
prop CEEXT3_CESEC3 :: (if (self.CEEXT3_SETUP == "Inactive") {0x00000000} else {0x0000010})
prop RENEN3_CESEC3 :: (if (self.RENEN3_SETUP == "ADS Mode") {0x00000000} else {0x0000020})
prop SNCCLK3_CESEC3 :: (if (self.SNCCLK3_SETUP == "Sync. to ECLKOUT1") {0x00000000} else {0x0000040})
prop TRC_SDCTL :: ((self.TRC_SETUP << 12))
prop TRP_SDCTL :: ((self.TRP_SETUP << 16))
prop TRCD_SDCTL :: ((self.TRCD_SETUP << 20))
prop INIT_SDCTL :: (if (self.INIT_SETUP == "Initialize") {0x01000000} else {0x00000000})
prop RFEN_SDCTL :: (if (self.RFEN_SETUP == "Enable") {0x02000000} else {0x00000000})
prop SDCSZ_SDCTL :: (if (self.SDCSZ_SETUP == " 8 addresses") {0x04000000} else {if (self.SDCSZ_SETUP == "10 addresses") {0x08000000} else {0x00000000}})
prop SDRSZ_SDCTL :: (if (self.SDRSZ_SETUP == "12 addresses") {0x10000000} else {if (self.SDRSZ_SETUP == "13 addresses") {0x20000000} else {0x00000000}})
prop SDBSZ_SDCTL :: (if (self.SDBSZ_SETUP == "Four banks") {0x40000000} else {0x00000000})
prop PERIOD_SDTIM2 :: ((self.PERIOD_SETUP2))
prop XRFR_SDTIM :: (((self.XRFR_SETUP - 1) << 24))
prop TCL_SDEXT :: ((self.TCL_SETUP - 2))
prop TRAS_SDEXT :: (((self.TRAS_SETUP - 1) << 1))
prop TRRD_SDEXT :: ((self.TRRD_SETUP - 2) << 4)
prop TWR_SDEXT :: (((self.TWR_SETUP - 1) << 5))
prop THZP_SDEXT :: (((self.THZP_SETUP - 1) << 7))
prop RD2RD_SDEXT :: (((self.RD2RD_SETUP - 1) << 9))
prop RD2DEAC_SDEXT :: (((self.RD2DEAC_SETUP - 1) << 10))
prop RD2WR_SDEXT :: (((self.RD2WR_SETUP - 1) << 12))
prop R2WDQM_SDEXT :: (((self.R2WDQM_SETUP - 1) << 15))
prop WR2WR_SDEXT :: (((self.WR2WR_SETUP - 1) << 17))
prop WR2DEAC_SDEXT :: (((self.WR2DEAC_SETUP - 1) << 18))
prop WR2RD_SDEXT :: (((self.WR2RD_SETUP - 1) << 20))
prop GBLCTL_VALUE_update :: (0x00000004 | self.NOHOLD_GBLCTL() | self.CLK4EN_GBLCTL() | self.CLK6EN_GBLCTL() | self.EK1EN_GBLCTL() | self.EK2EN_GBLCTL() | self.EK1HZ_GBLCTL() | self.EK2HZ_GBLCTL() | self.EK2RATE_GBLCTL() | self.BRMODE_GBLCTL())
prop GBLCTL_SETUP_update :: (self.NOHOLD_SETUP = if ($1 & 0x00000080) {"Disable Hold"} else {"Enable Hold"}, self.CLK4EN_SETUP = if ($1 & 0x00000010) {"Enabled to clock"} else {"Held high"}, self.CLK6EN_SETUP = if ($1 & 0x00000008) {"Enabled to clock"} else {"Held high"}, self.EK1EN_SETUP = if ($1 & 0x00000020) {"Enabled to clock"} else {"Held low"}, self.EK2EN_SETUP = if ($1 & 0x00010000) {"Enabled to clock"} else {"Held low"}, self.EK1HZ_SETUP = if ($1 & 0x00000040) {"High-Z during hold"} else {"Clock during hold"}, self.EK2HZ_SETUP = if ($1 & 0x00020000) {"High-Z during hold"} else {"Clock during hold"}, self.BRMODE_SETUP = if ($1 & 0x00002000) {"access/refresh pending or in progress"} else {"access pending or in progress"}, $a = $1 & 0x000C0000, if ($a == 0x00080000) {self.EK2RATE_SETUP = "1/4x EMIF input clock"} else {self.EK2RATE_SETUP = if ($1 & 0x00040000) {"1/2x EMIF input clock"} else {"1x EMIF input clock"}})
prop CECTL0_VALUE_update :: (self.MTYPE0_CECTL0() | self.RDHLD0_CECTL0() | self.RDSTRB0_CECTL0() | self.RDSETUP0_CECTL0() | self.WRHLD0_CECTL0() | self.WRHLDMSB0_CECTL0() | self.WRSETUP0_CECTL0() | self.WRSTRB0_CECTL0() | self.TA0_CECTL0())
prop CECTL0_SETUP_update :: (self.MTYPE0_SETUP = ($a = ($1 & 0x000000f0), if ($a == 0x00000000) {" 8-bit async. interf."} else {if ($a == 0x00000010) {"16-bit async. interf."} else {if ($a == 0x00000080) {" 8-bit SDRAM"} else {if ($a == 0x00000090) {"16-bit SDRAM"} else {if ($a == 0x000000a0) {" 8-bit prog. sync. mem"} else {"16-bit prog. sync. mem"}}}}}), self.RDHLD0_SETUP = ($1 & 0x00000007), self.RDSTRB0_SETUP = (($1 & 0x00003F00) >> 8), self.RDSETUP0_SETUP = (($1 & 0x000F0000) >> 16), self.WRHLD0_SETUP = ((($1 & 0x00300000) >> 20) + (($1 & 0x00000008) >> 1)), self.WRSTRB0_SETUP = (($1 & 0x0FC00000) >> 22), self.WRSETUP0_SETUP = (($1 >> 28) & 0xF), self.TA0_SETUP = ($1 & 0x0000c000) >> 14)
prop CECTL1_VALUE_update :: (self.MTYPE1_CECTL1() | self.RDHLD1_CECTL1() | self.RDSTRB1_CECTL1() | self.RDSETUP1_CECTL1() | self.WRHLD1_CECTL1() | self.WRHLDMSB1_CECTL1() | self.WRSETUP1_CECTL1() | self.WRSTRB1_CECTL1() | self.TA1_CECTL1())
prop CECTL1_SETUP_update :: (self.MTYPE1_SETUP = ($a = ($1 & 0x000000f0), if ($a == 0x00000000) {" 8-bit async. interf."} else {if ($a == 0x00000010) {"16-bit async. interf."} else {if ($a == 0x00000080) {" 8-bit SDRAM"} else {if ($a == 0x00000090) {"16-bit SDRAM"} else {if ($a == 0x000000a0) {" 8-bit prog. sync. mem"} else {"16-bit prog. sync. mem"}}}}}), self.RDHLD1_SETUP = ($1 & 0x00000007), self.RDSTRB1_SETUP = (($1 & 0x00003F00) >> 8), self.RDSETUP1_SETUP = (($1 & 0x000F0000) >> 16), self.WRHLD1_SETUP = ((($1 & 0x00300000) >> 20) + (($1 & 0x00000008) >> 1)), self.WRSTRB1_SETUP = (($1 & 0x0FC00000) >> 22), self.WRSETUP1_SETUP = (($1 >> 28) & 0xF), self.TA1_SETUP = ($1 & 0x0000c000) >> 14)
prop CECTL2_VALUE_update :: (self.MTYPE2_CECTL2() | self.RDHLD2_CECTL2() | self.RDSTRB2_CECTL2() | self.RDSETUP2_CECTL2() | self.WRHLD2_CECTL2() | self.WRHLDMSB2_CECTL2() | self.WRSETUP2_CECTL2() | self.WRSTRB2_CECTL2() | self.TA2_CECTL2())
prop CECTL2_SETUP_update :: (self.MTYPE2_SETUP = ($a = ($1 & 0x000000f0), if ($a == 0x00000000) {" 8-bit async. interf."} else {if ($a == 0x00000010) {"16-bit async. interf."} else {if ($a == 0x00000080) {" 8-bit SDRAM"} else {if ($a == 0x00000090) {"16-bit SDRAM"} else {if ($a == 0x000000a0) {" 8-bit prog. sync. mem"} else {"16-bit prog. sync. mem"}}}}}), self.RDHLD2_SETUP = ($1 & 0x00000007), self.RDSTRB2_SETUP = (($1 & 0x00003F00) >> 8), self.RDSETUP2_SETUP = (($1 & 0x000F0000) >> 16), self.WRHLD2_SETUP = ((($1 & 0x00300000) >> 20) + (($1 & 0x00000008) >> 1)), self.WRSTRB2_SETUP = (($1 & 0x0FC00000) >> 22), self.WRSETUP2_SETUP = (($1 >> 28) & 0xF), self.TA2_SETUP = ($1 & 0x0000c000) >> 14)
prop CECTL3_VALUE_update :: (self.MTYPE3_CECTL3() | self.RDHLD3_CECTL3() | self.RDSTRB3_CECTL3() | self.RDSETUP3_CECTL3() | self.WRHLD3_CECTL3() | self.WRHLDMSB3_CECTL3() | self.WRSETUP3_CECTL3() | self.WRSTRB3_CECTL3() | self.TA3_CECTL3())
prop CECTL3_SETUP_update :: (self.MTYPE3_SETUP = ($a = ($1 & 0x000000f0), if ($a == 0x00000000) {" 8-bit async. interf."} else {if ($a == 0x00000010) {"16-bit async. interf."} else {if ($a == 0x00000080) {" 8-bit SDRAM"} else {if ($a == 0x00000090) {"16-bit SDRAM"} else {if ($a == 0x000000a0) {" 8-bit prog. sync. mem"} else {"16-bit prog. sync. mem"}}}}}), self.RDHLD3_SETUP = ($1 & 0x00000007), self.RDSTRB3_SETUP = (($1 & 0x00003F00) >> 8), self.RDSETUP3_SETUP = (($1 & 0x000F0000) >> 16), self.WRHLD3_SETUP = ((($1 & 0x00300000) >> 20) + (($1 & 0x00000008) >> 1)), self.WRSTRB3_SETUP = (($1 & 0x0FC00000) >> 22), self.WRSETUP3_SETUP = (($1 >> 28) & 0xF), self.TA3_SETUP = ($1 & 0x0000c000) >> 14)
prop SDCTL_VALUE_update :: (self.TRC_SDCTL() | self.TRP_SDCTL() | self.TRCD_SDCTL() | self.INIT_SDCTL() | self.RFEN_SDCTL() | self.SDCSZ_SDCTL() | self.SDRSZ_SDCTL() | self.SDBSZ_SDCTL())
prop SDCTL_SETUP_update :: (self.TRC_SETUP = ($1 & 0x0000F000) >> 12, self.TRP_SETUP = ($1 & 0x000F0000) >> 16, self.TRCD_SETUP = ($1 & 0x00F00000) >> 20, self.INIT_SETUP = ($a = ($1 & 0x01000000), if ($a == 0x01000000) {"Initialize"} else {"No effect"}), self.RFEN_SETUP = ($a = ($1 & 0x02000000), if ($a == 0x02000000) {"Enable"} else {"Disable"}), self.SDCSZ_SETUP = ($a = ($1 & 0x0c000000), if ($a == 0x04000000) {" 8 addresses"} else {if ($a == 0x08000000) {"10 addresses"} else {" 9 addresses"}}), self.SDRSZ_SETUP = ($a = ($1 & 0x30000000), if ($a == 0x10000000) {"12 addresses"} else {if ($a == 0x20000000) {"13 addresses"} else {"11 addresses"}}), self.SDBSZ_SETUP = ($a = ($1 & 0x40000000), if ($a == 0x40000000) {"Four banks"} else {"Two banks"}))
prop SDTIM_VALUE_update :: (self.PERIOD_SDTIM2() | self.XRFR_SDTIM() | 0x005dc000)
prop SDTIM_SETUP_update :: (self.PERIOD_SETUP2 = ($1 & 0x00000FFF), self.XRFR_SETUP = (($1 & 0x03000000) >> 24) + 1)
prop SDEXT_VALUE_update :: (self.TCL_SDEXT() | self.TRAS_SDEXT() | self.TRRD_SDEXT() | self.TWR_SDEXT() | self.THZP_SDEXT() | self.RD2RD_SDEXT() | self.RD2DEAC_SDEXT() | self.RD2WR_SDEXT() | self.R2WDQM_SDEXT() | self.WR2WR_SDEXT() | self.WR2DEAC_SDEXT() | self.WR2RD_SDEXT())
prop SDEXT_SETUP_update :: (self.TCL_SETUP = ($1 & 0x00000001) + 2, self.TRAS_SETUP = (($1 & 0x0000000E) >> 1) + 1, self.TRRD_SETUP = (($1 & 0x00000010) >> 4) + 2, self.TWR_SETUP = (($1 & 0x00000060) >> 5) + 1, self.THZP_SETUP = (($1 & 0x00000180) >> 7) + 1, self.RD2RD_SETUP = (($1 & 0x00000200) >> 9) + 1, self.RD2DEAC_SETUP = (($1 & 0x00000c00) >> 10) + 1, self.RD2WR_SETUP = (($1 & 0x00007000) >> 12) + 1, self.R2WDQM_SETUP = (($1 & 0x00018000) >> 15) + 1, self.WR2WR_SETUP = (($1 & 0x00020000) >> 17) + 1, self.WR2DEAC_SETUP = (($1 & 0x000c0000) >> 18) + 1, self.WR2RD_SETUP = (($1 & 0x00100000) >> 20) + 1)
prop CESEC0_VALUE_update :: (self.SYNCRL0_CESEC0() | self.SYNCWL0_CESEC0() | self.CEEXT0_CESEC0() | self.RENEN0_CESEC0() | self.SNCCLK0_CESEC0())
prop CESEC0_SETUP_update :: (self.SYNCRL0_SETUP = ($a = ($1 & 0x00000003), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000001) {"1 cycle"} else {if ($a == 0x00000002) {"2 cycles"} else {"3 cycles"}}}), self.SYNCWL0_SETUP = ($a = ($1 & 0x0000000C), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000004) {"1 cycle"} else {if ($a == 0x00000008) {"2 cycles"} else {"3 cycles"}}}), self.CEEXT0_SETUP = ($a = ($1 & 0x00000010), if ($a == 0x00000000) {"Inactive"} else {"Active"}), self.RENEN0_SETUP = ($a = ($1 & 0x00000020), if ($a == 0x00000000) {"ADS Mode"} else {"Read Enable Mode"}), self.SNCCLK0_SETUP = ($a = ($1 & 0x00000040), if ($a == 0x00000000) {"Sync. to ECLKOUT1"} else {"Sync. to ECLKOUT2"}))
prop CESEC1_VALUE_update :: (self.SYNCRL1_CESEC1() | self.SYNCWL1_CESEC1() | self.CEEXT1_CESEC1() | self.RENEN1_CESEC1() | self.SNCCLK1_CESEC1())
prop CESEC1_SETUP_update :: (self.SYNCRL1_SETUP = ($a = ($1 & 0x00000003), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000001) {"1 cycle"} else {if ($a == 0x00000002) {"2 cycles"} else {"3 cycles"}}}), self.SYNCWL1_SETUP = ($a = ($1 & 0x0000000C), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000004) {"1 cycle"} else {if ($a == 0x00000008) {"2 cycles"} else {"3 cycles"}}}), self.CEEXT1_SETUP = ($a = ($1 & 0x00000010), if ($a == 0x00000000) {"Inactive"} else {"Active"}), self.RENEN1_SETUP = ($a = ($1 & 0x00000020), if ($a == 0x00000000) {"ADS Mode"} else {"Read Enable Mode"}), self.SNCCLK1_SETUP = ($a = ($1 & 0x00000040), if ($a == 0x00000000) {"Sync. to ECLKOUT1"} else {"Sync. to ECLKOUT2"}))
prop CESEC2_VALUE_update :: (self.SYNCRL2_CESEC2() | self.SYNCWL2_CESEC2() | self.CEEXT2_CESEC2() | self.RENEN2_CESEC2() | self.SNCCLK2_CESEC2())
prop CESEC2_SETUP_update :: (self.SYNCRL2_SETUP = ($a = ($1 & 0x00000003), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000001) {"1 cycle"} else {if ($a == 0x00000002) {"2 cycles"} else {"3 cycles"}}}), self.SYNCWL2_SETUP = ($a = ($1 & 0x0000000C), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000004) {"1 cycle"} else {if ($a == 0x00000008) {"2 cycles"} else {"3 cycles"}}}), self.CEEXT2_SETUP = ($a = ($1 & 0x00000010), if ($a == 0x00000000) {"Inactive"} else {"Active"}), self.RENEN2_SETUP = ($a = ($1 & 0x00000020), if ($a == 0x00000000) {"ADS Mode"} else {"Read Enable Mode"}), self.SNCCLK2_SETUP = ($a = ($1 & 0x00000040), if ($a == 0x00000000) {"Sync. to ECLKOUT1"} else {"Sync. to ECLKOUT2"}))
prop CESEC3_VALUE_update :: (self.SYNCRL3_CESEC3() | self.SYNCWL3_CESEC3() | self.CEEXT3_CESEC3() | self.RENEN3_CESEC3() | self.SNCCLK3_CESEC3())
prop CESEC3_SETUP_update :: (self.SYNCRL3_SETUP = ($a = ($1 & 0x00000003), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000001) {"1 cycle"} else {if ($a == 0x00000002) {"2 cycles"} else {"3 cycles"}}}), self.SYNCWL3_SETUP = ($a = ($1 & 0x0000000C), if ($a == 0x00000000) {"0 cycle"} else {if ($a == 0x00000004) {"1 cycle"} else {if ($a == 0x00000008) {"2 cycles"} else {"3 cycles"}}}), self.CEEXT3_SETUP = ($a = ($1 & 0x00000010), if ($a == 0x00000000) {"Inactive"} else {"Active"}), self.RENEN3_SETUP = ($a = ($1 & 0x00000020), if ($a == 0x00000000) {"ADS Mode"} else {"Read Enable Mode"}), self.SNCCLK3_SETUP = ($a = ($1 & 0x00000040), if ($a == 0x00000000) {"Sync. to ECLKOUT1"} else {"Sync. to ECLKOUT2"}))
global gUser :: "USER" {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gSetOf :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gNumOf :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gDirty :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gInitFlag :: 1 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
global gInit :: = ($a = 0, $b = 0, scan ($i; self) {if ($i.IsConfObj()) {$a += 1, if (self.isFinite) {$b |= 1 << $i.iId} } }, self.gNumOf = $a, self.gSetOf = $b, if (self.gInitFlag == 0) {self.localInit()} , self.gInitFlag = 1) {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
inst iComment :: if self.iDelUser == "USER" {"<add comments here>"} else {self.iDelMsg} {
prop Type :: "{21455EA3-B96A-11cf-9BFE-0000C0AC14C7}"
prop Label :: "comment"
prop JSName :: "comment"
prop Visible :: 1
prop Writable :: if self.iDelUser == "USER" {1} else {0}
prop NoGen :: 1
}
inst iIsUsed :: 0 {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
inst iId :: 0 {
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01
prop Visible :: 0
prop Writable :: 1
prop NoGen :: 1
}
inst iDelUser :: "USER" {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
inst iDelMsg :: "ok" {
prop Visible :: 0
prop Writable :: 0
prop NoGen :: 1
}
inst cConfigGen :: = ((hEmifb.EMIFB_INIT_ENABLE == 1) && (hEmifb.EMIFB_INIT == self) && (hEmifb.EMIFB_INIT != EMIFB_NOTHING)) {
prop Type :: "{21455EA0-B96A-11cf-9BFE-0000C0AC14C7}"
prop NoGen :: 1
prop Visible :: 0
}
inst cConfigArg0 :: = hEmifb.EMIFB_INIT {
prop Type :: "{21455EA3-B96A-11cf-9BFE-0000C0AC14C7}"
prop MemberType :: emifbCfg
prop Label :: "Pre-initialize Config"
prop Visible :: 0
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 0
prop cPreVal :: "&"
}
inst NOHOLD_SETUP :: "Enable Hold" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Enable Hold,Disable Hold"
prop Label :: "External HOLD disable (NOHOLD)"
prop JSName :: "emifbGblctlNoHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.NOHOLD_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst CLK4EN_SETUP :: "Enabled to clock" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Held high,Enabled to clock"
prop Label :: "CLKOUT4 Enable (CLK4EN)"
prop JSName :: "emifbGblctlClk4en"
prop Visible :: 1
prop Writable :: if (CSL.EMIFB_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.CLK4EN_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst CLK6EN_SETUP :: "Enabled to clock" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Held high,Enabled to clock"
prop Label :: "CLKOUT6 Enable (CLK6EN)"
prop JSName :: "emifbGblctlClk6en"
prop Visible :: 1
prop Writable :: if (CSL.EMIFB_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.CLK6EN_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst EK1EN_SETUP :: "Enabled to clock" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Held low,Enabled to clock"
prop Label :: "ECLKOUT1 Enable (EK1EN)"
prop JSName :: "emifbGblctlEk1en"
prop Visible :: 1
prop Writable :: if (CSL.EMIFB_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.EK1EN_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst EK2EN_SETUP :: "Enabled to clock" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Held low,Enabled to clock"
prop Label :: "ECLKOUT2 Enable (EK2EN)"
prop JSName :: "emifbGblctlEk2en"
prop Visible :: 1
prop Writable :: if (CSL.EMIFB_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.EK2EN_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst EK1HZ_SETUP :: "High-Z during hold" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Clock during hold,High-Z during hold"
prop Label :: "ECLKOUT1 High-Z Control (EK1HZ)"
prop JSName :: "emifbGblctlEk1hz"
prop Visible :: 1
prop Writable :: if (CSL.EMIFB_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.EK1HZ_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst EK2HZ_SETUP :: "Clock during hold" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "Clock during hold,High-Z during hold"
prop Label :: "ECLKOUT2 High-Z Control (EK2HZ)"
prop JSName :: "emifbGblctlEk2hz"
prop Visible :: 1
prop Writable :: if (CSL.EMIFB_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.EK2HZ_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst EK2RATE_SETUP :: "1/4x EMIF input clock" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "1x EMIF input clock,1/2x EMIF input clock,1/4x EMIF input clock"
prop Label :: "ECLKOUT2 Rate (EK2RATE)"
prop JSName :: "emifbGblctlEk2rate"
prop Visible :: 1
prop Writable :: if (CSL.EMIFB_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.EK2RATE_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst BRMODE_SETUP :: "access/refresh pending or in progress" {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: "access/refresh pending or in progress,access pending or in progress"
prop Label :: "Bus Request Mode"
prop JSName :: "emifbGblctlBrmode"
prop Visible :: 1
prop Writable :: if (CSL.EMIFB_SUPPORT != 0) {1} else {0}
prop NoGen :: 1
prop TabName :: "Global Control"
prop Set :: (self.BRMODE_SETUP = $1, self.GBLCTL_VALUE = self.GBLCTL_VALUE_update(), "ok")
}
inst MTYPE0_SETUP :: " 8-bit async. interf." {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 8-bit async. interf.,16-bit async. interf., 8-bit SDRAM,16-bit SDRAM, 8-bit prog. sync. mem,16-bit prog. sync. mem"
prop Label :: "Memory Type (MTYPE)"
prop JSName :: "emifbCectl0Mtype"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (self.MTYPE0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok")
}
inst RDSTRB0_SETUP :: 63 {
prop Label :: "Read Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl0ReadStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.RDSTRB0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst RDSETUP0_SETUP :: 15 {
prop Label :: "Read Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl0ReadSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.RDSETUP0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst RDHLD0_SETUP :: 3 {
prop Label :: "Read Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl0ReadHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycless")} else {self.RDHLD0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"}} else {if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.RDHLD0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"}})
}
inst WRSTRB0_SETUP :: 63 {
prop Label :: "Write Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl0WriteStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.WRSTRB0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst WRSETUP0_SETUP :: 15 {
prop Label :: "Write Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl0WriteSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.WRSETUP0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst WRHLD0_SETUP :: 3 {
prop Label :: "Write Hold Width (WRHLD-WRHLDMSB) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl0WriteHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.WRHLD0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst TA0_SETUP :: 3 {
prop Label :: "Turn around time (TA) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl0Ta"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE0 Space"
prop Set :: (if ($1 < 1 || $1 > 3) {self.error(" Minimum: 1 ECLKOU1 cycle - Maximum : 3 ECLKOU1 cycles")} else {self.TA0_SETUP = $1, self.CECTL0_VALUE = self.CECTL0_VALUE_update(), "ok"})
}
inst MTYPE1_SETUP :: " 8-bit async. interf." {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 8-bit async. interf.,16-bit async. interf., 8-bit SDRAM,16-bit SDRAM, 8-bit prog. sync. mem,16-bit prog. sync. mem"
prop Label :: "Memory Type (MTYPE)"
prop JSName :: "emifbCectl1Mtype"
prop Visible :: 1
prop Writable :: (if (CSL.EMIFB_SUPPORT) {1} else {0})
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (self.MTYPE1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok")
}
inst RDSTRB1_SETUP :: 63 {
prop Label :: "Read Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl1ReadStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.RDSTRB1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst RDSETUP1_SETUP :: 15 {
prop Label :: "Read Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl1ReadSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.RDSETUP1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst RDHLD1_SETUP :: 3 {
prop Label :: "Read Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl1ReadHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycless")} else {self.RDHLD1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"}} else {if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.RDHLD1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"}})
}
inst WRSTRB1_SETUP :: 63 {
prop Label :: "Write Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl1WriteStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.WRSTRB1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst WRSETUP1_SETUP :: 15 {
prop Label :: "Write Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl1WriteSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.WRSETUP1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst WRHLD1_SETUP :: 3 {
prop Label :: "Write Hold Width (WRHLD - WHLDMSB) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl1WriteHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.WRHLD1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst TA1_SETUP :: 3 {
prop Label :: "Turn around time (TA) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl1Ta"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE1 Space"
prop Set :: (if ($1 < 1 || $1 > 3) {self.error(" Minimum: 1 ECLKOU1 cycle - Maximum : 3 ECLKOU1 cycles")} else {self.TA1_SETUP = $1, self.CECTL1_VALUE = self.CECTL1_VALUE_update(), "ok"})
}
inst MTYPE2_SETUP :: " 8-bit async. interf." {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 8-bit async. interf.,16-bit async. interf., 8-bit SDRAM,16-bit SDRAM, 8-bit prog. sync. mem,16-bit prog. sync. mem"
prop Label :: "Memory Type (MTYPE)"
prop JSName :: "emifbCectl2Mtype"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (self.MTYPE2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok")
}
inst RDSTRB2_SETUP :: 63 {
prop Label :: "Read Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl2ReadStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.RDSTRB2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst RDSETUP2_SETUP :: 15 {
prop Label :: "Read Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl2ReadSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.RDSETUP2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst RDHLD2_SETUP :: 3 {
prop Label :: "Read Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl2ReadHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycless")} else {self.RDHLD2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"}} else {if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.RDHLD2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"}})
}
inst WRSTRB2_SETUP :: 63 {
prop Label :: "Write Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl2WriteStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.WRSTRB2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst WRSETUP2_SETUP :: 15 {
prop Label :: "Write Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl2WriteSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.WRSETUP2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst WRHLD2_SETUP :: 3 {
prop Label :: "Write Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl2WriteHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.WRHLD2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst TA2_SETUP :: 3 {
prop Label :: "Turn around time (TA) "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl2Ta"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE2 Space"
prop Set :: (if ($1 < 1 || $1 > 3) {self.error(" Minimum: 1 ECLKOU1 cycle - Maximum : 3 ECLKOU1 cycles")} else {self.TA2_SETUP = $1, self.CECTL2_VALUE = self.CECTL2_VALUE_update(), "ok"})
}
inst MTYPE3_SETUP :: " 8-bit async. interf." {
prop Type :: "{21455EA1-B96A-11cf-9BFE-0000C0AC14C7}"
prop Enum :: " 8-bit async. interf.,16-bit async. interf., 8-bit SDRAM,16-bit SDRAM, 8-bit prog. sync. mem,16-bit prog. sync. mem"
prop Label :: "Memory Type (MTYPE)"
prop JSName :: "emifbCectl3Mtype"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (self.MTYPE3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok")
}
inst RDSTRB3_SETUP :: 63 {
prop Label :: "Read Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl3ReadStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.RDSTRB3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst RDSETUP3_SETUP :: 15 {
prop Label :: "Read Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl3ReadSetup"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 15) {self.error(" Minimum setup :0 cycle - Maximum setup: 15 cycles")} else {self.RDSETUP3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst RDHLD3_SETUP :: 3 {
prop Label :: "Read Hold Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl3ReadHold"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ((!CSL.C11_SUPPORT)) {if ($1 < 0 || $1 > 3) {self.error(" Minimum hold :0 cycle - Maximum hold: 3 cycless")} else {self.RDHLD3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"}} else {if ($1 < 0 || $1 > 7) {self.error(" Minimum hold :0 cycle - Maximum hold: 7 cycles")} else {self.RDHLD3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"}})
}
inst WRSTRB3_SETUP :: 63 {
prop Label :: "Write Strobe Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl3WriteStrobe"
prop Visible :: 1
prop Writable :: (CSL.EMIFB_SUPPORT)
prop NoGen :: 1
prop TabName :: "CE3 Space"
prop Set :: (if ($1 < 0 || $1 > 63) {self.error(" Minimum strobe :0 cycle - Maximum strobe: 63 cycless")} else {self.WRSTRB3_SETUP = $1, self.CECTL3_VALUE = self.CECTL3_VALUE_update(), "ok"})
}
inst WRSETUP3_SETUP :: 15 {
prop Label :: "Write Setup Width "
prop Type :: "{21455EA2-B96A-11cf-9BFE-0000C0AC14C7}"
prop Style :: 0x01 | 0x02
prop JSName :: "emifbCectl3WriteSetup"
prop Visible :: 1