开通博客赚积分
发布资源赚积分
分类

源码开发语言/平台
当前位置：首页 > 源码/资料 > 嵌入式/单片机编程 > uCOS > 查看源码
cpu.h
资源名称：STM32-uCOS-II_UAV.rar　[点击查看]
上传用户：yj_qqy
上传日期：2017-01-28
资源大小：2911k
文件大小：31k
源码类别：

uCOS

开发平台：

C/C++

cpu.h：源码内容
  1. /*
  2. *********************************************************************************************************
  3. *                                               uC/CPU
  4. *                                    CPU CONFIGURATION & PORT LAYER
  5. *
  6. *                          (c) Copyright 2004-2008; Micrium, Inc.; Weston, FL
  7. *
  8. *               All rights reserved.  Protected by international copyright laws.
  9. *
  10. *               uC/CPU is provided in source form for FREE evaluation, for educational
  11. *               use or peaceful research.  If you plan on using uC/CPU in a commercial
  12. *               product you need to contact Micrium to properly license its use in your
  13. *               product.  We provide ALL the source code for your convenience and to
  14. *               help you experience uC/CPU.  The fact that the source code is provided
  15. *               does NOT mean that you can use it without paying a licensing fee.
  16. *
  17. *               Knowledge of the source code may NOT be used to develop a similar product.
  18. *
  19. *               Please help us continue to provide the Embedded community with the finest
  20. *               software available.  Your honesty is greatly appreciated.
  21. *********************************************************************************************************
  22. */
  24. /*
  25. *********************************************************************************************************
  26. *
  27. *                                            CPU PORT FILE
  28. *
  29. *                                            ARM-Cortex-M3
  30. *                                      RealView Development Suite
  31. *                            RealView Microcontroller Development Kit (MDK)
  32. *                                       ARM Developer Suite (ADS)
  33. *                                            Keil uVision
  34. *
  35. * Filename      : cpu.h
  36. * Version       : V1.19
  37. * Programmer(s) : JJL
  38. *                 BAN
  39. *********************************************************************************************************
  40. */
  43. /*
  44. *********************************************************************************************************
  45. *                                               MODULE
  46. *********************************************************************************************************
  47. */
  49. #ifndef  CPU_CFG_MODULE_PRESENT
  50. #define  CPU_CFG_MODULE_PRESENT
  53. /*
  54. *********************************************************************************************************
  55. *                                          CPU INCLUDE FILES
  56. *
  57. * Note(s) : (1) The following CPU files are located in the following directories :
  58. *
  59. *               (a) <CPU-Compiler Directory>cpu_def.h
  60. *
  61. *               (b) <CPU-Compiler Directory><cpu><compiler>cpu*.*
  62. *
  63. *                       where
  64. *                               <CPU-Compiler Directory>    directory path for common   CPU-compiler software
  65. *                               <cpu>                       directory name for specific CPU
  66. *                               <compiler>                  directory name for specific compiler
  67. *
  68. *           (2) Compiler MUST be configured to include the '<CPU-Compiler Directory>' directory & the
  69. *               specific CPU-compiler directory as additional include path directories.
  70. *********************************************************************************************************
  71. */
  73. #include  <cpu_def.h>
  76. /*$PAGE*/
  77. /*
  78. *********************************************************************************************************
  79. *                                    CONFIGURE STANDARD DATA TYPES
  80. *
  81. * Note(s) : (1) Configure standard data types according to CPU-/compiler-specifications.
  82. *
  83. *           (2) (a) (1) 'CPU_FNCT_VOID' data type defined to replace the commonly-used function pointer
  84. *                       data type of a pointer to a function which returns void & has no arguments.
  85. *
  86. *                   (2) Example function pointer usage :
  87. *
  88. *                           CPU_FNCT_VOID  FnctName;
  89. *
  90. *                           FnctName();
  91. *
  92. *               (b) (1) 'CPU_FNCT_PTR'  data type defined to replace the commonly-used function pointer
  93. *                       data type of a pointer to a function which returns void & has a single void
  94. *                       pointer argument.
  95. *
  96. *                   (2) Example function pointer usage :
  97. *
  98. *                           CPU_FNCT_PTR   FnctName;
  99. *                           void          *pobj
  100. *
  101. *                           FnctName(pobj);
  102. *********************************************************************************************************
  103. */
  105. typedef            void       CPU_VOID;
  106. typedef  unsigned  char       CPU_CHAR;                         /*  8-bit character                                     */
  107. typedef  unsigned  char       CPU_BOOLEAN;                      /*  8-bit boolean or logical                            */
  108. typedef  unsigned  char       CPU_INT08U;                       /*  8-bit unsigned integer                              */
  109. typedef    signed  char       CPU_INT08S;                       /*  8-bit   signed integer                              */
  110. typedef  unsigned  short      CPU_INT16U;                       /* 16-bit unsigned integer                              */
  111. typedef    signed  short      CPU_INT16S;                       /* 16-bit   signed integer                              */
  112. typedef  unsigned  int        CPU_INT32U;                       /* 32-bit unsigned integer                              */
  113. typedef    signed  int        CPU_INT32S;                       /* 32-bit   signed integer                              */
  114. typedef  unsigned  long long  CPU_INT64U;                       /* 64-bit unsigned integer                              */
  115. typedef    signed  long long  CPU_INT64S;                       /* 64-bit   signed integer                              */
  117. typedef            float      CPU_FP32;                         /* 32-bit floating point                                */
  118. typedef            double     CPU_FP64;                         /* 64-bit floating point                                */
  121. typedef            void     (*CPU_FNCT_VOID)(void);             /* See Note #2a.                                        */
  122. typedef            void     (*CPU_FNCT_PTR )(void *);           /* See Note #2b.                                        */
  125. /*$PAGE*/
  126. /*
  127. *********************************************************************************************************
  128. *                                       CPU WORD CONFIGURATION
  129. *
  130. * Note(s) : (1) Configure CPU_CFG_ADDR_SIZE & CPU_CFG_DATA_SIZE with CPU's word sizes :
  131. *
  132. *                   CPU_WORD_SIZE_08             8-bit word size
  133. *                   CPU_WORD_SIZE_16            16-bit word size
  134. *                   CPU_WORD_SIZE_32            32-bit word size
  135. *                   CPU_WORD_SIZE_64            64-bit word size            See Note #1a
  136. *
  137. *               (a) 64-bit word size NOT currently supported.
  138. *
  139. *           (2) Configure CPU_CFG_ENDIAN_TYPE with CPU's data-word-memory order :
  140. *
  141. *                   CPU_ENDIAN_TYPE_BIG         Big-   endian word order (CPU words' most  significant
  142. *                                                                         octet @ lowest memory address)
  143. *                   CPU_ENDIAN_TYPE_LITTLE      Little-endian word order (CPU words' least significant
  144. *                                                                         octet @ lowest memory address)
  145. *********************************************************************************************************
  146. */
  148.                                                                 /* Define  CPU         word sizes (see Note #1) :       */
  149. #define  CPU_CFG_ADDR_SIZE              CPU_WORD_SIZE_32        /* Defines CPU address word size.                       */
  151. #define  CPU_CFG_DATA_SIZE              CPU_WORD_SIZE_32        /* Defines CPU data    word size.                       */
  152. #define  CPU_CFG_ENDIAN_TYPE            CPU_ENDIAN_TYPE_LITTLE  /* Defines CPU data    word-memory order.               */
  155. /*
  156. *********************************************************************************************************
  157. *                                 CONFIGURE CPU ADDRESS & DATA TYPES
  158. *********************************************************************************************************
  159. */
  161.                                                                 /* CPU address type based on address bus size.          */
  162. #if     (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_32)
  163. typedef  CPU_INT32U  CPU_ADDR;
  164. #elif   (CPU_CFG_ADDR_SIZE == CPU_WORD_SIZE_16)
  165. typedef  CPU_INT16U  CPU_ADDR;
  166. #else
  167. typedef  CPU_INT08U  CPU_ADDR;
  168. #endif
  170.                                                                 /* CPU data    type based on data    bus size.          */
  171. #if     (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_32)
  172. typedef  CPU_INT32U  CPU_DATA;
  173. #elif   (CPU_CFG_DATA_SIZE == CPU_WORD_SIZE_16)
  174. typedef  CPU_INT16U  CPU_DATA;
  175. #else
  176. typedef  CPU_INT08U  CPU_DATA;
  177. #endif
  180. typedef  CPU_DATA    CPU_ALIGN;                                 /* Defines CPU data-word-alignment size.                */
  181. typedef  CPU_DATA    CPU_SIZE_T;                                /* Defines CPU standard 'size_t'   size.                */
  184. /*$PAGE*/
  185. /*
  186. *********************************************************************************************************
  187. *                                   CRITICAL SECTION CONFIGURATION
  188. *
  189. * Note(s) : (1) Configure CPU_CFG_CRITICAL_METHOD with CPU's/compiler's critical section method :
  190. *
  191. *                                                       Enter/Exit critical sections by ...
  192. *
  193. *                   CPU_CRITICAL_METHOD_INT_DIS_EN      Disable/Enable interrupts
  194. *                   CPU_CRITICAL_METHOD_STATUS_STK      Push/Pop       interrupt status onto stack
  195. *                   CPU_CRITICAL_METHOD_STATUS_LOCAL    Save/Restore   interrupt status to local variable
  196. *
  197. *               (a) CPU_CRITICAL_METHOD_INT_DIS_EN  is NOT a preferred method since it does NOT support
  198. *                   multiple levels of interrupts.  However, with some CPUs/compilers, this is the only
  199. *                   available method.
  200. *
  201. *               (b) CPU_CRITICAL_METHOD_STATUS_STK    is one preferred method since it DOES support multiple
  202. *                   levels of interrupts.  However, this method assumes that the compiler allows in-line
  203. *                   assembly AND will correctly modify the local stack pointer when interrupt status is
  204. *                   pushed/popped onto the stack.
  205. *
  206. *               (c) CPU_CRITICAL_METHOD_STATUS_LOCAL  is one preferred method since it DOES support multiple
  207. *                   levels of interrupts.  However, this method assumes that the compiler provides C-level
  208. *                   &/or assembly-level functionality for the following :
  209. *
  210. *                     ENTER CRITICAL SECTION :
  211. *                       (a) Save    interrupt status into a local variable
  212. *                       (b) Disable interrupts
  213. *
  214. *                     EXIT  CRITICAL SECTION :
  215. *                       (c) Restore interrupt status from a local variable
  216. *
  217. *           (2) Critical section macro's most likely require inline assembly.  If the compiler does NOT
  218. *               allow inline assembly in C source files, critical section macro's MUST call an assembly
  219. *               subroutine defined in a 'cpu_a.asm' file located in the following software directory :
  220. *
  221. *                   <CPU-Compiler Directory><cpu><compiler>
  222. *
  223. *                       where
  224. *                               <CPU-Compiler Directory>    directory path for common   CPU-compiler software
  225. *                               <cpu>                       directory name for specific CPU
  226. *                               <compiler>                  directory name for specific compiler
  227. *
  228. *           (3) To save/restore interrupt status, a local variable 'cpu_sr' of type 'CPU_SR' MAY need to
  229. *               be declared (e.g. if 'CPU_CRITICAL_METHOD_STATUS_LOCAL' method is configured).  Configure
  230. *               'CPU_SR' data type with the appropriate-sized CPU data type large enough to completely
  231. *               store the CPU's/compiler's status word.
  232. *********************************************************************************************************
  233. */
  235. typedef  CPU_INT32U  CPU_SR;                                    /* Defines   CPU status register size (see Note #3).    */
  237.                                                                 /* Configure CPU critical method      (see Note #1) :   */
  238. #define  CPU_CFG_CRITICAL_METHOD        CPU_CRITICAL_METHOD_STATUS_LOCAL
  240. #define  CPU_CRITICAL_ENTER()           { cpu_sr = CPU_SR_Save(); }
  241. #define  CPU_CRITICAL_EXIT()            { CPU_SR_Restore(cpu_sr); }
  244. /*
  245. *********************************************************************************************************
  246. *                                         FUNCTION PROTOTYPES
  247. *********************************************************************************************************
  248. */
  250. void        CPU_IntDis       (void);
  251. void        CPU_IntEn        (void);
  253. void        CPU_IntSrcDis    (CPU_INT08U  pos);
  254. void        CPU_IntSrcEn     (CPU_INT08U  pos);
  255. CPU_INT16S  CPU_IntSrcPrioGet(CPU_INT08U  pos);
  256. void        CPU_IntSrcPrioSet(CPU_INT08U  pos,
  257.                               CPU_INT08U  prio);
  259. CPU_SR      CPU_SR_Save      (void);
  260. void        CPU_SR_Restore   (CPU_SR      cpu_sr);
  262. CPU_INT32U  CPU_CntLeadZeros (CPU_INT32U  val);
  263. CPU_INT32U  CPU_RevBits      (CPU_INT32U  val);
  265. void        CPU_WaitForInt   (void);
  266. void        CPU_WaitForExcept(void);
  268. void        CPU_BitBandClr   (CPU_ADDR    addr,
  269.                               CPU_INT08U  bit_nbr);
  270. void        CPU_BitBandSet   (CPU_ADDR    addr,
  271.                               CPU_INT08U  bit_nbr);
  273. /*
  274. *********************************************************************************************************
  275. *                                           INTERRUPT SOURCES
  276. *********************************************************************************************************
  277. */
  279. #define  CPU_INT_STK_PTR                                   0
  280. #define  CPU_INT_RESET                                     1
  281. #define  CPU_INT_NMI                                       2
  282. #define  CPU_INT_HFAULT                                    3
  283. #define  CPU_INT_MEM                                       4
  284. #define  CPU_INT_BUSFAULT                                  5
  285. #define  CPU_INT_USAGEFAULT                                6
  286. #define  CPU_INT_RSVD_07                                   7
  287. #define  CPU_INT_RSVD_08                                   8
  288. #define  CPU_INT_RSVD_09                                   9
  289. #define  CPU_INT_RSVD_10                                  10
  290. #define  CPU_INT_SVCALL                                   11
  291. #define  CPU_INT_DBGMON                                   12
  292. #define  CPU_INT_RSVD_13                                  13
  293. #define  CPU_INT_PENDSV                                   14
  294. #define  CPU_INT_SYSTICK                                  15
  297. /*
  298. *********************************************************************************************************
  299. *                                             CPU REGISTERS
  300. *********************************************************************************************************
  301. */
  303. #define  CPU_REG_NVIC_NVIC              (*((volatile CPU_INT32U *)(0xE000E004))) /* Int Ctrl'er Type Reg.               */
  304. #define  CPU_REG_NVIC_ST_CTRL           (*((volatile CPU_INT32U *)(0xE000E010))) /* SysTick Ctrl & Status Reg.          */
  305. #define  CPU_REG_NVIC_ST_RELOAD         (*((volatile CPU_INT32U *)(0xE000E014))) /* SysTick Reload      Value Reg.      */
  306. #define  CPU_REG_NVIC_ST_CURRENT        (*((volatile CPU_INT32U *)(0xE000E018))) /* SysTick Current     Value Reg.      */
  307. #define  CPU_REG_NVIC_ST_CAL            (*((volatile CPU_INT32U *)(0xE000E01C))) /* SysTick Calibration Value Reg.      */
  308.                                                                                  /* IRQ Set En Reg.                     */
  309. #define  CPU_REG_NVIC_SETEN(n)          (*((volatile CPU_INT32U *)(0xE000E100 + (n) * 4)))
  310.                                                                                  /* IRQ Clr En Reg.                     */
  311. #define  CPU_REG_NVIC_CLREN(n)          (*((volatile CPU_INT32U *)(0xE000E180 + (n) * 4)))
  312.                                                                                  /* IRQ Set Pending Reg.                */
  313. #define  CPU_REG_NVIC_SETPEND(n)        (*((volatile CPU_INT32U *)(0xE000E200 + (n) * 4)))
  314.                                                                                  /* IRQ Clr Pending Reg.                */
  315. #define  CPU_REG_NVIC_CLRPEND(n)        (*((volatile CPU_INT32U *)(0xE000E280 + (n) * 4)))
  316.                                                                                  /* IRQ Active Reg.                     */
  317. #define  CPU_REG_NVIC_ACTIVE(n)         (*((volatile CPU_INT32U *)(0xE000E300 + (n) * 4)))
  318.                                                                                  /* IRQ Prio Reg.                       */
  319. #define  CPU_REG_NVIC_PRIO(n)           (*((volatile CPU_INT32U *)(0xE000E400 + (n) * 4)))
  321. #define  CPU_REG_NVIC_CPUID             (*((volatile CPU_INT32U *)(0xE000ED00))) /* CPUID Base Reg.                     */
  322. #define  CPU_REG_NVIC_ICSR              (*((volatile CPU_INT32U *)(0xE000ED04))) /* Int Ctrl State  Reg.                */
  323. #define  CPU_REG_NVIC_VTOR              (*((volatile CPU_INT32U *)(0xE000ED08))) /* Vect Tbl Offset Reg.                */
  324. #define  CPU_REG_NVIC_AIRCR             (*((volatile CPU_INT32U *)(0xE000ED0C))) /* App Int/Reset Ctrl Reg.             */
  325. #define  CPU_REG_NVIC_SCR               (*((volatile CPU_INT32U *)(0xE000ED10))) /* System Ctrl Reg.                    */
  326. #define  CPU_REG_NVIC_CCR               (*((volatile CPU_INT32U *)(0xE000ED14))) /* Cfg    Ctrl Reg.                    */
  327. #define  CPU_REG_NVIC_SHPRI1            (*((volatile CPU_INT32U *)(0xE000ED18))) /* System Handlers  4 to  7 Prio.      */
  328. #define  CPU_REG_NVIC_SHPRI2            (*((volatile CPU_INT32U *)(0xE000ED1C))) /* System Handlers  8 to 11 Prio.      */
  329. #define  CPU_REG_NVIC_SHPRI3            (*((volatile CPU_INT32U *)(0xE000ED20))) /* System Handlers 12 to 15 Prio.      */
  330. #define  CPU_REG_NVIC_SHCSR             (*((volatile CPU_INT32U *)(0xE000ED24))) /* System Handler Ctrl & State Reg.    */
  331. #define  CPU_REG_NVIC_CFSR              (*((volatile CPU_INT32U *)(0xE000ED28))) /* Configurable Fault Status Reg.      */
  332. #define  CPU_REG_NVIC_HFSR              (*((volatile CPU_INT32U *)(0xE000ED2C))) /* Hard  Fault Status Reg.             */
  333. #define  CPU_REG_NVIC_DFSR              (*((volatile CPU_INT32U *)(0xE000ED30))) /* Debug Fault Status Reg.             */
  334. #define  CPU_REG_NVIC_MMFAR             (*((volatile CPU_INT32U *)(0xE000ED34))) /* Mem Manage Addr Reg.                */
  335. #define  CPU_REG_NVIC_BFAR              (*((volatile CPU_INT32U *)(0xE000ED38))) /* Bus Fault  Addr Reg.                */
  336. #define  CPU_REG_NVIC_AFSR              (*((volatile CPU_INT32U *)(0xE000ED3C))) /* Aux Fault Status Reg.               */
  338. #define  CPU_REG_NVIC_PFR0              (*((volatile CPU_INT32U *)(0xE000ED40))) /* Processor Feature Reg 0.            */
  339. #define  CPU_REG_NVIC_PFR1              (*((volatile CPU_INT32U *)(0xE000ED44))) /* Processor Feature Reg 1.            */
  340. #define  CPU_REG_NVIC_DFR0              (*((volatile CPU_INT32U *)(0xE000ED48))) /* Debug     Feature Reg 0.            */
  341. #define  CPU_REG_NVIC_AFR0              (*((volatile CPU_INT32U *)(0xE000ED4C))) /* Aux       Feature Reg 0.            */
  342. #define  CPU_REG_NVIC_MMFR0             (*((volatile CPU_INT32U *)(0xE000ED50))) /* Memory Model Feature Reg 0.         */
  343. #define  CPU_REG_NVIC_MMFR1             (*((volatile CPU_INT32U *)(0xE000ED54))) /* Memory Model Feature Reg 1.         */
  344. #define  CPU_REG_NVIC_MMFR2             (*((volatile CPU_INT32U *)(0xE000ED58))) /* Memory Model Feature Reg 2.         */
  345. #define  CPU_REG_NVIC_MMFR3             (*((volatile CPU_INT32U *)(0xE000ED5C))) /* Memory Model Feature Reg 3.         */
  346. #define  CPU_REG_NVIC_ISAFR0            (*((volatile CPU_INT32U *)(0xE000ED60))) /* ISA Feature Reg 0.                  */
  347. #define  CPU_REG_NVIC_ISAFR1            (*((volatile CPU_INT32U *)(0xE000ED64))) /* ISA Feature Reg 1.                  */
  348. #define  CPU_REG_NVIC_ISAFR2            (*((volatile CPU_INT32U *)(0xE000ED68))) /* ISA Feature Reg 2.                  */
  349. #define  CPU_REG_NVIC_ISAFR3            (*((volatile CPU_INT32U *)(0xE000ED6C))) /* ISA Feature Reg 3.                  */
  350. #define  CPU_REG_NVIC_ISAFR4            (*((volatile CPU_INT32U *)(0xE000ED70))) /* ISA Feature Reg 4.                  */
  351. #define  CPU_REG_NVIC_SW_TRIG           (*((volatile CPU_INT32U *)(0xE000EF00))) /* Software Trigger Int Reg.           */
  353. #define  CPU_REG_MPU_TYPE               (*((volatile CPU_INT32U *)(0xE000ED90))) /* MPU Type Reg.                       */
  354. #define  CPU_REG_MPU_CTRL               (*((volatile CPU_INT32U *)(0xE000ED94))) /* MPU Ctrl Reg.                       */
  355. #define  CPU_REG_MPU_REG_NBR            (*((volatile CPU_INT32U *)(0xE000ED98))) /* MPU Region Nbr Reg.                 */
  356. #define  CPU_REG_MPU_REG_BASE           (*((volatile CPU_INT32U *)(0xE000ED9C))) /* MPU Region Base Addr Reg.           */
  357. #define  CPU_REG_MPU_REG_ATTR           (*((volatile CPU_INT32U *)(0xE000EDA0))) /* MPU Region Attrib & Size Reg.       */
  359. #define  CPU_REG_DBG_CTRL               (*((volatile CPU_INT32U *)(0xE000EDF0))) /* Debug Halting Ctrl & Status Reg.    */
  360. #define  CPU_REG_DBG_SELECT             (*((volatile CPU_INT32U *)(0xE000EDF4))) /* Debug Core Reg Selector Reg.        */
  361. #define  CPU_REG_DBG_DATA               (*((volatile CPU_INT32U *)(0xE000EDF8))) /* Debug Core Reg Data     Reg.        */
  362. #define  CPU_REG_DBG_INT                (*((volatile CPU_INT32U *)(0xE000EDFC))) /* Debug Except & Monitor Ctrl Reg.    */
  364. /*
  365. *********************************************************************************************************
  366. *                                          CPU REGISTER BITS
  367. *********************************************************************************************************
  368. */
  370.                                                                 /* ---------- SYSTICK CTRL & STATUS REG BITS ---------- */
  371. #define  CPU_REG_NVIC_ST_CTRL_COUNTFLAG         DEF_BIT_16
  372. #define  CPU_REG_NVIC_ST_CTRL_CLKSOURCE         DEF_BIT_02
  373. #define  CPU_REG_NVIC_ST_CTRL_TICKINT           DEF_BIT_01
  374. #define  CPU_REG_NVIC_ST_CTRL_ENABLE            DEF_BIT_00
  377.                                                                 /* -------- SYSTICK CALIBRATION VALUE REG BITS -------- */
  378. #define  CPU_REG_NVIC_ST_CAL_NOREF              DEF_BIT_31
  379. #define  CPU_REG_NVIC_ST_CAL_SKEW               DEF_BIT_30
  381.                                                                 /* -------------- INT CTRL STATE REG BITS ------------- */
  382. #define  CPU_REG_NVIC_ICSR_NMIPENDSET           DEF_BIT_31
  383. #define  CPU_REG_NVIC_ICSR_PENDSVSET            DEF_BIT_28
  384. #define  CPU_REG_NVIC_ICSR_PENDSVCLR            DEF_BIT_27
  385. #define  CPU_REG_NVIC_ICSR_PENDSTSET            DEF_BIT_26
  386. #define  CPU_REG_NVIC_ICSR_PENDSTCLR            DEF_BIT_25
  387. #define  CPU_REG_NVIC_ICSR_ISRPREEMPT           DEF_BIT_23
  388. #define  CPU_REG_NVIC_ICSR_ISRPENDING           DEF_BIT_22
  389. #define  CPU_REG_NVIC_ICSR_RETTOBASE            DEF_BIT_11
  391.                                                                 /* ------------- VECT TBL OFFSET REG BITS ------------- */
  392. #define  CPU_REG_NVIC_VTOR_TBLBASE              DEF_BIT_29
  394.                                                                 /* ------------ APP INT/RESET CTRL REG BITS ----------- */
  395. #define  CPU_REG_NVIC_AIRCR_ENDIANNESS          DEF_BIT_15
  396. #define  CPU_REG_NVIC_AIRCR_SYSRESETREQ         DEF_BIT_02
  397. #define  CPU_REG_NVIC_AIRCR_VECTCLRACTIVE       DEF_BIT_01
  398. #define  CPU_REG_NVIC_AIRCR_VECTRESET           DEF_BIT_00
  400.                                                                 /* --------------- SYSTEM CTRL REG BITS --------------- */
  401. #define  CPU_REG_NVIC_SCR_SEVONPEND             DEF_BIT_04
  402. #define  CPU_REG_NVIC_SCR_SLEEPDEEP             DEF_BIT_02
  403. #define  CPU_REG_NVIC_SCR_SLEEPONEXIT           DEF_BIT_01
  405.                                                                 /* ----------------- CFG CTRL REG BITS ---------------- */
  406. #define  CPU_REG_NVIC_CCR_STKALIGN              DEF_BIT_09
  407. #define  CPU_REG_NVIC_CCR_BFHFNMIGN             DEF_BIT_08
  408. #define  CPU_REG_NVIC_CCR_DIV_0_TRP             DEF_BIT_04
  409. #define  CPU_REG_NVIC_CCR_UNALIGN_TRP           DEF_BIT_03
  410. #define  CPU_REG_NVIC_CCR_USERSETMPEND          DEF_BIT_01
  411. #define  CPU_REG_NVIC_CCR_NONBASETHRDENA        DEF_BIT_00
  413.                                                                 /* ------- SYSTEM HANDLER CTRL & STATE REG BITS ------- */
  414. #define  CPU_REG_NVIC_SHCSR_USGFAULTENA         DEF_BIT_18
  415. #define  CPU_REG_NVIC_SHCSR_BUSFAULTENA         DEF_BIT_17
  416. #define  CPU_REG_NVIC_SHCSR_MEMFAULTENA         DEF_BIT_16
  417. #define  CPU_REG_NVIC_SHCSR_SVCALLPENDED        DEF_BIT_15
  418. #define  CPU_REG_NVIC_SHCSR_BUSFAULTPENDED      DEF_BIT_14
  419. #define  CPU_REG_NVIC_SHCSR_MEMFAULTPENDED      DEF_BIT_13
  420. #define  CPU_REG_NVIC_SHCSR_USGFAULTPENDED      DEF_BIT_12
  421. #define  CPU_REG_NVIC_SHCSR_SYSTICKACT          DEF_BIT_11
  422. #define  CPU_REG_NVIC_SHCSR_PENDSVACT           DEF_BIT_10
  423. #define  CPU_REG_NVIC_SHCSR_MONITORACT          DEF_BIT_08
  424. #define  CPU_REG_NVIC_SHCSR_SVCALLACT           DEF_BIT_07
  425. #define  CPU_REG_NVIC_SHCSR_USGFAULTACT         DEF_BIT_03
  426. #define  CPU_REG_NVIC_SHCSR_BUSFAULTACT         DEF_BIT_01
  427. #define  CPU_REG_NVIC_SHCSR_MEMFAULTACT         DEF_BIT_00
  429.                                                                 /* -------- CONFIGURABLE FAULT STATUS REG BITS -------- */
  430. #define  CPU_REG_NVIC_CFSR_DIVBYZERO            DEF_BIT_25
  431. #define  CPU_REG_NVIC_CFSR_UNALIGNED            DEF_BIT_24
  432. #define  CPU_REG_NVIC_CFSR_NOCP                 DEF_BIT_19
  433. #define  CPU_REG_NVIC_CFSR_INVPC                DEF_BIT_18
  434. #define  CPU_REG_NVIC_CFSR_INVSTATE             DEF_BIT_17
  435. #define  CPU_REG_NVIC_CFSR_UNDEFINSTR           DEF_BIT_16
  436. #define  CPU_REG_NVIC_CFSR_BFARVALID            DEF_BIT_15
  437. #define  CPU_REG_NVIC_CFSR_STKERR               DEF_BIT_12
  438. #define  CPU_REG_NVIC_CFSR_UNSTKERR             DEF_BIT_11
  439. #define  CPU_REG_NVIC_CFSR_IMPRECISERR          DEF_BIT_10
  440. #define  CPU_REG_NVIC_CFSR_PRECISERR            DEF_BIT_09
  441. #define  CPU_REG_NVIC_CFSR_IBUSERR              DEF_BIT_08
  442. #define  CPU_REG_NVIC_CFSR_MMARVALID            DEF_BIT_07
  443. #define  CPU_REG_NVIC_CFSR_MSTKERR              DEF_BIT_04
  444. #define  CPU_REG_NVIC_CFSR_MUNSTKERR            DEF_BIT_03
  445. #define  CPU_REG_NVIC_CFSR_DACCVIOL             DEF_BIT_01
  446. #define  CPU_REG_NVIC_CFSR_IACCVIOL             DEF_BIT_00
  448.                                                                 /* ------------ HARD FAULT STATUS REG BITS ------------ */
  449. #define  CPU_REG_NVIC_HFSR_DEBUGEVT             DEF_BIT_31
  450. #define  CPU_REG_NVIC_HFSR_FORCED               DEF_BIT_30
  451. #define  CPU_REG_NVIC_HFSR_VECTTBL              DEF_BIT_01
  453.                                                                 /* ------------ DEBUG FAULT STATUS REG BITS ----------- */
  454. #define  CPU_REG_NVIC_DFSR_EXTERNAL             DEF_BIT_04
  455. #define  CPU_REG_NVIC_DFSR_VCATCH               DEF_BIT_03
  456. #define  CPU_REG_NVIC_DFSR_DWTTRAP              DEF_BIT_02
  457. #define  CPU_REG_NVIC_DFSR_BKPT                 DEF_BIT_01
  458. #define  CPU_REG_NVIC_DFSR_HALTED               DEF_BIT_00
  460. /*$PAGE*/
  461. /*
  462. *********************************************************************************************************
  463. *                                        CONFIGURATION ERRORS
  464. *********************************************************************************************************
  465. */
  467. #ifndef   CPU_CFG_ADDR_SIZE
  468. #error   "CPU_CFG_ADDR_SIZE              not #define'd in 'cpu.h'               "
  469. #error   "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
  470. #error   "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
  471. #error   "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
  473. #elif   ((CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_08) && 
  474.          (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_16) && 
  475.          (CPU_CFG_ADDR_SIZE != CPU_WORD_SIZE_32))
  476. #error   "CPU_CFG_ADDR_SIZE        illegally #define'd in 'cpu.h'               "
  477. #error   "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
  478. #error   "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
  479. #error   "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
  480. #endif
  483. #ifndef   CPU_CFG_DATA_SIZE
  484. #error   "CPU_CFG_DATA_SIZE              not #define'd in 'cpu.h'               "
  485. #error   "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
  486. #error   "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
  487. #error   "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
  489. #elif   ((CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_08) && 
  490.          (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_16) && 
  491.          (CPU_CFG_DATA_SIZE != CPU_WORD_SIZE_32))
  492. #error   "CPU_CFG_DATA_SIZE        illegally #define'd in 'cpu.h'               "
  493. #error   "                         [MUST be  CPU_WORD_SIZE_08   8-bit alignment]"
  494. #error   "                         [     ||  CPU_WORD_SIZE_16  16-bit alignment]"
  495. #error   "                         [     ||  CPU_WORD_SIZE_32  32-bit alignment]"
  496. #endif
  500. #ifndef   CPU_CFG_ENDIAN_TYPE
  501. #error   "CPU_CFG_ENDIAN_TYPE            not #define'd in 'cpu.h'   "
  502. #error   "                         [MUST be  CPU_ENDIAN_TYPE_BIG   ]"
  503. #error   "                         [     ||  CPU_ENDIAN_TYPE_LITTLE]"
  505. #elif   ((CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_BIG   ) && 
  506.          (CPU_CFG_ENDIAN_TYPE != CPU_ENDIAN_TYPE_LITTLE))
  507. #error   "CPU_CFG_ENDIAN_TYPE      illegally #define'd in 'cpu.h'   "
  508. #error   "                         [MUST be  CPU_ENDIAN_TYPE_BIG   ]"
  509. #error   "                         [     ||  CPU_ENDIAN_TYPE_LITTLE]"
  510. #endif
  515. #ifndef   CPU_CFG_CRITICAL_METHOD
  516. #error   "CPU_CFG_CRITICAL_METHOD        not #define'd in 'cpu.h'             "
  517. #error   "                         [MUST be  CPU_CRITICAL_METHOD_INT_DIS_EN  ]"
  518. #error   "                         [     ||  CPU_CRITICAL_METHOD_STATUS_STK  ]"
  519. #error   "                         [     ||  CPU_CRITICAL_METHOD_STATUS_LOCAL]"
  521. #elif   ((CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_INT_DIS_EN  ) && 
  522.          (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_STK  ) && 
  523.          (CPU_CFG_CRITICAL_METHOD != CPU_CRITICAL_METHOD_STATUS_LOCAL))
  524. #error   "CPU_CFG_CRITICAL_METHOD  illegally #define'd in 'cpu.h'             "
  525. #error   "                         [MUST be  CPU_CRITICAL_METHOD_INT_DIS_EN  ]"
  526. #error   "                         [     ||  CPU_CRITICAL_METHOD_STATUS_STK  ]"
  527. #error   "                         [     ||  CPU_CRITICAL_METHOD_STATUS_LOCAL]"
  528. #endif
  531. /*$PAGE*/
  532. /*
  533. *********************************************************************************************************
  534. *                                             MODULE END
  535. *********************************************************************************************************
  536. */
  538. #endif                                                          /* End of CPU cfg module inclusion.                     */