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cpu_c.c
资源名称：STM32-uCOS-II_UAV.rar　[点击查看]
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上传日期：2017-01-28
资源大小：2911k
文件大小：28k
源码类别：

uCOS

开发平台：

C/C++

cpu_c.c：源码内容
  1. /*
  2. *********************************************************************************************************
  3. *                                               uC/CPU
  4. *                                    CPU CONFIGURATION & PORT LAYER
  5. *
  6. *                          (c) Copyright 2004-2008; Micrium, Inc.; Weston, FL
  7. *
  8. *               All rights reserved.  Protected by international copyright laws.
  9. *
  10. *               uC/CPU is provided in source form for FREE evaluation, for educational
  11. *               use or peaceful research.  If you plan on using uC/CPU in a commercial
  12. *               product you need to contact Micrium to properly license its use in your
  13. *               product.  We provide ALL the source code for your convenience and to
  14. *               help you experience uC/CPU.  The fact that the source code is provided
  15. *               does NOT mean that you can use it without paying a licensing fee.
  16. *
  17. *               Knowledge of the source code may NOT be used to develop a similar product.
  18. *
  19. *               Please help us continue to provide the Embedded community with the finest
  20. *               software available.  Your honesty is greatly appreciated.
  21. *********************************************************************************************************
  22. */
  24. /*
  25. *********************************************************************************************************
  26. *
  27. *                                            CPU PORT FILE
  28. *
  29. *                                            ARM-Cortex-M3
  30. *                                      RealView Development Suite
  31. *                            RealView Microcontroller Development Kit (MDK)
  32. *                                       ARM Developer Suite (ADS)
  33. *                                            Keil uVision
  34. *
  35. * Filename      : cpu_c.c
  36. * Version       : V1.19
  37. * Programmer(s) : JJL
  38. *                 BAN
  39. *********************************************************************************************************
  40. */
  43. /*
  44. *********************************************************************************************************
  45. *                                              INCLUDE FILES
  46. *********************************************************************************************************
  47. */
  49. #include  <cpu.h>
  50. #include  <lib_def.h>
  53. /*
  54. *********************************************************************************************************
  55. *                                              LOCAL DEFINES
  56. *********************************************************************************************************
  57. */
  59. #define  CPU_INT_SRC_POS_MAX      ((((CPU_REG_NVIC_NVIC + 1) & 0x1F) * 32) + 1)
  61. #define  CPU_BIT_BAND_SRAM_REG_LO       0x20000000
  62. #define  CPU_BIT_BAND_SRAM_REG_HI       0x200FFFFF
  63. #define  CPU_BIT_BAND_SRAM_BASE         0x22000000
  66. #define  CPU_BIT_BAND_PERIPH_REG_LO     0x40000000
  67. #define  CPU_BIT_BAND_PERIPH_REG_HI     0x400FFFFF
  68. #define  CPU_BIT_BAND_PERIPH_BASE       0x42000000
  71. /*
  72. *********************************************************************************************************
  73. *                                             LOCAL CONSTANTS
  74. *********************************************************************************************************
  75. */
  78. /*
  79. *********************************************************************************************************
  80. *                                            LOCAL DATA TYPES
  81. *********************************************************************************************************
  82. */
  85. /*
  86. *********************************************************************************************************
  87. *                                              LOCAL TABLES
  88. *********************************************************************************************************
  89. */
  92. /*
  93. *********************************************************************************************************
  94. *                                         LOCAL GLOBAL VARIABLES
  95. *********************************************************************************************************
  96. */
  99. /*
  100. *********************************************************************************************************
  101. *                                        LOCAL FUNCTION PROTOTYPES
  102. *********************************************************************************************************
  103. */
  106. /*
  107. *********************************************************************************************************
  108. *                                       LOCAL CONFIGURATION ERRORS
  109. *********************************************************************************************************
  110. */
  112. /*
  113. *********************************************************************************************************
  114. *                                           CPU_BitBandClr()
  115. *
  116. * Description : Clear bit in bit-band region.
  117. *
  118. * Argument(s) : addr            Byte address in memory space.
  119. *
  120. *               bit_nbr         Bit number in byte.
  121. *
  122. * Return(s)   : none.
  123. *
  124. * Caller(s)   : Application.
  125. *
  126. * Note(s)     : none.
  127. *********************************************************************************************************
  128. */
  130. void  CPU_BitBandClr (CPU_ADDR    addr,
  131.                       CPU_INT08U  bit_nbr)
  132. {
  133.     CPU_ADDR  bit_word_off;
  134.     CPU_ADDR  bit_word_addr;
  137.     if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
  138.         (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
  139.         bit_word_off  = ((addr - CPU_BIT_BAND_SRAM_REG_LO) * 32) + (bit_nbr * 4);
  140.         bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
  142.        *(volatile CPU_INT32U *)(bit_word_addr) = 0;
  144.     } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
  145.                (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
  146.         bit_word_off  = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
  147.         bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
  149.        *(volatile CPU_INT32U *)(bit_word_addr) = 0;
  150.     }
  151. }
  154. /*
  155. *********************************************************************************************************
  156. *                                           CPU_BitBandClr()
  157. *
  158. * Description : Set bit in bit-band region.
  159. *
  160. * Argument(s) : addr            Byte address in memory space.
  161. *
  162. *               bit_nbr         Bit number in byte.
  163. *
  164. * Return(s)   : none.
  165. *
  166. * Caller(s)   : Application.
  167. *
  168. * Note(s)     : none.
  169. *********************************************************************************************************
  170. */
  172. void  CPU_BitBandSet (CPU_ADDR    addr,
  173.                       CPU_INT08U  bit_nbr)
  174. {
  175.     CPU_ADDR  bit_word_off;
  176.     CPU_ADDR  bit_word_addr;
  179.     if ((addr >= CPU_BIT_BAND_SRAM_REG_LO) &&
  180.         (addr <= CPU_BIT_BAND_SRAM_REG_HI)) {
  181.         bit_word_off  = ((addr - CPU_BIT_BAND_SRAM_REG_LO) * 32) + (bit_nbr * 4);
  182.         bit_word_addr = CPU_BIT_BAND_SRAM_BASE + bit_word_off;
  184.        *(volatile CPU_INT32U *)(bit_word_addr) = 1;
  186.     } else if ((addr >= CPU_BIT_BAND_PERIPH_REG_LO) &&
  187.                (addr <= CPU_BIT_BAND_PERIPH_REG_HI)) {
  188.         bit_word_off  = ((addr - CPU_BIT_BAND_PERIPH_REG_LO) * 32) + (bit_nbr * 4);
  189.         bit_word_addr = CPU_BIT_BAND_PERIPH_BASE + bit_word_off;
  191.        *(volatile CPU_INT32U *)(bit_word_addr) = 1;
  192.     }
  193. }
  196. /*
  197. *********************************************************************************************************
  198. *                                           CPU_IntSrcDis()
  199. *
  200. * Description : Disable an interrupt source.
  201. *
  202. * Argument(s) : pos     Position of interrupt vector in interrupt table :
  203. *
  204. *                           0       Invalid (see Note #1a).
  205. *                           1       Invalid (see Note #1b).
  206. *                           2       Non-maskable interrupt.
  207. *                           3       Hard Fault.
  208. *                           4       Memory Management.
  209. *                           5       Bus Fault.
  210. *                           6       Usage Fault.
  211. *                           7-10    Reserved.
  212. *                           11      SVCall
  213. *                           12      Debug monitor.
  214. *                           13      Reserved
  215. *                           14      PendSV.
  216. *                           15      SysTick.
  217. *                           16+     External Interrupt.
  218. *
  219. * Return(s)   : none.
  220. *
  221. * Caller(s)   : Application.
  222. *
  223. * Note(s)     : (1) Several table positions do not contain interrupt sources :
  224. *
  225. *                   (a) Position 0 contains the stack pointer.
  226. *                   (b) Positions 7-10, 13 are reserved.
  227. *
  228. *               (2) Several interrupts cannot be disabled/enabled :
  229. *
  230. *                   (a) Reset.
  231. *                   (b) NMI.
  232. *                   (c) Hard fault.
  233. *                   (d) SVCall.
  234. *                   (e) Debug monitor.
  235. *                   (f) PendSV.
  236. *
  237. *               (3) The maximum Cortex-M3 table position is 256.  A particular Cortex-M3 may have fewer
  238. *                   than 240 external exceptions and, consequently, fewer than 256 table positions.
  239. *                   This function assumes that the specified table position is valid if the interrupt
  240. *                   controller type register's INTLINESNUM field is large enough so that the position
  241. *                   COULD be valid.
  242. *********************************************************************************************************
  243. */
  245. void  CPU_IntSrcDis (CPU_INT08U  pos)
  246. {
  247. #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
  248.     CPU_SR      cpu_sr;
  249. #endif
  250.     CPU_INT08U  group;
  251.     CPU_INT08U  pos_max;
  252.     CPU_INT08U  nbr;
  255.     switch (pos) {
  256.         case CPU_INT_STK_PTR:                                   /* ---------------- INVALID OR RESERVED --------------- */
  257.         case CPU_INT_RSVD_07:
  258.         case CPU_INT_RSVD_08:
  259.         case CPU_INT_RSVD_09:
  260.         case CPU_INT_RSVD_10:
  261.         case CPU_INT_RSVD_13:
  262.              break;
  265.                                                                 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
  266.         case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
  267.         case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
  268.         case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
  269.         case CPU_INT_SVCALL:                                    /* SVCall (see Note #2).                                */
  270.         case CPU_INT_DBGMON:                                    /* Debug monitor (see Note #2).                         */
  271.         case CPU_INT_PENDSV:                                    /* PendSV (see Note #2).                                */
  272.              break;
  274.         case CPU_INT_MEM:                                       /* Memory management.                                   */
  275.              CPU_CRITICAL_ENTER();
  276.              CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_MEMFAULTENA;
  277.              CPU_CRITICAL_EXIT();
  278.              break;
  280.         case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
  281.              CPU_CRITICAL_ENTER();
  282.              CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_BUSFAULTENA;
  283.              CPU_CRITICAL_EXIT();
  284.              break;
  286.         case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
  287.              CPU_CRITICAL_ENTER();
  288.              CPU_REG_NVIC_SHCSR &= ~CPU_REG_NVIC_SHCSR_USGFAULTENA;
  289.              CPU_CRITICAL_EXIT();
  290.              break;
  292.         case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
  293.              CPU_CRITICAL_ENTER();
  294.              CPU_REG_NVIC_ST_CTRL &= ~CPU_REG_NVIC_ST_CTRL_ENABLE;
  295.              CPU_CRITICAL_EXIT();
  296.              break;
  299.                                                                 /* ---------------- EXTERNAL INTERRUPT ---------------- */
  300.         default:
  301.             pos_max = CPU_INT_SRC_POS_MAX;
  302.             if (pos < pos_max) {                                /* See Note #3.                                         */
  303.                  group = (pos - 16) / 32;
  304.                  nbr   = (pos - 16) % 32;
  306.                  CPU_CRITICAL_ENTER();
  307.                  CPU_REG_NVIC_CLREN(group) = DEF_BIT(nbr);
  308.                  CPU_CRITICAL_EXIT();
  309.              }
  310.              break;
  311.     }
  312. }
  315. /*
  316. *********************************************************************************************************
  317. *                                           CPU_IntSrcEn()
  318. *
  319. * Description : Enable an interrupt source.
  320. *
  321. * Argument(s) : pos     Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
  322. *
  323. * Return(s)   : none.
  324. *
  325. * Caller(s)   : Application.
  326. *
  327. * Note(s)     : (1) See 'CPU_IntSrcDis() Note #1'.
  328. *
  329. *               (2) See 'CPU_IntSrcDis() Note #2'.
  330. *
  331. *               (3) See 'CPU_IntSrcDis() Note #3'.
  332. *********************************************************************************************************
  333. */
  335. void  CPU_IntSrcEn (CPU_INT08U  pos)
  336. {
  337. #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
  338.     CPU_SR      cpu_sr;
  339. #endif
  340.     CPU_INT08U  group;
  341.     CPU_INT08U  nbr;
  342.     CPU_INT08U  pos_max;
  345.     switch (pos) {
  346.         case CPU_INT_STK_PTR:                                   /* ---------------- INVALID OR RESERVED --------------- */
  347.         case CPU_INT_RSVD_07:
  348.         case CPU_INT_RSVD_08:
  349.         case CPU_INT_RSVD_09:
  350.         case CPU_INT_RSVD_10:
  351.         case CPU_INT_RSVD_13:
  352.              break;
  355.                                                                 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
  356.         case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
  357.         case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
  358.         case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
  359.         case CPU_INT_SVCALL:                                    /* SVCall (see Note #2).                                */
  360.         case CPU_INT_DBGMON:                                    /* Debug monitor (see Note #2).                         */
  361.         case CPU_INT_PENDSV:                                    /* PendSV (see Note #2).                                */
  362.              break;
  364.         case CPU_INT_MEM:                                       /* Memory management.                                   */
  365.              CPU_CRITICAL_ENTER();
  366.              CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_MEMFAULTENA;
  367.              CPU_CRITICAL_EXIT();
  368.              break;
  370.         case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
  371.              CPU_CRITICAL_ENTER();
  372.              CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_BUSFAULTENA;
  373.              CPU_CRITICAL_EXIT();
  374.              break;
  376.         case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
  377.              CPU_CRITICAL_ENTER();
  378.              CPU_REG_NVIC_SHCSR |= CPU_REG_NVIC_SHCSR_USGFAULTENA;
  379.              CPU_CRITICAL_EXIT();
  380.              break;
  382.         case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
  383.              CPU_CRITICAL_ENTER();
  384.              CPU_REG_NVIC_ST_CTRL |= CPU_REG_NVIC_ST_CTRL_ENABLE;
  385.              CPU_CRITICAL_EXIT();
  386.              break;
  389.                                                                 /* ---------------- EXTERNAL INTERRUPT ---------------- */
  390.         default:
  391.             pos_max = CPU_INT_SRC_POS_MAX;
  392.             if (pos < pos_max) {                                /* See Note #3.                                         */
  393.                  group = (pos - 16) / 32;
  394.                  nbr   = (pos - 16) % 32;
  396.                  CPU_CRITICAL_ENTER();
  397.                  CPU_REG_NVIC_SETEN(group) = DEF_BIT(nbr);
  398.                  CPU_CRITICAL_EXIT();
  399.              }
  400.              break;
  401.     }
  402. }
  405. /*
  406. *********************************************************************************************************
  407. *                                           CPU_IntSrcPrioSet()
  408. *
  409. * Description : Set priority of an interrupt source.
  410. *
  411. * Argument(s) : pos     Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
  412. *
  413. *               prio    Priority.  Use a lower priority number for a higher priority.
  414. *
  415. * Return(s)   : none.
  416. *
  417. * Caller(s)   : Application.
  418. *
  419. * Note(s)     : (1) See 'CPU_IntSrcDis() Note #1'.
  420. *
  421. *               (2) Several interrupts priorities CANNOT be set :
  422. *
  423. *                   (a) Reset (always -3).
  424. *                   (b) NMI (always -2).
  425. *                   (c) Hard fault (always -1).
  426. *
  427. *               (3) See 'CPU_IntSrcDis() Note #3'.
  428. *********************************************************************************************************
  429. */
  431. void  CPU_IntSrcPrioSet (CPU_INT08U  pos,
  432.                          CPU_INT08U  prio)
  433. {
  434. #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
  435.     CPU_SR      cpu_sr;
  436. #endif
  437.     CPU_INT08U  group;
  438.     CPU_INT08U  nbr;
  439.     CPU_INT08U  pos_max;
  440.     CPU_INT32U  prio_32;
  441.     CPU_INT32U  temp;
  444.     prio_32 = CPU_RevBits((CPU_INT08U)prio);
  445.     prio    = (CPU_INT08U)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
  447.     switch (pos) {
  448.         case CPU_INT_STK_PTR:                                   /* ---------------- INVALID OR RESERVED --------------- */
  449.         case CPU_INT_RSVD_07:
  450.         case CPU_INT_RSVD_08:
  451.         case CPU_INT_RSVD_09:
  452.         case CPU_INT_RSVD_10:
  453.         case CPU_INT_RSVD_13:
  454.              break;
  457.                                                                 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
  458.         case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
  459.         case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
  460.         case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
  461.              break;
  463.         case CPU_INT_MEM:                                       /* Memory management.                                   */
  464.              CPU_CRITICAL_ENTER();
  465.              temp                 = CPU_REG_NVIC_SHPRI1;
  466.              temp                &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
  467.              temp                |=  (prio           << (0 * DEF_OCTET_NBR_BITS));
  468.              CPU_REG_NVIC_SHPRI1  = temp;
  469.              CPU_CRITICAL_EXIT();
  470.              break;
  472.         case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
  473.              CPU_CRITICAL_ENTER();
  474.              temp                 = CPU_REG_NVIC_SHPRI1;
  475.              temp                &= ~(DEF_OCTET_MASK << (1 * DEF_OCTET_NBR_BITS));
  476.              temp                |=  (prio           << (1 * DEF_OCTET_NBR_BITS));
  477.              CPU_REG_NVIC_SHPRI1  = temp;
  478.              CPU_CRITICAL_EXIT();
  479.              break;
  481.         case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
  482.              CPU_CRITICAL_ENTER();
  483.              temp                 = CPU_REG_NVIC_SHPRI1;
  484.              temp                &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
  485.              temp                |=  (prio           << (2 * DEF_OCTET_NBR_BITS));
  486.              CPU_REG_NVIC_SHPRI1  = temp;
  487.              CPU_CRITICAL_EXIT();
  488.              break;
  490.         case CPU_INT_SVCALL:                                    /* SVCall.                                              */
  491.              CPU_CRITICAL_ENTER();
  492.              temp                 = CPU_REG_NVIC_SHPRI2;
  493.              temp                &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
  494.              temp                |=  (prio                       << (3 * DEF_OCTET_NBR_BITS));
  495.              CPU_REG_NVIC_SHPRI2  = temp;
  496.              CPU_CRITICAL_EXIT();
  497.              break;
  499.         case CPU_INT_DBGMON:                                    /* Debug monitor.                                       */
  500.              CPU_CRITICAL_ENTER();
  501.              temp                = CPU_REG_NVIC_SHPRI3;
  502.              temp                &= ~(DEF_OCTET_MASK << (0 * DEF_OCTET_NBR_BITS));
  503.              temp                |=  (prio           << (0 * DEF_OCTET_NBR_BITS));
  504.              CPU_REG_NVIC_SHPRI3  = temp;
  505.              CPU_CRITICAL_EXIT();
  506.              break;
  508.         case CPU_INT_PENDSV:                                    /* PendSV.                                              */
  509.              CPU_CRITICAL_ENTER();
  510.              temp                 = CPU_REG_NVIC_SHPRI3;
  511.              temp                &= ~(DEF_OCTET_MASK << (2 * DEF_OCTET_NBR_BITS));
  512.              temp                |=  (prio           << (2 * DEF_OCTET_NBR_BITS));
  513.              CPU_REG_NVIC_SHPRI3  = temp;
  514.              CPU_CRITICAL_EXIT();
  515.              break;
  517.         case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
  518.              CPU_CRITICAL_ENTER();
  519.              temp                 = CPU_REG_NVIC_SHPRI3;
  520.              temp                &= ~((CPU_INT32U)DEF_OCTET_MASK << (3 * DEF_OCTET_NBR_BITS));
  521.              temp                |=  (prio                       << (3 * DEF_OCTET_NBR_BITS));
  522.              CPU_REG_NVIC_SHPRI3  = temp;
  523.              CPU_CRITICAL_EXIT();
  524.              break;
  527.                                                                 /* ---------------- EXTERNAL INTERRUPT ---------------- */
  528.         default:
  529.             pos_max = CPU_INT_SRC_POS_MAX;
  530.             if (pos < pos_max) {                                /* See Note #3.                                         */
  531.                  group                    = (pos - 16) / 4;
  532.                  nbr                      = (pos - 16) % 4;
  534.                  CPU_CRITICAL_ENTER();
  535.                  temp                     = CPU_REG_NVIC_PRIO(group);
  536.                  temp                    &= ~(DEF_OCTET_MASK << (nbr * DEF_OCTET_NBR_BITS));
  537.                  temp                    |=  (prio           << (nbr * DEF_OCTET_NBR_BITS));
  538.                  CPU_REG_NVIC_PRIO(group) = temp;
  539.                  CPU_CRITICAL_EXIT();
  540.              }
  541.              break;
  542.     }
  543. }
  546. /*
  547. *********************************************************************************************************
  548. *                                           CPU_IntSrcPrioGet()
  549. *
  550. * Description : Get priority of an interrupt source.
  551. *
  552. * Argument(s) : pos     Position of interrupt vector in interrupt table (see 'CPU_IntSrcDis()').
  553. *
  554. * Return(s)   : Priority of interrupt source.  If the interrupt source specified is invalid, then
  555. *               DEF_INT_16S_MIN_VAL is returned.
  556. *
  557. * Caller(s)   : Application.
  558. *
  559. * Note(s)     : (1) See 'CPU_IntSrcDis() Note #1'.
  560. *
  561. *               (2) See 'CPU_IntSrcPrioSet() Note #2'.
  562. *
  563. *               (3) See 'CPU_IntSrcDis() Note #3'.
  564. *********************************************************************************************************
  565. */
  567. CPU_INT16S  CPU_IntSrcPrioGet (CPU_INT08U  pos)
  568. {
  569. #if (CPU_CFG_CRITICAL_METHOD == CPU_CRITICAL_METHOD_STATUS_LOCAL)
  570.     CPU_SR      cpu_sr;
  571. #endif
  572.     CPU_INT08U  group;
  573.     CPU_INT08U  nbr;
  574.     CPU_INT08U  pos_max;
  575.     CPU_INT16S  prio;
  576.     CPU_INT32U  prio_32;
  577.     CPU_INT32U  temp;
  580.     switch (pos) {
  581.         case CPU_INT_STK_PTR:                                   /* ---------------- INVALID OR RESERVED --------------- */
  582.         case CPU_INT_RSVD_07:
  583.         case CPU_INT_RSVD_08:
  584.         case CPU_INT_RSVD_09:
  585.         case CPU_INT_RSVD_10:
  586.         case CPU_INT_RSVD_13:
  587.              prio = DEF_INT_16S_MIN_VAL;
  588.              break;
  591.                                                                 /* ----------------- SYSTEM EXCEPTIONS ---------------- */
  592.         case CPU_INT_RESET:                                     /* Reset (see Note #2).                                 */
  593.              prio = -3;
  594.              break;
  596.         case CPU_INT_NMI:                                       /* Non-maskable interrupt (see Note #2).                */
  597.              prio = -2;
  598.              break;
  600.         case CPU_INT_HFAULT:                                    /* Hard fault (see Note #2).                            */
  601.              prio = -1;
  602.              break;
  605.         case CPU_INT_MEM:                                       /* Memory management.                                   */
  606.              CPU_CRITICAL_ENTER();
  607.              temp = CPU_REG_NVIC_SHPRI1;
  608.              prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
  609.              CPU_CRITICAL_EXIT();
  610.              break;
  613.         case CPU_INT_BUSFAULT:                                  /* Bus fault.                                           */
  614.              CPU_CRITICAL_ENTER();
  615.              temp = CPU_REG_NVIC_SHPRI1;
  616.              prio = (temp >> (1 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
  617.              CPU_CRITICAL_EXIT();
  618.              break;
  621.         case CPU_INT_USAGEFAULT:                                /* Usage fault.                                         */
  622.              CPU_CRITICAL_ENTER();
  623.              temp = CPU_REG_NVIC_SHPRI1;
  624.              prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
  625.              break;
  627.         case CPU_INT_SVCALL:                                    /* SVCall.                                              */
  628.              CPU_CRITICAL_ENTER();
  629.              temp = CPU_REG_NVIC_SHPRI2;
  630.              prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
  631.              CPU_CRITICAL_EXIT();
  632.              break;
  634.         case CPU_INT_DBGMON:                                    /* Debug monitor.                                       */
  635.              CPU_CRITICAL_ENTER();
  636.              temp = CPU_REG_NVIC_SHPRI3;
  637.              prio = (temp >> (0 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
  638.              CPU_CRITICAL_EXIT();
  639.              break;
  641.         case CPU_INT_PENDSV:                                    /* PendSV.                                              */
  642.              CPU_CRITICAL_ENTER();
  643.              temp = CPU_REG_NVIC_SHPRI3;
  644.              prio = (temp >> (2 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
  645.              CPU_CRITICAL_EXIT();
  646.              break;
  648.         case CPU_INT_SYSTICK:                                   /* SysTick.                                             */
  649.              CPU_CRITICAL_ENTER();
  650.              temp = CPU_REG_NVIC_SHPRI3;
  651.              prio = (temp >> (3 * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
  652.              CPU_CRITICAL_EXIT();
  653.              break;
  656.                                                                 /* ---------------- EXTERNAL INTERRUPT ---------------- */
  657.         default:
  658.             pos_max = CPU_INT_SRC_POS_MAX;
  659.             if (pos < pos_max) {                                /* See Note #3.                                         */
  660.                  group = (pos - 16) / 4;
  661.                  nbr   = (pos - 16) % 4;
  663.                  CPU_CRITICAL_ENTER();
  664.                  temp  = CPU_REG_NVIC_PRIO(group);
  665.                  CPU_CRITICAL_EXIT();
  667.                  prio  = (temp >> (nbr * DEF_OCTET_NBR_BITS)) & DEF_OCTET_MASK;
  668.              } else {
  669.                  prio  = DEF_INT_16S_MIN_VAL;
  670.              }
  671.              break;
  672.     }
  674.     if (prio >= 0) {
  675.         prio_32 = CPU_RevBits((CPU_INT32U)prio);
  676.         prio    = (CPU_INT16S)(prio_32 >> (3 * DEF_OCTET_NBR_BITS));
  677.     }
  679.     return (prio);
  680. }