ixp425Pci.h
资源名称:ixp425BSP.rar [点击查看]
上传用户:luoyougen
上传日期:2008-05-12
资源大小:23136k
文件大小:9k
源码类别:
VxWorks
开发平台:
C/C++
- /* ixp425Pci.h - public header file for the ixp425 PCI unit driver */
- /* Copyright 2002 Wind River Systems, Inc. */
- /*
- modification history
- --------------------
- 01a,05jun02,jb initial version...
- */
- /*
- DESCRIPTION
- This header defines the IXP425 PCI driver interface that is made
- available for use by clients such as PCI device drivers.
- */
- #ifndef IXP425PCI_H
- #define IXP425PCI_H
- #include "ixp425.h" /*BSP defines*/
- #ifdef __cplusplus
- extern "C" {
- #endif
- /*these specify the start PCI bus addresses for
- memory and IO BARs, note these are addresses
- on the PCI bus, not ahb bus*/
- #define IXP425_PCI_BAR_MEM_BASE 0x100000
- #define IXP425_PCI_BAR_IO_BASE 0x000000
- /* These specify the range of AHB physical addresses
- that get translated into PCI addresses*/
- #define IXP425_PHYS_PCI_MEM_BASE IXP425_PCI_BASE
- #define IXP425_PHYS_PCI_IO_BASE IXP425_PCI_BASE
- #define IXP425_PHYS_PCI_MEM_TOP (IXP425_PCI_BASE + IXP425_PCI_SP_SIZE)
- /*defines required by vxWorks*/
- #define PCI_CLINE_SZ 0x0
- #define PCI_LAT_TIMER 0x0
- /*defines required by End driver*/
- #define PCI_IO_ADR0 0x0000000
- #define PCI_MEM_ADR0 0x0000000
- #define PCI_INT_LVL0 7
- #define PCI_INT_VEC0 7
- #define PCI_IO_ADR1 0x0000000
- #define PCI_MEM_ADR1 0x0000000
- #define PCI_INT_LVL1 7
- #define PCI_INT_VEC1 7
- #define PCI_IO_ADR2 0x0000000
- #define PCI_MEM_ADR2 0x0000000
- #define PCI_INT_LVL2 7
- #define PCI_INT_VEC2 7
- #define PCI_IO_ADR3 0x0000000
- #define PCI_MEM_ADR3 0x0000000
- #define PCI_INT_LVL3 7
- #define PCI_INT_VEC3 7
- #define CPU_PCI_MEM_ADRS IXP425_PHYS_PCI_MEM_BASE
- #define CPU_PCI_IO_ADRS IXP425_PHYS_PCI_IO_BASE
- /*define the sub vendor and subsystem to be used */
- #define IXP425_PCI_SUB_VENDOR_SYSTEM 0x00000000
- /* the simple mapping scheme sets up a flat translation whereby the bottom
- 64MB of SDRAM maps is accessible on the PCI bus as the bottom
- 64MB of PCI address space. This scheme only works for boards with 64 MB of
- SDRAM or less, and should not be used under normal circumstances.*/
- #undef IXP425_PCI_SIMPLE_MAPPING
- /*define the default settings for the controller's BARs*/
- #ifdef IXP425_PCI_SIMPLE_MAPPING
- #define IXP425_PCI_BAR_0_DEFAULT 0x00000000
- #define IXP425_PCI_BAR_1_DEFAULT 0x01000000
- #define IXP425_PCI_BAR_2_DEFAULT 0x02000000
- #define IXP425_PCI_BAR_3_DEFAULT 0x03000000
- #define IXP425_PCI_BAR_4_DEFAULT 0x00000000
- #define IXP425_PCI_BAR_5_DEFAULT 0x00000000
- #else
- #define IXP425_PCI_BAR_0_DEFAULT 0x40000000
- #define IXP425_PCI_BAR_1_DEFAULT 0x41000000
- #define IXP425_PCI_BAR_2_DEFAULT 0x42000000
- #define IXP425_PCI_BAR_3_DEFAULT 0x43000000
- #define IXP425_PCI_BAR_4_DEFAULT 0x00000000
- #define IXP425_PCI_BAR_5_DEFAULT 0x00000000
- #endif
- /*define the default setting of the AHB memory base reg*/
- #define IXP425_PCI_AHBMEMBASE_DEFAULT 0x00010203
- #define IXP425_PCI_AHBIOBASE_DEFAULT 0x0
- #define IXP425_PCI_PCIMEMBASE_DEFAULT 0x0
- #define IXP425_PCI_INTERNAL_INT_VEC 8
- /*define the GPIO pins used for the 4 PCI interrupts*/
- #define IXP425_PCI_INTA_PIN IXP425_GPIO_PIN_1
- /*#define IXP425_PCI_INTB_PIN IXP425_GPIO_PIN_10
- #define IXP425_PCI_INTC_PIN IXP425_GPIO_PIN_9
- #define IXP425_PCI_INTD_PIN IXP425_GPIO_PIN_8*/
- /*define the interrupt vector numbers used for the 4 PCI interrupts*/
- #define IXP425_PCI_INTA_INTERRUPT_NUM PCI_INT_LVL0
- #define IXP425_PCI_INTB_INTERRUPT_NUM PCI_INT_LVL1
- #define IXP425_PCI_INTC_INTERRUPT_NUM PCI_INT_LVL2
- #define IXP425_PCI_INTD_INTERRUPT_NUM PCI_INT_LVL3
- /*define the index into the interrupt routine linked list for
- each PCI interrupt*/
- #define IXP425_PCI_INTA_INDEX 0
- #define IXP425_PCI_INTB_INDEX 1
- #define IXP425_PCI_INTC_INDEX 2
- #define IXP425_PCI_INTD_INDEX 3
- /*define the maximum number of bus segments - we support a single segment*/
- #define IXP425_PCI_MAX_BUS 1
- /*define the maximum number of cards per bus segment*/
- #define IXP425_PCI_MAX_DEV 4
- /*define the maximum number of functions per device*/
- #define IXP425_PCI_MAX_FUNC 8
- /* define the maximum number of separate functions that we can
- potentially have on the bus*/
- #define IXP425_PCI_MAX_FUNC_ON_BUS (1+ IXP425_PCI_MAX_FUNC *
- IXP425_PCI_MAX_DEV *
- IXP425_PCI_MAX_BUS)
- /*define the maximum number of BARs per function*/
- #define IXP425_PCI_MAX_BAR_PER_FUNC 6
- #define IXP425_PCI_MAX_BAR (IXP425_PCI_MAX_BAR_PER_FUNC *
- IXP425_PCI_MAX_FUNC_ON_BUS)
- #define IXP425_PCI_DMA_DIR_IN 0
- #define IXP425_PCI_DMA_DIR_OUT 1
- /*Hardware configuration defines - these parameters are used to specify
- the particular h/w configuration of the board with regard to PCI*/
- #define IXP425_PCI_CLK_PIN IXP425_GPIO_CLK_0
- /*define whether or not we are to drive the clock through a
- GPIO pin when in host mode*/
- #define IXP425_PCI_GPIO_CLOCK_ON
- /*#undef IXP425_PCI_GPIO_CLOCK_ON*/
- /*define the GPIO pin used to supply the PCI reset signal*/
- #define IXP425_PCI_RESET_GPIO IXP425_GPIO_PIN_0
- /*Mode selection defines*/
- /*define whether byte lane routing between the Little endian PCI bus
- and big endian AHB bus is performed automatically by the PCC*/
- #define IXP425_PCI_ENABLE_BYTE_ROUTING
- typedef enum
- {
- PciClock33 = 0
- } PciClockRate;
- enum PciBarId
- {
- CSR_BAR=0,
- IO_BAR,
- SD_BAR,
- NO_BAR
- };
- /*Base address register descriptor*/
- typedef struct
- {
- UINT32 size;
- UINT32 address;
- } PciBar;
- typedef struct
- {
- UINT32 bus;
- UINT32 device;
- UINT32 func;
- UINT32 irq;
- BOOL error;
- UINT16 vendor_id;
- UINT16 device_id;
- /*We need an extra entry in this array for dummy placeholder*/
- PciBar bar[IXP425_PCI_MAX_BAR_PER_FUNC + 1];
- } PciDevice;
- typedef enum
- {
- PCI_OK = 0,
- PCI_ERR_PSE, /*System Error*/
- PCI_ERR_PFE, /*Fatal Error*/
- PCI_ERR_PPE, /*Parity Error*/
- PCI_ERR_AHBE, /*AHB Error*/
- PCI_APDC, /*ATP DMA transfer complete*/
- PCI_PADC, /*PTA DMA transfer complete*/
- PCI_ERROR /*General error*/
- }PciStatus;
- typedef void (*PCICALLBACKFUNC)(PciStatus status, UINT32 parameter);
- #if defined(__STDC__) || defined(__cplusplus)
- STATUS pciIomapLibInit (UINT32 mechanism, UINT32 addr0, UINT32 addr1, UINT32 addr2);
- STATUS pciFindDevice (UINT32 vendorId, UINT32 deviceId, UINT32 index,
- UINT32 *pBusNo, UINT32 *pDeviceNo, UINT32 *pFuncNo);
- STATUS pciFindClass (UINT32 classCode, UINT32 index,
- UINT32 *pBusNo, UINT32 *pDeviceNo, UINT32 *pFuncNo);
- STATUS pciConfigInByte (UINT32 busNo, UINT32 deviceNo, UINT32 funcNo, UINT32 address,
- UINT8 *pData);
- STATUS pciConfigInWord (UINT32 busNo, UINT32 deviceNo, UINT32 funcNo, UINT32 address,
- UINT16 *pData);
- STATUS pciConfigInLong (UINT32 busNo, UINT32 deviceNo, UINT32 funcNo, UINT32 address,
- UINT32 *pData);
- STATUS pciConfigOutByte (UINT32 busNo, UINT32 deviceNo, UINT32 funcNo, UINT32 address,
- UINT8 data);
- STATUS pciConfigOutWord (UINT32 busNo, UINT32 deviceNo, UINT32 funcNo, UINT32 address,
- UINT16 data);
- STATUS pciConfigOutLong (UINT32 busNo, UINT32 deviceNo, UINT32 funcNo, UINT32 address,
- UINT32 data);
- STATUS pciIOInByte (void *pciAddr, UINT8 *data);
- STATUS pciIOInWord (void *pciAddr, UINT16 *data);
- STATUS pciIOInLong (void *pciAddr, UINT32 *data);
- STATUS pciIOOutByte (void *pciAddr, UINT8 data);
- STATUS pciIOOutWord (void *pciAddr, UINT16 data);
- STATUS pciIOOutLong (void *pciAddr, UINT32 data);
- STATUS pciMemInByte (void *pciAddr, UINT8 *data);
- STATUS pciMemInWord (void *pciAddr, UINT16 *data);
- STATUS pciMemInLong (void *pciAddr, UINT32 *data);
- STATUS pciMemOutByte (void *pciAddr, UINT8 data);
- STATUS pciMemOutWord (void *pciAddr, UINT16 data);
- STATUS pciMemOutLong (void *pciAddr, UINT32 data);
- STATUS pciSpecialCycle (UINT32 busNo, UINT32 message);
- STATUS pciDeviceShow (UINT32 busNo);
- STATUS pciHeaderShow (UINT32 busNo, UINT32 deviceNo, UINT32 funcNo);
- STATUS pciFindClassShow (UINT32 classCode, UINT32 index);
- void pciAddrShow (void);
- STATUS pciIntConnect (VOIDFUNCPTR *vector, VOIDFUNCPTR routine,
- UINT32 parameter);
- STATUS pciIntDisconnect (VOIDFUNCPTR *vector, VOIDFUNCPTR routine);
- PciDevice *pciInfoGet (UINT16 device);
- PciDevice *pciInfoSearch (UINT32 bus, UINT32 device, UINT32 func, UINT32 count);
- PciDevice *pciDeviceGet (UINT32 vendor_id, UINT32 device_id, UINT32 count);
- void sysPciInit (void);
- void sysPciAssignAddrs (void);
- void *sysPciToPhys (void *pciAddr);
- void *sysPhysToPci (void *phyAddr);
- STATUS pciErrorCallbackRegister (PCICALLBACKFUNC routine);
- STATUS sysPciMappingAdd (UINT32 addr, UINT32 size);
- #else /* __STDC__ */
- STATUS pciIomapLibInit ();
- STATUS pciFindDevice ();
- STATUS pciFindClass ();
- STATUS pciConfigInByte ();
- STATUS pciConfigInWord ();
- STATUS pciConfigInLong ();
- STATUS pciConfigOutByte ();
- STATUS pciConfigOutWord ();
- STATUS pciConfigOutLong ();
- STATUS pciSpecialCycle ();
- STATUS pciIOInByte ();
- STATUS pciIOInWord ();
- STATUS pciIOInLong ();
- STATUS pciIOOutByte ();
- STATUS pciIOOutWord ();
- STATUS pciIOOutLong ();
- STATUS pciMemInByte ();
- STATUS pciMemInWord ();
- STATUS pciMemInLong ();
- STATUS pciMemOutByte ();
- STATUS pciMemOutWord ();
- STATUS pciMemOutLong ();
- STATUS pciDeviceShow ();
- STATUS pciHeaderShow ();
- STATUS pciFindClassShow ();
- void pciAddrShow ();
- STATUS pciIntConnect ();
- STATUS pciIntDisconnect ();
- PciDevice *pciInfoGet ();
- PciDevice *pciInfoSearch ();
- PciDevice *pciDeviceGet ();
- void sysPciInit ();
- void sysPciAssignAddrs ();
- void *sysPciToPhys ();
- void *sysPhysToPci ();
- STATUS pciErrorCallbackRegister ();
- STATUS sysPciMappingAdd ();
- #endif /* __STDC__ */
- #ifdef __cplusplus
- }
- #endif
- #endif /* IXP425PCI_H */