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dec21x40End.c：源码内容

(pDrvCtrl->rxLen < pDrvCtrl->rxMaxLen))
dec21x40Recv (pDrvCtrl, pRxD);
if (dec21x40RxDGet (pDrvCtrl) != NULL)
{
pDrvCtrl->rxMaxLen = (TCP_MSS * 30); /* get more packets next time */
netJobAdd ((FUNCPTR)dec21x40RxIntHandle, (int)pDrvCtrl, 0, 0, 0, 0);
}
else
{
pDrvCtrl->rxMaxLen = RWIN;
DEC_CSR_UPDATE (CSR7, CSR7_RIM); /* turn on Rx interrupts */
pDrvCtrl->rxHandling = FALSE;
}
}
/***************************************************************************
*
* dec21x40RxDGet - get a ready receive descriptor
*
* RETURNS: a filled receive descriptor, otherwise NULL.
*/
LOCAL DEC_RD * dec21x40RxDGet
(
DRV_CTRL *pDrvCtrl
)
{
DEC_RD *pRxD = pDrvCtrl->rxRing + pDrvCtrl->rxIndex;
DEC_CACHE_INVALIDATE (pRxD, RD_SIZ);
/* check if the descriptor is owned by the chip */
if (pRxD->rDesc0 & PCISWAP (RDESC0_OWN))
return NULL;
return pRxD;
}
/***************************************************************************
*
* dec21x40TxDGet - get an available transmit descriptor
*
* RETURNS: an available transmit descriptor, otherwise NULL.
*/
LOCAL DEC_TD * dec21x40TxDGet
(
DRV_CTRL *pDrvCtrl
)
{
DEC_TD *pTxD = pDrvCtrl->txRing + pDrvCtrl->txIndex;
DEC_CACHE_INVALIDATE (pTxD, TD_SIZ);
/* check if this descriptor is owned by the chip or is out of bounds */
if ((pTxD->tDesc0 & PCISWAP(TDESC0_OWN)) ||
(((pDrvCtrl->txIndex + 1) % pDrvCtrl->numTds) == pDrvCtrl->txDiIndex))
return (NULL);
return pTxD;
}
/***************************************************************************
*
* dec21x40TxRingClean - clean up processed tx descriptors
*
* This routine processes the transmit queue, freeing all transmitted
* descriptors.
*
* RETURNS: None
*/
LOCAL void dec21x40TxRingClean
(
DRV_CTRL *pDrvCtrl
)
{
DEC_TD *pTxD;
pDrvCtrl->txCleaning = TRUE;
while (pDrvCtrl->txDiIndex != pDrvCtrl->txIndex)
{
pTxD = pDrvCtrl->txRing + pDrvCtrl->txDiIndex;
DEC_CACHE_INVALIDATE (pTxD, TD_SIZ);
if (pTxD->tDesc0 & PCISWAP(TDESC0_OWN))
break;
DRV_LOG (DRV_DEBUG_TX, "Tc:0x%x ", pDrvCtrl->txDiIndex, 0, 0, 0, 0, 0);
/* free the buffer */
if (pDrvCtrl->freeBuf[pDrvCtrl->txDiIndex].pClBuf != NULL)
{
NET_BUF_FREE(pDrvCtrl->freeBuf[pDrvCtrl->txDiIndex].pClBuf);
pDrvCtrl->freeBuf[pDrvCtrl->txDiIndex].pClBuf = NULL;
}
pDrvCtrl->txDiIndex = (pDrvCtrl->txDiIndex + 1) % pDrvCtrl->numTds;
/* clear frame-type of a setup frame and process errors for others */
if (pTxD->tDesc1 & PCISWAP(TDESC1_SET))
{
pTxD->tDesc1 &= PCISWAP(~(TDESC1_SET | TDESC1_FT0));
CACHE_PIPE_FLUSH();
}
else if (pTxD->tDesc0 & PCISWAP(TDESC0_ES))
{
#ifdef INCLUDE_RFC_1213
/* Old RFC 1213 mib2 interface */
END_OBJ *pEndObj = &pDrvCtrl->endObj;
END_ERR_ADD (pEndObj, MIB2_OUT_ERRS, +1);
END_ERR_ADD (pEndObj, MIB2_OUT_UCAST, -1);
#else
/* New RFC 2233 mib2 interface */
if (pDrvCtrl->endObj.pMib2Tbl != NULL)
{
pDrvCtrl->endObj.pMib2Tbl->m2CtrUpdateRtn(pDrvCtrl->endObj.
pMib2Tbl,
M2_ctrId_ifOutErrors,
1);
}
#endif /* INCLUDE_RFC_1213 */
/*
* NOTE: NC and LO TxDesc bits not valid in internal
* loop-back mode (CSR6_OM_IL).
*/
/* we dont have MII phy on a 21145 */
if( (pDrvCtrl->usrFlags & DEC_USR_21145) == 0)
{
if ( !(DEC_CSR_READ(CSR6) & PCISWAP(CSR6_OM_IL)) &&
(pTxD->tDesc0 & PCISWAP(TDESC0_NC|TDESC0_LO)) )
{
/* check for no carrier */
if ((pTxD->tDesc0 & PCISWAP(TDESC0_NC)) &&
!(pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_FD))
{
DRV_LOG (DRV_DEBUG_ALL, "%s%d - no carriern",
(int)DRV_NAME, pDrvCtrl->unit, 0, 0, 0, 0);
}
if ((pTxD->tDesc0 & PCISWAP(TDESC0_LO)) &&
!(pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_FD))
{
DRV_LOG (DRV_DEBUG_ALL, "%s%d - loss of carriern",
(int)DRV_NAME, pDrvCtrl->unit, 0, 0, 0, 0);
}
dec21x40MediaChange (pDrvCtrl);
}
}
/*
* check for link failure (LF)
* NOTE: LF in invalid in HomePNA mode
*/
if ( !(DEC_CSR_READ(CSR6) & PCISWAP(CSR6_OM_IL)) &&
(pTxD->tDesc0 & PCISWAP(TDESC0_LF)) )
{
if((pDrvCtrl->usrFlags & DEC_USR_21145) == 0)
{
DRV_LOG (DRV_DEBUG_ALL, "%s%d - link failn",
(int)DRV_NAME, pDrvCtrl->unit, 0, 0, 0, 0);
dec21x40MediaChange (pDrvCtrl);
}
/* we are a 21145, make sure we are not in HomePNA mode */
else if( (DEC_CSR_READ(CSR13) & CSR13_AUI_TP) == 0)
{
DRV_LOG (DRV_DEBUG_ALL, "%s%d - link failn",
(int)DRV_NAME, pDrvCtrl->unit, 0, 0, 0, 0);
dec21x40MediaChange (pDrvCtrl);
}
else if( pDrvCtrl->usrFlags & DEC_USR_HPNA_PREFER_10BT)
{
/*
* we are in HOMEPNA mode and usr flags are set to
* prefer 10BT so we must
* restart autonegotiation
*/
DEC_CSR_WRITE(CSR12, (DEC_CSR_READ(CSR12) &
~CSR12_AN_MASK) |
CSR12_AN_TX_DISABLED);
}
}
/* restart if DMA underflow is detected */
if (pTxD->tDesc0 & PCISWAP(TDESC0_UF))
{
DRV_LOG (DRV_DEBUG_ALL, "%s%d - fatal DMA underflown",
(int)DRV_NAME, pDrvCtrl->unit, 0, 0, 0, 0);
dec21x40Stop (pDrvCtrl);
pDrvCtrl->txCleaning = FALSE;
netJobAdd ((FUNCPTR)dec21x40Restart, (int)pDrvCtrl, 0, 0, 0, 0);
return;
}
}
#ifdef DRV_DEBUG
{
UINT32 debugStat = pTxD->tDesc0 & PCISWAP (0x0000cf87);
if (debugStat & (PCISWAP(TDESC0_ES |
TDESC0_LF | TDESC0_DE)))
{
decDescErrors++;
}
}
#endif /* DRV_DEBUG */
pTxD->tDesc0 = 0; /* clear errors and stats */
CACHE_PIPE_FLUSH();
}
pDrvCtrl->txCleaning = FALSE;
return;
}
/***************************************************************************
*
* dec21x40Int - handle device interrupts
*
* This interrupt service routine, reads device interrupt status, acknowledges
* the interrupting events, and schedules receive and transmit processing when
* required.
*
* RETURNS: None
*/
LOCAL void dec21x40Int
(
DRV_CTRL * pDrvCtrl
)
{
ULONG status;
CACHE_PIPE_FLUSH();
/* get the status bits and clear the interrupts */
status = DEC_CSR_READ (CSR5);
while (status & (pDrvCtrl->intrMask))
{
DEC_CSR_WRITE (CSR5, status);
DRV_LOG (DRV_DEBUG_INT, "i=0x%x:n", status, 0, 0, 0, 0, 0);
/* Check for autonego/link pass int 21145 */
/* if HPNA_PREFER_10BT is set and */
/* we are in HOME_PNA mode */
if ((status & CSR5_ANC) &&
DRV_FLAGS_ISSET(DEC_21145) &&
(pDrvCtrl->usrFlags & DEC_USR_HPNA_PREFER_10BT) &&
(DEC_CSR_READ(CSR13) & CSR13_AUI_TP))
{
DRV_LOG (DRV_DEBUG_INT, "anc_int: %lxn", DEC_CSR_READ(CSR12),
0, 0, 0, 0, 0);
dec21x40Stop (pDrvCtrl);
netJobAdd ((FUNCPTR)dec21x40Restart, (int)pDrvCtrl, 0, 0, 0, 0);
}
if ((status & CSR5_21040_LNF) &&
DRV_FLAGS_ISSET(DEC_21145) &&
(pDrvCtrl->usrFlags & DEC_USR_HPNA_PREFER_10BT) &&
( (DEC_CSR_READ(CSR13) & CSR13_AUI_TP) == 0))
{
DRV_LOG (DRV_DEBUG_INT, "lnk_fail_int: %lxn", DEC_CSR_READ(CSR12),
0, 0, 0, 0, 0);
dec21x40Stop (pDrvCtrl);
netJobAdd ((FUNCPTR)dec21x40Restart, (int)pDrvCtrl, 0, 0, 0, 0);
}
/* return on false interrupt */
if ((status & (CSR5_NIS | CSR5_AIS)) == 0)
{
DRV_LOG (DRV_DEBUG_INT, "false intrn", 0, 0, 0, 0, 0, 0);
return;
}
/* Check for system error */
if (status & CSR5_SE)
{
DRV_LOG (DRV_DEBUG_INT, "E", 0, 0, 0, 0, 0, 0);
DRV_LOG (DRV_DEBUG_INT, "%s%d - fatal system errorn",
(int)DRV_NAME, pDrvCtrl->unit, 0, 0, 0, 0);
dec21x40Stop (pDrvCtrl);
netJobAdd ((FUNCPTR) dec21x40Restart, (int)pDrvCtrl, 0, 0, 0, 0);
return;
}
/* Handle received packets */
if ((status & CSR5_RI) && (! (status & CSR5_RPS)) &&
(!pDrvCtrl->rxHandling))
{
DRV_LOG (DRV_DEBUG_INT, "r ", 0, 0, 0, 0, 0, 0);
pDrvCtrl->rxHandling = TRUE;
netJobAdd ((FUNCPTR)dec21x40RxIntHandle, (int)pDrvCtrl, 0, 0, 0, 0);
/* disable Rx intr; re-enable in dec21x40RxIntHandle() */
DEC_CSR_RESET (CSR7, CSR7_RIM);
}
#ifdef DRV_DEBUG
if (status & CSR5_TI)
decTxInts++;
if (status & CSR5_RI)
decRxInts++;
if (status & (CSR5_TPS | CSR5_TU | CSR5_TJT | CSR5_UNF))
decTxErrors++;
if (status & (CSR5_RU | CSR5_RPS | CSR5_RWT))
decRxErrors++;
if (status & (CSR5_TPS))
decTxTpsErrors++;
if (status & (CSR5_TU))
decTxBufErrors++;
if (status & (CSR5_TJT))
decTxTjtErrors++;
if (status & (CSR5_UNF))
decTxUnfErrors++;
if (status & (CSR5_RU))
decRxBufErrors++;
if (status & (CSR5_RPS))
decRxRpsErrors++;
if (status & (CSR5_RWT))
decRxWtErrors++;
#endif
/* Cleanup TxRing */
if ((status & CSR5_TI) && (!pDrvCtrl->txCleaning))
{
DRV_LOG (DRV_DEBUG_INT, "t ", 0, 0, 0, 0, 0, 0);
pDrvCtrl->txCleaning = TRUE;
dec21x40TxRingClean (pDrvCtrl);
}
if (_func_dec2114xIntAck != NULL)
{
/*
* Call BSP specific interrupt ack. routine, if defined.
* This must be called after all the interrupt sources
* have been cleared
*/
(* _func_dec2114xIntAck) ();
}
if (pDrvCtrl->txBlocked)
{
pDrvCtrl->txBlocked = FALSE;
netJobAdd ((FUNCPTR)muxTxRestart, (int)&pDrvCtrl->endObj, 0, 0,
0, 0);
}
status = DEC_CSR_READ (CSR5); /* Get more interrupt status bits */
}
return;
}
/***************************************************************************
*
* dec21x40PollStart - starting polling mode
*
* RETURNS: OK, always.
*/
LOCAL STATUS dec21x40PollStart
(
DRV_CTRL * pDrvCtrl
)
{
int intLevel;
DRV_LOG (DRV_DEBUG_POLL, "S ", 0, 0, 0, 0, 0, 0);
intLevel = intLock();
DEC_CSR_RESET (CSR7, CSR7_NIM | CSR7_AIM);
DRV_FLAGS_SET (DEC_POLLING);
intUnlock (intLevel);
return (OK);
}
/***************************************************************************
*
* dec21x40PollStop - stop polling mode
*
* RETURNS: OK, always.
*/
LOCAL STATUS dec21x40PollStop
(
DRV_CTRL * pDrvCtrl
)
{
int intLevel;
intLevel = intLock();
DEC_CSR_UPDATE (CSR7, (CSR7_NIM | CSR7_AIM));
DRV_FLAGS_CLR (DEC_POLLING);
intUnlock (intLevel);
DRV_LOG (DRV_DEBUG_POLL, "s", 0, 0, 0, 0, 0, 0);
return (OK);
}
/***************************************************************************
*
* dec21x40PollSend - send a packet in polled mode
*
* RETURNS: OK on success, EAGAIN on failure
*/
LOCAL STATUS dec21x40PollSend
(
DRV_CTRL * pDrvCtrl,
M_BLK * pMblk
)
{
DEC_TD *pTxD;
char * pBuf;
int len;
pTxD = dec21x40TxDGet (pDrvCtrl);
pBuf = pDrvCtrl->txPollSendBuf;
/* copy and free the MBLK */
len = netMblkToBufCopy (pMblk, pBuf, NULL);
#ifndef INCLUDE_RFC_1213
/* New RFC 2233 mib2 interface */
/* RFC 2233 mib2 counter update for outgoing packet */
if (pDrvCtrl->endObj.pMib2Tbl != NULL)
{
pDrvCtrl->endObj.pMib2Tbl->m2PktCountRtn(pDrvCtrl->endObj.pMib2Tbl,
M2_PACKET_OUT, pBuf, len);
}
#endif /* INCLUDE_RFC_1213 */
pTxD->tDesc2 = PCISWAP (DEC_VIRT_TO_PCI (pBuf));
pTxD->tDesc3 = 0;
/* Associate the data pointer with the MBLK */
/* setup descriptor fields for tansmit */
pTxD->tDesc0 = 0;
pTxD->tDesc1 &= PCISWAP (~TDESC1_TBS1_MSK);
pTxD->tDesc1 |= PCISWAP (TDESC1_TBS1_PUT(len));
pTxD->tDesc0 = PCISWAP(TDESC0_OWN); /* ready for transmit */
CACHE_PIPE_FLUSH();
/* Advance our management index */
pDrvCtrl->txIndex = (pDrvCtrl->txIndex + 1) % pDrvCtrl->numTds;
if (DRV_FLAGS_ISSET(DEC_TX_KICKSTART))
DEC_CSR_WRITE (CSR1, CSR1_TPD);
/* The buffer does not belong to us; Spin until it can be freed */
while (pTxD->tDesc0 & PCISWAP(TDESC0_OWN))
;
/* Try again on transmit errors */
if (pTxD->tDesc0 & PCISWAP(TDESC0_ES))
return (EAGAIN);
return (OK);
}
/***************************************************************************
*
* dec21x40PollReceive - get a packet in polled mode
*
* RETURNS: OK on success, EAGAIN on failure.
*/
LOCAL STATUS dec21x40PollReceive
(
DRV_CTRL *pDrvCtrl,
M_BLK *pMblk
)
{
DEC_RD *pRxD;
char *pRxBuf;
int len;
BOOL gotOne=FALSE;
if ((pMblk->mBlkHdr.mFlags & M_EXT) != M_EXT)
return (EAGAIN);
while (((pRxD = dec21x40RxDGet (pDrvCtrl)) != NULL) && !gotOne)
{
/* Check if the packet was received OK */
if (pRxD->rDesc0 & PCISWAP (RDESC0_ES))
{
/* Update the error statistics and discard the packet */
#ifdef INCLUDE_RFC_1213
/* Old RFC 1213 mib2 interface */
END_ERR_ADD (&pDrvCtrl->endObj, MIB2_IN_ERRS, +1);
#else
/* New RFC 2233 mib2 interface */
if (pDrvCtrl->endObj.pMib2Tbl != NULL)
{
pDrvCtrl->endObj.pMib2Tbl->m2CtrUpdateRtn(pDrvCtrl->endObj.
pMib2Tbl,
M2_ctrId_ifInErrors,
1);
}
#endif /* INCLUDE_RFC_1213 */
}
else
{
len = DEC_FRAME_LEN_GET (PCISWAP(pRxD->rDesc0)) - ETH_CRC_LEN;
if (pMblk->mBlkHdr.mLen >= len)
{
gotOne = TRUE;
#ifdef INCLUDE_RFC_1213
/* Old RFC 1213 mib2 interface */
END_ERR_ADD (&pDrvCtrl->endObj, MIB2_IN_UCAST, +1);
#endif /* INCLUDE_RFC_1213 */
/* Deal with memory alignment */
if (((int) pMblk->mBlkHdr.mData & 0x3) == 0)
pMblk->mBlkHdr.mData += pDrvCtrl->offset;
pMblk->mBlkHdr.mFlags |= M_PKTHDR; /* set the packet header */
pMblk->mBlkHdr.mLen = len; /* set the data len */
pMblk->mBlkPktHdr.len = len; /* set the total len */
pRxBuf = (char *) PCISWAP (pRxD->rDesc3); /* virt address */
#ifndef INCLUDE_RFC_1213
/* RFC 2233 mib2 counter update for incoming packet */
if (pDrvCtrl->endObj.pMib2Tbl != NULL)
{
pDrvCtrl->endObj.pMib2Tbl->m2PktCountRtn(pDrvCtrl->endObj.
pMib2Tbl,
M2_PACKET_IN,
pRxBuf, len);
}
#endif /* INCLUDE_RFC_1213 */
DEC_CACHE_INVALIDATE (pRxBuf, len);
bcopy (pRxBuf, (char *)pMblk->mBlkHdr.mData, len);
}
}
pRxD->rDesc0 = PCISWAP (RDESC0_OWN);
CACHE_PIPE_FLUSH();
pDrvCtrl->rxIndex = (pDrvCtrl->rxIndex + 1) % pDrvCtrl->numRds;
}
return (gotOne ? OK : EAGAIN);
}
/***************************************************************************
*
* dec21x40CsrRead - read a Command and Status Register
*
* RETURNS: contents of the CSR register.
*/
LOCAL ULONG dec21x40CsrRead
(
DRV_CTRL * pDrvCtrl, /* device control */
int reg /* register to read */
)
{
ULONG *csrReg;
ULONG csrData;
csrReg = (ULONG *)(pDrvCtrl->devAdrs + (reg * DECPCI_REG_OFFSET));
csrData = *csrReg;
return REGSWAP(csrData);
}
/***************************************************************************
*
* dec21x40CsrWrite - write a Command and Status Register
*
* RETURNS: None
*/
LOCAL void dec21x40CsrWrite
(
DRV_CTRL * pDrvCtrl, /* device control */
int reg,
ULONG value
)
{
ULONG *csrReg;
csrReg = (ULONG *)(pDrvCtrl->devAdrs + (reg * DECPCI_REG_OFFSET));
*csrReg = REGSWAP (value);
return;
}
/***************************************************************************
*
* dec21040AuiTpInit - initialize either AUI or 10BASE-T connection
*
* This function configures 10BASE-T interface. If the link pass state is
* not achieved within two seconds then the AUI interface is initialized.
*/
LOCAL void dec21040AuiTpInit
(
DRV_CTRL * pDrvCtrl
)
{
/* reset the SIA registers */
DEC_CSR_WRITE (CSR13, 0);
DEC_CSR_WRITE (CSR14, 0);
DEC_CSR_WRITE (CSR15, 0);
/* configure 10BASE-T */
DEC_CSR_WRITE (CSR13, CSR13_CAC_CSR); /* 10BT auto configuration */
taskDelay (sysClkRateGet() * 2); /* 2 second delay */
/* configure AUI if 10BASE-T is not connected */
if (DEC_CSR_READ (CSR12) & (CSR12_21040_LKF | CSR12_21040_NCR))
{
/* reset SIA registers */
DEC_CSR_WRITE (CSR13, 0);
DEC_CSR_WRITE (CSR14, 0);
DEC_CSR_WRITE (CSR15, 0);
/* AUI auto configuration */
DEC_CSR_WRITE (CSR13, (CSR13_AUI_TP | CSR13_CAC_CSR));
}
return;
}
/***************************************************************************
*
* dec21x40EnetAddrGet - gets the ethernet address
*
* This routine gets the ethernet address by calling the appropriate
* EnetAddrGet() routine.
*
* RETURNS: OK/ERROR
*
* SEE ALSO: dec20140EnetAddrGet(), dec21140EnetAddrGet(),
* sysDec21x40EnetAddrGet()
*/
LOCAL STATUS dec21x40EnetAddrGet
(
DRV_CTRL * pDrvCtrl,
char * enetAdrs
)
{
int retVal=ERROR;
if (! DRV_FLAGS_ISSET (DEC_BSP_EADRS))
{
if (DRV_FLAGS_ISSET (DEC_21040))
retVal=dec21040EnetAddrGet (pDrvCtrl, enetAdrs);
else
retVal=dec21140EnetAddrGet (pDrvCtrl, enetAdrs);
}
if (retVal == ERROR)
retVal = sysDec21x40EnetAddrGet (pDrvCtrl->unit, enetAdrs);
return retVal;
}
/***************************************************************************
*
* dec21040EnetAddrGet - gets the ethernet address from the ROM register
*
* This routine gets the ethernet address from the ROM register.
* This routine returns the ethernet address into the pointer supplied to it.
*
* RETURNS: OK/ERROR
*/
LOCAL STATUS dec21040EnetAddrGet
(
DRV_CTRL * pDrvCtrl,
char * enetAdrs /* pointer to the ethernet address */
)
{
FAST ULONG csr9Value; /* register to hold CSR9 */
BOOL eRomReady = FALSE; /* ethernet ROM register state */
int ix; /* index register */
int len = EADDR_LEN;
DEC_CSR_WRITE (CSR9, 0); /* reset rom pointer */
while (len > 0)
{
for (ix = 0; ix < 10; ix++) /* try at least 10 times */
{
if ((csr9Value = DEC_CSR_READ (CSR9)) & CSR9_21040_DNV)
{
eRomReady = FALSE;
DEC_NSDELAY(125);
}
else
{
*enetAdrs++ = (UCHAR) csr9Value;
len--;
eRomReady = TRUE;
break;
}
}
if (!eRomReady)
return (ERROR);
}
return (OK);
}
/***************************************************************************
*
* dec21140EnetAddrGet - gets the ethernet address from the ROM register
*
* This routine reads an ethernet address from the serial ROM. It supports
* legacy, ver 1/A, and 3.0 serial ROM formats.
*
* RETURNS: OK on success, and ERROR if the ethernet address bytes cannot be
* read.
*/
LOCAL STATUS dec21140EnetAddrGet
(
DRV_CTRL * pDrvCtrl,
char * enetAdrs /* pointer to the ethernet address */
)
{
USHORT sromData;
int adrsOffset;
int len;
/* Check if SROM is programmed. */
sromData = dec21140SromWordRead (pDrvCtrl, 0);
if ( sromData == 0xFFFF )
return (ERROR);
sromData = dec21140SromWordRead (pDrvCtrl, 13);
/*
* Set MAC address offset from the ROM format.
* Legacy ROMs have ethernet address start at offset 0,
* while the rest (ver 1/A and 3.0) have it at byte offset 20.
*/
adrsOffset = ((sromData == 0xAA55) ||
(sromData == 0xFFFF)) ? 0: 10;
for (len=EADDR_LEN; len; len-=2, adrsOffset++)
{
sromData = dec21140SromWordRead (pDrvCtrl, adrsOffset);
/* byte swap it for little endian */
sromData = LE_BYTE_SWAP(sromData);
*enetAdrs++ = MSB(sromData);
*enetAdrs++ = LSB(sromData);
}
return (OK);
}
/***************************************************************************
*
* dec21140SromWordRead - read two bytes from the serial ROM
*
* This routine returns the two bytes of information that is associated
* with it the specified ROM line number. This will later be used by the
* dec21140GetEthernetAdr function. It can also be used to
* review the ROM contents itself.
* The function must first send some initial bit patterns to the CSR9 that
* contains the Serial ROM Control bits. Then the line index into the ROM
* is evaluated bit-by-bit to program the ROM. The 2 bytes of data
* are extracted and processed into a normal pair of bytes.
*
* RETURNS: Value from ROM or ERROR.
*/
USHORT dec21140SromWordRead
(
DRV_CTRL * pDrvCtrl,
UCHAR lineCnt /* Serial ROM line Number */
)
{
int ix; /* index register */
int loop; /* address loop counter */
ULONG adrsBase;
USHORT romData;
/* Is the line offset valid, and if so, how large is it */
if (lineCnt > DEC21140_SROM_SIZE)
return (ERROR);
if (lineCnt < 64)
{
loop = 6;
lineCnt = lineCnt << 2; /* Prepare lineCnt for processing */
}
else
loop = 8;
/* Command the Serial ROM to the correct Line */
/* Preamble */
DEC_SROM_CMD_WRITE (0x0, 30); /* Command 1 */
DEC_SROM_CMD_WRITE (0x1, 50); /* Command 2 */
DEC_SROM_CMD_WRITE (0x3, 250); /* Command 3 */
DEC_SROM_CMD_WRITE (0x1, 150); /* Command 4 */
/* Command Phase */
DEC_SROM_CMD_WRITE (0x5, 150); /* Command 5 */
DEC_SROM_CMD_WRITE (0x7, 250); /* Command 6 */
DEC_SROM_CMD_WRITE (0x5, 250); /* Command 7 */
DEC_SROM_CMD_WRITE (0x7, 250); /* Command 8 */
DEC_SROM_CMD_WRITE (0x5, 100); /* Command 9 */
DEC_SROM_CMD_WRITE (0x1, 150); /* Command 10 */
DEC_SROM_CMD_WRITE (0x3, 250); /* Command 11 */
DEC_SROM_CMD_WRITE (0x1, 100); /* Command 12 */
/* Address Phase */
for (ix=0; ix < loop; ix++)
{
adrsBase = ((lineCnt & 0x80) >> 5);
/* Write the command */
DEC_SROM_CMD_WRITE (adrsBase | 0x1, 150); /* Command 13 */
DEC_SROM_CMD_WRITE (adrsBase | 0x3, 250); /* Command 14 */
DEC_SROM_CMD_WRITE (adrsBase | 0x1, 100); /* Command 15 */
lineCnt = lineCnt<<1;
}
DEC_NSDELAY (150);
/* Data Phase */
romData = 0;
for (ix=15; ix >= 0; ix--)
{
/* Write the command */
DEC_SROM_CMD_WRITE (0x3, 100); /* Command 16 */
/* Extract data */
romData |= (DEC_SROM_CMD_READ() << ix);
DEC_NSDELAY (150); /* Command 17 */
DEC_SROM_CMD_WRITE (0x1, 250); /* Command 18 */
}
/* Finish up command */
DEC_SROM_CMD_WRITE (0x0, 100); /* Command 19 */
return (PCISWAP_SHORT(romData));
}
/***************************************************************************
*
* dec21x40ChipReset - reset the chip and setup CSR0 register
*
* This routine stops the transmitter and receiver, masks all interrupts, then
* resets the ethernet chip. Once the device comes out of the reset state, it
* initializes CSR0 register.
*
* RETURNS: OK, or ERROR if a new TxD could not be obtained.
*/
LOCAL STATUS dec21x40ChipReset
(
DRV_CTRL * pDrvCtrl /* pointer to device control structure */
)
{
ULONG usrFlags=pDrvCtrl->usrFlags;
ULONG csr0Val=0x0;
DEC_TD * pTxD;
char * pBuf;
pTxD = dec21x40TxDGet (pDrvCtrl);
pBuf = NET_BUF_ALLOC ();
if ((pTxD == NULL) || (pBuf == NULL))
{
if (pBuf)
NET_BUF_FREE (pBuf);
return ERROR;
}
/*
* "Kick" the dec21143 chip on startup to handle a dec21143
* known problem. Note the "kicking" will not hurt the dec21140
* but seems to hurt the 21145.
*/
/* setup the transmit buffer pointers */
pTxD->tDesc2 = PCISWAP (DEC_VIRT_TO_PCI (pBuf));
pTxD->tDesc3 = 0;
/* setup frame len */
pTxD->tDesc1 &= PCISWAP (~TDESC1_TBS1_MSK);
pTxD->tDesc1 |= PCISWAP (TDESC1_TBS1_PUT(4));
/* transfer ownership to device */
pTxD->tDesc0 = PCISWAP(TDESC0_OWN);
/* Flush the write pipe */
CACHE_PIPE_FLUSH();
/*
* start xmit dummy packet, this will never go
* out to the physical bus
*/
DEC_CSR_WRITE (CSR4, DEC_VIRT_TO_PCI((ULONG)pTxD));
DEC_CSR_WRITE (CSR7, 0);
DEC_CSR_WRITE (CSR6, CSR6_21140_MB1 |
CSR6_21140_TTM |
CSR6_21140_SF |
CSR6_21140_PS |
CSR6_ST |
CSR6_OM_IL);
DEC_CSR_WRITE (CSR1, CSR1_TPD ); /* xmit poll demand */
CACHE_PIPE_FLUSH ();
/* We're done "kicking" */
DEC_NSDELAY (0x2000);
/*
* Reset the device while xmitting, it ensures the device will not hang
* up in its 1st xmit later on
*/
DEC_CSR_WRITE (CSR0, DEC_CSR_READ (CSR0) | CSR0_SWR);
CACHE_PIPE_FLUSH ();
/* Re-claim buffer(s) */
pTxD->tDesc0 = 0;
NET_BUF_FREE(pBuf);
taskDelay (sysClkRateGet() / 2);
DEC_CSR_WRITE (CSR6, 0); /* stop rcvr & xmitter */
DEC_CSR_WRITE (CSR7, 0); /* mask interrupts */
DEC_CSR_WRITE (CSR0, CSR0_SWR);
CACHE_PIPE_FLUSH ();
/* Wait Loop, Loop for at least 50 PCI cycles according to chip spec */
DEC_NSDELAY (1000);
/* Decode user setting into CSR0 bits */
csr0Val |= (usrFlags & DEC_USR_BAR_RX)? 0 : CSR0_BAR;
csr0Val |= (usrFlags & DEC_USR_BE)? CSR0_BLE : 0;
csr0Val |= (usrFlags & DEC_USR_TAP_MSK) << DEC_USR_TAP_SHF;
csr0Val |= (usrFlags & DEC_USR_PBL_MSK) << DEC_USR_PBL_SHF;
csr0Val |= (usrFlags & DEC_USR_RML)? CSR0_21140_RML : 0;
if (usrFlags & DEC_USR_CAL_MSK)
csr0Val |= (usrFlags & DEC_USR_CAL_MSK) << DEC_USR_CAL_SHF;
else
{
csr0Val &= ~(CSR0_CAL_MSK | CSR0_PBL_MSK);
csr0Val |= (CSR0_CAL_32 | CSR0_PBL_32);
}
if (! (usrFlags & DEC_USR_TAP_MSK))
DRV_FLAGS_SET (DEC_TX_KICKSTART);
DEC_CSR_WRITE (CSR0, csr0Val);
CACHE_PIPE_FLUSH ();
DEC_NSDELAY (1000);
return (OK);
}
/***************************************************************************
*
* dec21140MediaInit - Initailize media information
*
*/
LOCAL STATUS dec21140MediaInit
(
DRV_CTRL * pDrvCtrl,
UCHAR * pSromData
)
{
USHORT * pSromWord = (USHORT *)pSromData;
UCHAR * pInfoLeaf0;
UCHAR ix;
/* read the serial ROM into pSromData */
for (ix=0; ix<DEC21140_SROM_WORDS; ix++)
*pSromWord++ = dec21140SromWordRead (pDrvCtrl, ix);
/* Initialize the media summary */
if (pDrvCtrl->mediaCount == 0xFF)
{
/* check version */
if (SROM_VERSION( pSromData ) < DEC21140_SROM_VERSION_3)
return (ERROR);
/* get the leaf offset */
pInfoLeaf0 = pSromData + SROM_ILEAF0_OFFSET( pSromData );
pDrvCtrl->gprModeVal = ILEAF_GPR_MODE( pInfoLeaf0 );
pDrvCtrl->mediaCount = ILEAF_MEDIA_COUNT( pInfoLeaf0 );
pDrvCtrl->mediaCurrent = 0xFF;
pDrvCtrl->mediaDefault = 0xFF;
DRV_LOG (DRV_DEBUG_LOAD,
"gpMask=0x%x mediaCount = 0x%dn",
pDrvCtrl->gprModeVal, pDrvCtrl->mediaCount, 0, 0, 0, 0);
}
return (OK);
}
/***************************************************************************
*
* dec21x40MiiRead - read a PHY device register via MII
*
* RETURNS: the contents of a PHY device register in retVal arg, OK always
*/
LOCAL STATUS dec21x40MiiRead
(
DRV_CTRL *pDrvCtrl,
UINT8 phyAdrs, /* PHY address to access */
UINT8 phyReg, /* PHY register to read */
UINT16 *pRetVal
)
{
/* Write 34-bit preamble */
DEC_MII_WRITE (MII_PREAMBLE, 32);
DEC_MII_WRITE (MII_PREAMBLE, 2);
/* start of frame + op-code nibble */
DEC_MII_WRITE ((MII_SOF | MII_RD), 4);
/* device address */
DEC_MII_WRITE (phyAdrs, 5);
DEC_MII_WRITE (phyReg, 5);
/* turn around */
DEC_MII_RTRISTATE;
/* read data */
DEC_MII_READ (pRetVal, 16);
return OK;
}
/***************************************************************************
*
* dec21x40MiiWrite - write to a PHY device register via MII
*
* RETURNS: OK, always
*/
LOCAL STATUS dec21x40MiiWrite
(
DRV_CTRL *pDrvCtrl,
UINT8 phyAdrs, /* PHY address to access */
UINT8 phyReg, /* PHY register to write */
UINT16 data /* Data to write */
)
{
/* write 34-bit preamble */
DEC_MII_WRITE (MII_PREAMBLE, 32);
DEC_MII_WRITE (MII_PREAMBLE, 2);
/* start of frame + op-code nibble */
DEC_MII_WRITE (MII_SOF | MII_WR, 4);
/* device address */
DEC_MII_WRITE (phyAdrs, 5);
DEC_MII_WRITE (phyReg, 5);
/* turn around */
DEC_MII_WTRISTATE;
/* write data */
DEC_MII_WRITE (data, 16);
return OK;
}
/***************************************************************************
*
* dec21x40PhyFind - Find the first PHY connected to DEC MII port.
*
* RETURNS: Address of PHY or 0xFF if not found.
*/
UINT8 dec21x40PhyFind
(
DRV_CTRL *pDrvCtrl
)
{
UINT16 miiData;
UINT8 phyAddr;
for (phyAddr = 0; phyAddr < (UINT8)DEC_MAX_PHY; phyAddr++)
{
dec21x40MiiRead(pDrvCtrl, phyAddr, MII_PHY_ID0, &miiData);
/* Verify PHY address read */
if ((miiData != 0xFFFF) && (miiData != 0)) /* Found PHY */
{
DRV_LOG (DRV_DEBUG_LOAD, "PHY @ %#xn", phyAddr, 0,0,0,0,0);
return (phyAddr);
}
}
DRV_LOG (DRV_DEBUG_INIT, "No PHY foundn", 0,0,0,0,0,0);
return (0xFF);
}
/***************************************************************************
*
* dec21140MediaSelect - select the current media
*
* RETURNS: OK, always
*/
LOCAL STATUS dec21140MediaSelect
(
DRV_CTRL * pDrvCtrl,
UINT * pCsr6Val
)
{
UCHAR sromData[128];
UCHAR * pInfoLeaf0;
UCHAR * pInfoBlock;
UINT8 ix;
if (dec21140MediaInit (pDrvCtrl, sromData) == ERROR)
return (ERROR);
/* Get Info Leaf 0 */
pInfoLeaf0 = sromData + SROM_ILEAF0_OFFSET (sromData);
/* Get the current media */
if ((pDrvCtrl->mediaCurrent == 0) ||
(pDrvCtrl->mediaCurrent >= pDrvCtrl->mediaCount))
pDrvCtrl->mediaCurrent = pDrvCtrl->mediaCount - 1;
else
pDrvCtrl->mediaCurrent --;
/* Seek to the correct media Info Block */
pInfoBlock = ILEAF_INFO_BLK0( pInfoLeaf0);
for (ix=0; ix<pDrvCtrl->mediaCurrent; ix++)
{
if (IBLK_IS_COMPACT (pInfoBlock))
pInfoBlock += IBLK_COMPACT_SIZE;
else
pInfoBlock += IBLK_EXT_SIZE (pInfoBlock) + 1;
}
/* Convert ext0 into compact */
if (IBLK_IS_EXT0 (pInfoBlock))
pInfoBlock = IBLK_EXT0_TO_COMPACT (pInfoBlock);
/* Setup the GP port */
DEC_CSR_WRITE (CSR12, CSR12_21140_GPC | pDrvCtrl->gprModeVal);
DEC_NSDELAY (150);
if (IBLK_IS_COMPACT (pInfoBlock))
{
USHORT compactCmd;
DRV_LOG ( DRV_DEBUG_LOAD,
"COMPACT: mediaCode=0x%x gpData=0x%x command=0x%xn",
IBLK_COMPACT_MCODE( pInfoBlock ),
IBLK_COMPACT_GPDATA( pInfoBlock ),
IBLK_COMPACT_CMD( pInfoBlock ), 0, 0, 0);
/* Initialize the PHY interface */
DEC_CSR_WRITE (CSR12, IBLK_COMPACT_GPDATA(pInfoBlock));
DEC_NSDELAY(150);
/* Get CSR6 settings */
compactCmd = IBLK_COMPACT_CMD( pInfoBlock );
if (compactCmd & COMPACT_CMD_SCR)
*pCsr6Val |= CSR6_21140_SCR;
if (compactCmd & COMPACT_CMD_PCS)
*pCsr6Val |= CSR6_21140_PCS;
if (compactCmd & COMPACT_CMD_PS)
*pCsr6Val |= CSR6_21140_PS;
}
else
{
UCHAR * pGpStr;
DRV_LOG (DRV_DEBUG_LOAD,
"EXT1: PHY#=0x%x InitLen=0x%x resetLen=0x%x n",
IBLK_EXT1_PHY(pInfoBlock),
IBLK_EXT1_INIT_LEN(pInfoBlock),
IBLK_EXT1_RESET_LEN(pInfoBlock), 0, 0, 0);
DRV_LOG (DRV_DEBUG_LOAD,
"mediaCap=0x%x autoAd=0x%x FDMap=0x%x TTMmap=0x%xn",
IBLK_EXT1_MEDIA_CAP(pInfoBlock),
IBLK_EXT1_AUTO_AD(pInfoBlock),
IBLK_EXT1_FD_MAP(pInfoBlock),
IBLK_EXT1_TTM_MAP(pInfoBlock), 0, 0);
/* Reset the media */
pGpStr = IBLK_EXT1_RESET_STR (pInfoBlock);
for (ix=IBLK_EXT1_RESET_LEN(pInfoBlock); ix; ix--, pGpStr++)
DEC_CSR_WRITE (CSR12, *pGpStr);
DEC_NSDELAY(150);
/* if there's an MII-compliant PHY */
if (IBLK_IS_EXT1 (pInfoBlock))
{
DRV_LOG (DRV_DEBUG_LOAD, "PHY compliant devicen",
0,0,0,0,0,0);
if (dec21x40MiiInit (pDrvCtrl, pCsr6Val, pInfoBlock) == ERROR)
return (ERROR);
}
}
return (OK);
}
/***************************************************************************
*
* dec21143MediaInit - Initialize media information
*
* This routine initializes media information for dec21143 chip.
*
* RETURNS: OK or ERROR
*/
LOCAL STATUS dec21143MediaInit
(
DRV_CTRL * pDrvCtrl,
UCHAR * pSromData
)
{
USHORT * pSromWord = (USHORT *)pSromData;
UCHAR * pInfoLeaf0;
UCHAR ix;
/* read the serial ROM into pSromData */
for (ix=0; ix < DEC21140_SROM_WORDS; ix++)
*pSromWord++ = dec21140SromWordRead (pDrvCtrl, ix);
/* Initialize the media summary */
if (pDrvCtrl->mediaCount == 0xFF)
{
/* check version */
if (SROM_VERSION( pSromData ) < DEC21140_SROM_VERSION_3)
{
DRV_LOG (DRV_DEBUG_LOAD,
"dec21143MediaInit: incorrect SROM version %d (expected >= %d",
SROM_VERSION (pSromData), DEC21140_SROM_VERSION_3, 0,0,0,0);
return (ERROR);
}
/* get the leaf offset */
pInfoLeaf0 = pSromData + SROM_ILEAF0_OFFSET(pSromData);
pDrvCtrl->mediaCount = ILEAF_21143_MEDIA_COUNT(pInfoLeaf0);
pDrvCtrl->mediaCurrent = 0xFF;
pDrvCtrl->mediaDefault = 0xFF;
DRV_LOG (DRV_DEBUG_LOAD, "mediaCount = %dn",
pDrvCtrl->mediaCount, 0, 0, 0, 0, 0);
}
return (OK);
}
/***************************************************************************
*
* dec21143MediaSelect - select the current media for dec21143
*
* This routine reads and sets up physical media with configuration
* information from a Version 3 DEC Serial ROM. Any other media configuration
* can be supported by initializing <_func_dec21x40MediaSelect>.
*
* RETURN: OK or ERROR
*/
LOCAL STATUS dec21143MediaSelect
(
DRV_CTRL * pDrvCtrl,
UINT * pCsr6Val
)
{
UCHAR sromData[128];
UCHAR * pInfoLeaf0;
UCHAR * pInfoBlock;
UINT mediaCmd;
UINT8 ix;
UINT32 csr15Val;
if (dec21143MediaInit (pDrvCtrl, sromData) == ERROR)
return (ERROR);
/* Get Info Leaf 0 */
pInfoLeaf0 = sromData + SROM_ILEAF0_OFFSET (sromData);
/* Get the current media */
if ((pDrvCtrl->mediaCurrent == 0) ||
(pDrvCtrl->mediaCurrent >= pDrvCtrl->mediaCount))
pDrvCtrl->mediaCurrent = pDrvCtrl->mediaCount - 1;
else
pDrvCtrl->mediaCurrent --;
DRV_LOG (DRV_DEBUG_LOAD, "dec21143MediaSelect trying %dn",
pDrvCtrl->mediaCurrent, 0, 0, 0, 0, 0);
/* Seek to the correct media Info Block */
pInfoBlock = ILEAF_21143_INFO_BLK0( pInfoLeaf0);
for (ix=0; ix < pDrvCtrl->mediaCurrent; ix++)
pInfoBlock += IBLK_EXT_SIZE (pInfoBlock) + 1;
if (IBLK_IS_EXT(pInfoBlock))
{
switch (IBLK_EXT_TYPE(pInfoBlock))
{
case IBLK_IS_EXT2 : /* Extended format block - type 2 */
DEC_CSR_WRITE (CSR6, 0);
DEC_CSR_WRITE (CSR0, CSR0_SWR);
DEC_NSDELAY(150);
*pCsr6Val &= ~CSR6_21140_PS;
DRV_LOG ( DRV_DEBUG_LOAD, "EXT2: mediaCode=%#x EXT=%#xn",
IBLK_EXT2_MCODE(pInfoBlock),
IBLK_EXT2_EXT(pInfoBlock), 0, 0, 0, 0);
DRV_LOG ( DRV_DEBUG_LOAD, "GP Ctrl=%#x GP Data=%#xn",
IBLK_EXT2_GPC(pInfoBlock),
IBLK_EXT2_GPD(pInfoBlock), 0, 0, 0, 0);
/* get Media-specific data */
if (IBLK_EXT2_EXT(pInfoBlock))
{
DRV_LOG (DRV_DEBUG_LOAD,
"CSR13=%#x CSR14=%#x CSR15=%#xn",
IBLK_EXT2_MSD_CSR13(pInfoBlock),
IBLK_EXT2_MSD_CSR14(pInfoBlock),
IBLK_EXT2_MSD_CSR15(pInfoBlock), 0, 0, 0);
DEC_CSR_WRITE (CSR15, (IBLK_EXT2_GPC(pInfoBlock) << 16) |
IBLK_EXT2_MSD_CSR15(pInfoBlock));
DEC_CSR_WRITE (CSR15, (IBLK_EXT2_GPD(pInfoBlock) << 16) |
IBLK_EXT2_MSD_CSR15(pInfoBlock));
DEC_CSR_WRITE (CSR14, IBLK_EXT2_MSD_CSR14(pInfoBlock));
DEC_CSR_WRITE (CSR13, IBLK_EXT2_MSD_CSR13(pInfoBlock));
}
else
{
/* setup the GP port */
csr15Val = 0; /* OR'd into GPC/GPD values */
DEC_CSR_WRITE (CSR13, 0);
switch (IBLK_EXT2_MCODE(pInfoBlock))
{
case EXT2_MEDIA_10TP:
DRV_LOG (DRV_DEBUG_LOAD, "EXT2: 10TPn",
0,0,0,0,0,0);
DEC_CSR_WRITE (CSR14, CSR14_SPP | CSR14_APE |
CSR14_LTE | CSR14_SQE | CSR14_CLD |
CSR14_CSQ | CSR14_RSQ |
CSR14_CPEN_HP |
CSR14_CPEN_DM | CSR14_LSE |
CSR14_DREN | CSR14_LBK | CSR14_ECEN);
DEC_CSR_WRITE (CSR13, CSR13_SRL_SIA);
break;
case EXT2_MEDIA_BNC:
DRV_LOG (DRV_DEBUG_LOAD, "EXT2: BNCn",0,0,0,0,0,0);
DEC_CSR_WRITE (CSR14, CSR14_ECEN | CSR14_DREN |
CSR14_CLD | CSR14_CSQ | CSR14_RSQ);
DEC_CSR_WRITE (CSR13, CSR13_SRL_SIA | CSR13_AUI_TP);
break;
case EXT2_MEDIA_AUI:
DRV_LOG (DRV_DEBUG_LOAD, "EXT2: AUIn",0,0,0,0,0,0);
DEC_CSR_WRITE (CSR14, CSR14_ECEN | CSR14_DREN |
CSR14_CLD | CSR14_CSQ | CSR14_RSQ);
csr15Val = CSR15_21143_ABM;
DEC_CSR_WRITE (CSR13, CSR13_SRL_SIA | CSR13_AUI_TP);
break;
case EXT2_MEDIA_10FD:
DRV_LOG (DRV_DEBUG_LOAD, "EXT2: 10FDn",
0,0,0,0,0,0);
DEC_CSR_WRITE (CSR14, CSR14_SPP | CSR14_APE |
CSR14_LTE | CSR14_SQE | CSR14_CLD |
CSR14_CSQ | CSR14_RSQ |
CSR14_CPEN_NC |
CSR14_LSE | CSR14_DREN | CSR14_ECEN);
DEC_CSR_WRITE (CSR13, CSR13_SRL_SIA);
break;
default:
DRV_LOG (DRV_DEBUG_LOAD, "EXT2: UNKn",0,0,0,0,0,0);
break;
}
DEC_CSR_WRITE (CSR15, (IBLK_EXT2_GPC(pInfoBlock) << 16) |
csr15Val);
DEC_CSR_WRITE (CSR15, (IBLK_EXT2_GPD(pInfoBlock) << 16) |
csr15Val);
}
DEC_NSDELAY(150);
break;
case IBLK_IS_EXT3 : /* Extended format block - type 3 */
DRV_LOG (DRV_DEBUG_LOAD,
"EXT3: PHY#=%#x InitLen=%#x resetLen=%#x n",
IBLK_EXT3_PHY(pInfoBlock),
IBLK_EXT3_INIT_LEN(pInfoBlock),
IBLK_EXT3_RESET_LEN(pInfoBlock), 0, 0, 0);
DRV_LOG (DRV_DEBUG_LOAD,
"mediaCap=%#x autoAd=%#x FDMap=%#x"
"TTMmap=%#x MIIci=%#xn",
IBLK_EXT3_MEDIA_CAP(pInfoBlock),
IBLK_EXT3_AUTO_AD(pInfoBlock),
IBLK_EXT3_FD_MAP(pInfoBlock),
IBLK_EXT3_TTM_MAP(pInfoBlock),
IBLK_EXT3_MII_CI(pInfoBlock), 0);
if (dec21x40MiiInit (pDrvCtrl, pCsr6Val, pInfoBlock) == ERROR)
return (ERROR);
break;
case IBLK_IS_EXT4 : /* Extended format block - type 4 */
DRV_LOG ( DRV_DEBUG_LOAD,
"EXT4: mediaCode=%#x GPCtrl=%#x GPData=%#x Cmd=%#xn",
IBLK_EXT4_MCODE(pInfoBlock),
IBLK_EXT4_GPC(pInfoBlock),
IBLK_EXT4_GPD(pInfoBlock),
IBLK_EXT4_CMD(pInfoBlock), 0, 0);
/* setup the GP port */
DEC_CSR_WRITE (CSR15, IBLK_EXT4_GPC(pInfoBlock) << 16);
DEC_CSR_WRITE (CSR15, IBLK_EXT4_GPD(pInfoBlock) << 16);
DEC_NSDELAY(150);
/* Get CSR6 settings */
mediaCmd = IBLK_EXT4_CMD(pInfoBlock);
/* *pCsr6Val = 0; */
if (mediaCmd & IBLK_EXT4_CMD_PS)
*pCsr6Val |= CSR6_21140_PS;
if (mediaCmd & IBLK_EXT4_CMD_TTM)
*pCsr6Val |= CSR6_21140_TTM;
if (mediaCmd & IBLK_EXT4_CMD_PCS)
*pCsr6Val |= CSR6_21140_PCS;
if (mediaCmd & IBLK_EXT4_CMD_SCR)
*pCsr6Val |= CSR6_21140_SCR;
if (IBLK_EXT4_MCODE(pInfoBlock) == 3)
{
/* Half duplex, 100BaseTx */
*pCsr6Val &= ~(CSR6_FD);
}
else if (IBLK_EXT4_MCODE(pInfoBlock) == 5)
{
/* Full duplex, 100BaseTx */
*pCsr6Val |= CSR6_FD;
}
else
{
DRV_LOG (DRV_DEBUG_INIT, "Unsupported media coden",
0,0,0,0,0,0);
}
break;
case IBLK_IS_EXT5 : /* Extended format block - type 5 */
DRV_LOG ( DRV_DEBUG_LOAD, "EXT5: Rst Seq length=%#xn",
IBLK_EXT5_RESET_LEN(pInfoBlock), 0, 0, 0, 0, 0);
/* Reset the media */
/* not implemented */
break;
default :
return (ERROR);
}
}
else
{
return (ERROR);
}
DRV_LOG (DRV_DEBUG_LOAD, "CSR6 = %#08xn", *pCsr6Val, 0,0,0,0,0);
return (OK);
}
/***************************************************************************
*
* dec21145SPIStart - Setup HomePNA SPI port
*
* RETURNS: nothing
*/
LOCAL void dec21145SPIStart
(
DRV_CTRL * pDrvCtrl /* pointer to DRV_CTRL structure */
)
{
/* Clear SPI Chip Select to HomePNA Phy, and all other SPI bits */
DEC_CSR_RESET (CSR9, CSR9_21145_SPI_MSK);
/* SPI Chip Select the HomePNA PHY, set output to zero */
DEC_CSR_UPDATE (CSR9, CSR9_21145_SPI_CS);
}
/***************************************************************************
*
* dec21145SPIStop - Reset HomePNA SPI port
*
* RETURNS: nothing
*/
LOCAL void dec21145SPIStop
(
DRV_CTRL * pDrvCtrl /* pointer to DRV_CTRL structure */
)
{
/* Clear SPI Chip Select to HomePNA Phy, and all other SPI bits */
DEC_CSR_RESET (CSR9, CSR9_21145_SPI_MSK);
/* SPI Chip Select the HomePNA PHY, set output to zero */
DEC_CSR_UPDATE (CSR9, CSR9_21145_SPI_CLK);
}
/***************************************************************************
*
* dec21145SPIByteTransfer - transfer a byte over the HomePNA SPI port
*
* This routine writes and, as a result also, reads a byte of data to/from
* the SPI port. This routine is generally used to write/read registers on the
* HomePNA PHY.
*
* RETURNS: byte value read from SPI port
*/
LOCAL UCHAR dec21145SPIByteTransfer
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
UCHAR WriteData
)
{
int i;
UCHAR ReadData = 0;
for (i=7; i>=0; i--)
{
/* falling edge clock */
DEC_CSR_RESET (CSR9, CSR9_21145_SPI_CLK);
/* read data coming out of PHY */
if(DEC_CSR_READ(CSR9) & CSR9_21145_SPI_DO)
ReadData |= (0x1<<i);
if(WriteData & (0x1<<i))
/* set Phy input to a ONE */
DEC_CSR_UPDATE(CSR9, CSR9_21145_SPI_DI);
else
/* set Phy input to a ZERO */
DEC_CSR_RESET (CSR9, CSR9_21145_SPI_DI);
/* rising edge clock, write the Phy input out */
DEC_CSR_UPDATE(CSR9, CSR9_21145_SPI_CLK);
}
return ReadData;
}
#ifdef DRV_DEBUG
/***************************************************************************
*
* dec21145SPIReadBack - Read all PHY registers out
*
* RETURNS: nothing
*/
void dec21145SPIReadBack
(
DRV_CTRL * pDrvCtrl /* pointer to DRV_CTRL structure */
)
{
int i;
/* read back the PHY registers */
for(i=0; i<0x20; i++)
{
dec21145SPIStart(pDrvCtrl);
/* output HomePNA SPI read opcode */
dec21145SPIByteTransfer(pDrvCtrl, (UCHAR) PNA_SPI_OPCODE_READ);
/* output HomePNA Phy register index */
dec21145SPIByteTransfer(pDrvCtrl, i);
/* read HomePNA Phy register data */
DRV_LOG (DRV_DEBUG_LOAD, "Read PNA Phy Reg %x: %xn",
i,dec21145SPIByteTransfer(pDrvCtrl,0x0),0,0,0,0);
dec21145SPIStop(pDrvCtrl);
}
}
#endif /* DRV_DEBUG */
/***************************************************************************
*
* dec21145HomePNAInit - initialize the chip and PHY to use the HomePNA interface
*
* This routine initializes the chip and PHY to use the HomePNA interface.
*
* RETURNS: OK, or ERROR
*/
LOCAL STATUS dec21145HomePNAInit
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
UINT * pCsr6Val
)
{
int i = 0;
int j = 0;
int regValue;
char WriteableHRRegisters[]={0x00, 0x01, 0x04, 0x05, 0x08, 0x09,
0x0A, 0x0B, 0x10, 0x12, 0x13,
0x14, 0x15, 0x19, 0x1A, 0x1C, 0x1D,
0x1E, 0x1F, -1};
if(pDrvCtrl->pHomePNAPhyInfo == NULL)
{
printf("HomePNAInit: No Ext7 PHY parameters found in SROMn");
exit(ERROR);
}
else
{
/* Get clocks going to the HomePNA Phy */
#if 0
/* hard code analog control values from datasheet */
DEC_CSR_WRITE(CSR13, (0x708a<<16) | CSR13_AUI_TP
| CSR13_SRL_SIA);
#endif
/* use analog control values from srom */
DEC_CSR_WRITE(CSR13, ((pDrvCtrl->pHomePNAPhyInfo->sp_csr13)<<16) |
CSR13_AUI_TP);
/* make sure the Phy is not going to be powered down */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][0] &=
~PHA_PHY_CTRL_LOW_PDN;
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][1]= 1;
/* force the HomePNA speed if user flags are set */
if(pDrvCtrl->usrFlags & DEC_USR_HPNA_FORCE_SLOW)
{
/* force slow speed mode - 0.7 MB/sec */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][0] &=
~PHA_PHY_CTRL_LOW_HS;
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][1]= 1;
}
else if (pDrvCtrl->usrFlags & DEC_USR_HPNA_FORCE_FAST)
{
/* force high speed mode - 1 MB/sec */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][0] |=
PHA_PHY_CTRL_LOW_HS;
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][1]= 1;
}
/* force the HomePNA power if user flags are set */
if(pDrvCtrl->usrFlags & DEC_USR_HPNA_FORCE_LOW_PWR)
{
/* force low power mode */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][0] &=
~PHA_PHY_CTRL_LOW_HP;
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][1]= 1;
}
else if (pDrvCtrl->usrFlags & DEC_USR_HPNA_FORCE_HI_PWR)
{
/* force high power mode */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][0] |=
PHA_PHY_CTRL_LOW_HP;
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][1]= 1;
}
/* ZERO out CSR9!! This must happen or we wont be able to talk SPI */
DEC_CSR_WRITE (CSR9, 0);
/* output HomePNA SPI latch write enable opcode */
dec21145SPIStart(pDrvCtrl);
dec21145SPIByteTransfer(pDrvCtrl, (UCHAR) PNA_SPI_OPCODE_SET_WE);
dec21145SPIStop(pDrvCtrl);
/* initialize the PHY registers */
for(i=0,j=0; (j != -1) && (j<0x20); j=WriteableHRRegisters[i++] )
{
if(j != -1)
{
DRV_LOG(DRV_DEBUG_LOAD, "phy reg %x: %x updated %xrn",
j, pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[j][0],
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[j][1], 4,5,6);
/* did we need to update it? */
if( pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[j][1] == 1)
{
/* output HomePNA SPI write opcode */
dec21145SPIStart(pDrvCtrl);
dec21145SPIByteTransfer(pDrvCtrl,
(UCHAR) PNA_SPI_OPCODE_WRITE);
/* output HomePNA Phy register index */
dec21145SPIByteTransfer(pDrvCtrl, j);
/* output HomePNA Phy register data */
regValue = pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[j][0];
DRV_LOG(DRV_DEBUG_LOAD, "Writing reg %x: %xrn",
j, regValue,3,4,5,6);
dec21145SPIByteTransfer(pDrvCtrl, regValue);
dec21145SPIStop(pDrvCtrl);
}
}
}
#ifdef DRV_DEBUG
dec21145SPIReadBack(pDrvCtrl);
#endif
/* output HomePNA SPI latch clear write enable opcode */
dec21145SPIStart(pDrvCtrl);
dec21145SPIByteTransfer(pDrvCtrl, (UCHAR) PNA_SPI_OPCODE_CLEAR_WE);
dec21145SPIStop(pDrvCtrl);
}
/* reset the SIA and wait 5ms */
DEC_CSR_WRITE(CSR13, ((pDrvCtrl->pHomePNAPhyInfo->sp_csr13)<<16) |
CSR13_SRL_SIA );
taskDelay((sysClkRateGet() / 200) + 2);
/* enable collison detect, receive squelch, decoder/encoder */
DEC_CSR_WRITE(CSR14, CSR14_CLD | CSR14_RSQ | CSR14_DREN | CSR14_ECEN);
/* enable 10-BT autonegotitation when the usr flag is set */
if(pDrvCtrl->usrFlags & DEC_USR_HPNA_PREFER_10BT)
DEC_CSR_UPDATE(CSR14, CSR14_21143_TAS | CSR14_SPP | CSR14_APE |
CSR14_LTE | CSR14_21143_ANE | CSR14_CPEN_NC |
CSR14_LSE | CSR14_21143_TH );
/* disable receive watchdog, and jabber timer*/
DEC_CSR_WRITE(CSR15, CSR15_21143_RWD | CSR15_JBD);
DEC_CSR_WRITE(CSR13, ((pDrvCtrl->pHomePNAPhyInfo->sp_csr13)<<16) |
CSR13_AUI_TP | CSR13_SRL_SIA);
return (OK);
}
/***************************************************************************
*
* dec21145DecodeExt7InfoBlock - Decode and load HomePNA Phy defaults from SROM
*
* This routine decodes an EXT7 record from the SROM containing the
* HomePNA PHY register defaults. This routine load up the pHomePNAPhyInfo
* structure with the values it finds in the SROM.
*
* RETURNS: OK or ERROR if decoding fails
*/
LOCAL STATUS dec21145DecodeExt7InfoBlock
(
DRV_CTRL * pDrvCtrl,
UCHAR * pInfoBlock /* ptr to infoBlock */
)
{
UCHAR iy;
UCHAR tmpExt7ExtraIndex;
UCHAR tmpExt7ExtraData;
/* assume decode failure */
pDrvCtrl->homePNAPhyValuesFound = FALSE;
if(IBLK_EXT_TYPE(pInfoBlock) == 0x07)
{
/* get memory for the HomePNAphyInfo structure */
if ((pDrvCtrl->pHomePNAPhyInfo =
calloc (sizeof (HOMEPNA_PHY_INFO), 1)) == NULL)
return(ERROR);
pDrvCtrl->pHomePNAPhyInfo->sp_csr13 =
IBLK_EXT7_ANALOG_CTRL(pInfoBlock);
DRV_LOG ( DRV_DEBUG_LOAD, "EXT7: analog_ctrl 0x%xn",
IBLK_EXT7_ANALOG_CTRL(pInfoBlock),2,3,4,5,6);
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][0] =
IBLK_EXT7_CTRL_LOW(pInfoBlock);
/* flag this register for update in the phy init */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_LOW][1] = 1;
DRV_LOG ( DRV_DEBUG_LOAD, "EXT7: ctrl_low 0x%xn",
IBLK_EXT7_CTRL_LOW(pInfoBlock),2,3,4,5,6);
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_HI][0] =
IBLK_EXT7_CTRL_HI(pInfoBlock);
/* flag this register for update in the phy init */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_CTRL_HI][1] =1;
DRV_LOG ( DRV_DEBUG_LOAD, "EXT7: ctrl_hi 0x%xn",
IBLK_EXT7_CTRL_HI(pInfoBlock),2,3,4,5,6);
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_NOISE][0] =
IBLK_EXT7_NOISE(pInfoBlock);
/* flag this register for update in the phy init */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_NOISE][1] = 1;
DRV_LOG ( DRV_DEBUG_LOAD, "EXT7: noise 0x%xn",
IBLK_EXT7_NOISE(pInfoBlock),2,3,4,5,6);
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_NSE_FLOOR][0] =
IBLK_EXT7_NSE_FLOOR(pInfoBlock);
/* flag this register for update in the phy init */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_NSE_FLOOR][1] = 1;
DRV_LOG ( DRV_DEBUG_LOAD, "EXT7: floor 0x%xn",
IBLK_EXT7_NSE_FLOOR(pInfoBlock),2,3,4,5,6);
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_NSE_CEILING][0] =
IBLK_EXT7_NSE_CEILING(pInfoBlock);
/* flag this register for update in the phy init */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_NSE_CEILING][1] =1;
DRV_LOG ( DRV_DEBUG_LOAD, "EXT7: ceiling 0x%xn",
IBLK_EXT7_NSE_CEILING(pInfoBlock),2,3,4,5,6);
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_NSE_ATTACK][0] =
IBLK_EXT7_NSE_ATTACK(pInfoBlock);
/* flag this register for update in the phy init */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs[PNA_PHY_NSE_ATTACK][1] =1;
DRV_LOG ( DRV_DEBUG_LOAD, "EXT7: attack 0x%xn",
IBLK_EXT7_NSE_ATTACK(pInfoBlock),2,3,4,5,6);
if( IBLK_EXT_SIZE(pInfoBlock) > 11)
/* additional fields */
{
if((IBLK_EXT_SIZE(pInfoBlock) & 0x1) != 0x1)
{
for(iy=10; iy < IBLK_EXT_SIZE(pInfoBlock); iy += 2)
{
tmpExt7ExtraIndex =
IBLK_EXT7_EXTRA_INDEX(pInfoBlock + iy);
tmpExt7ExtraData =
IBLK_EXT7_EXTRA_DATA(pInfoBlock + iy);
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs [tmpExt7ExtraIndex][0]=
tmpExt7ExtraData;
/* flag this register for update in the phy init */
pDrvCtrl->pHomePNAPhyInfo->pna_phy_regs [tmpExt7ExtraIndex][1]=1;
DRV_LOG ( DRV_DEBUG_LOAD,
"EXT7: Extra index 0x%x data 0x%xn",
tmpExt7ExtraIndex, tmpExt7ExtraData,3,4,5,6);
}
}
else
{
DRV_LOG( DRV_DEBUG_LOAD, "Invalid SROM Ext7 formatn",
1,2,3,4,5,6);
return (ERROR);
}
}
/* we decoded everything ok! */
pDrvCtrl->homePNAPhyValuesFound = TRUE;
}
else
{
/* no EXT7 type found */
DRV_LOG( DRV_DEBUG_LOAD, "Not an Ext7 Info Blockn",
1,2,3,4,5,6);
return(ERROR);
}
return (OK);
}
/***************************************************************************
*
* dec21145FindHomePNAPhyValues - find HomePNA Phy defaults from SROM
*
* This routine searches the SROM for HomePNA defaults.
*
* HomePNA PHY register defaults. This routine load up the pHomePNAPhyInfo
* structure with the values it finds in the SROM.
*
* RETURNS: OK or ERROR if decoding fails
*/
LOCAL STATUS dec21145FindHomePNAPhyValues
(
DRV_CTRL * pDrvCtrl,
UCHAR * infoBlockPtrs[] /* array of ptr to infoBlocks */
)
{
UCHAR ix;
for(ix=0; ix< pDrvCtrl->mediaCount; ix++)
{
if(IBLK_EXT_TYPE(infoBlockPtrs[ix]) == 0x07)
{
dec21145DecodeExt7InfoBlock(pDrvCtrl, infoBlockPtrs[ix]);
/* keep searching until we found some good values */
if(pDrvCtrl->homePNAPhyValuesFound == TRUE)
return (OK);
}
}
return (ERROR);
}
/***************************************************************************
*
* dec21145MediaInit - Initialize media information
*
* This routine initializes media information for dec21145 chip.
*
* RETURNS: OK or ERROR
*/
LOCAL STATUS dec21145MediaInit
(
DRV_CTRL * pDrvCtrl,
UCHAR * pSromData
)
{
USHORT * pSromWord = (USHORT *)pSromData;
UCHAR * pInfoLeaf0;
UCHAR ix;
DRV_LOG (DRV_DEBUG_LOAD, "dec21145MediaInitn",
pDrvCtrl->mediaCount, 0, 0, 0, 0, 0);
/* read the serial ROM into pSromData */
for (ix=0; ix < DEC21140_SROM_WORDS; ix++)
*pSromWord++ = dec21140SromWordRead (pDrvCtrl, ix);
/* Initialize the media summary */
if (pDrvCtrl->mediaCount == 0xFF)
{
/* check version */
if (SROM_VERSION( pSromData ) < DEC21140_SROM_VERSION_4)
{
DRV_LOG (DRV_DEBUG_LOAD,
"dec21145MediaInit: unsupport SROM versionn",
pDrvCtrl->mediaCount, 0, 0, 0, 0, 0);
return (ERROR);
}
/* get the leaf offset */
pInfoLeaf0 = pSromData + SROM_ILEAF0_OFFSET(pSromData);
pDrvCtrl->mediaCount = ILEAF_21145_MEDIA_COUNT(pInfoLeaf0);
pDrvCtrl->mediaCurrent = 0xFF;
pDrvCtrl->mediaDefault = 0xFF;
DRV_LOG (DRV_DEBUG_LOAD, "mediaCount = %dn",
pDrvCtrl->mediaCount, 0, 0, 0, 0, 0);
}
return (OK);
}
/***************************************************************************
*
* dec21145MediaSelect - select the current media for dec21143
*
* This routine reads and sets up physical media with configuration
* information from a Version 4 Intel/DEC Serial ROM. Any other
* media configuration can be supported by initializing
* <_func_dec21x40MediaSelect>.
*
* RETURN: OK or ERROR
*/
LOCAL STATUS dec21145MediaSelect
(
DRV_CTRL * pDrvCtrl,
UINT * pCsr6Val
)
{
UCHAR sromData[128];
UCHAR * pInfoLeaf0;
UCHAR * pInfoBlock;
UINT mediaCmd;
UCHAR * infoBlockPtrs[10];
BOOL mediaOK;
int ix;
pDrvCtrl->pHomePNAPhyInfo = NULL;
mediaOK = FALSE;
DRV_LOG (DRV_DEBUG_LOAD, " dec21145MediaSelectn", 0, 0, 0, 0, 0, 0);
if (dec21145MediaInit (pDrvCtrl, sromData) == ERROR)
return (ERROR);
/* Get Info Leaf 0 */
pInfoLeaf0 = sromData + SROM_ILEAF0_OFFSET (sromData);
/* Get the current media */
if ((pDrvCtrl->mediaCurrent == 0) ||
(pDrvCtrl->mediaCurrent >= pDrvCtrl->mediaCount))
pDrvCtrl->mediaCurrent = pDrvCtrl->mediaCount - 1;
else
pDrvCtrl->mediaCurrent --;
pInfoBlock = ILEAF_21145_INFO_BLK0( pInfoLeaf0);
infoBlockPtrs[0] = pInfoBlock;
for (ix=0; ix < pDrvCtrl->mediaCurrent; ix++)
{
pInfoBlock += IBLK_EXT_SIZE (pInfoBlock) + 1;
infoBlockPtrs[ix+1] = pInfoBlock;
}
/* Media fallback loop */
do
{
DRV_LOG (DRV_DEBUG_LOAD, " dec21145MediaSelect media current %dn",
pDrvCtrl->mediaCurrent, 0, 0, 0, 0, 0);
pInfoBlock = infoBlockPtrs[pDrvCtrl->mediaCurrent];
if (IBLK_IS_EXT(pInfoBlock))
{
DRV_LOG (DRV_DEBUG_LOAD, " dec21145MediaSelect media is EXTn",
0, 0, 0, 0, 0, 0);
/* Seek to the correct media Info Block */
switch (IBLK_EXT_TYPE(pInfoBlock))
{
case IBLK_IS_EXT2 : /* Extended format block - type 2 */
DRV_LOG ( DRV_DEBUG_LOAD, "EXT2: mediaCode=%#x EXT=%#xn",
IBLK_EXT2_MCODE(pInfoBlock),
IBLK_EXT2_EXT(pInfoBlock), 0, 0, 0, 0);
/* make sure we use 10BASE-T/HomePNA port */
*pCsr6Val &= ~CSR6_21140_PS;
/* get Media-specific data */
if (IBLK_EXT2_EXT(pInfoBlock))
{
DRV_LOG (DRV_DEBUG_LOAD,
"CSR13=%#x CSR14=%#x CSR15=%#xn",
IBLK_EXT2_MSD_CSR13(pInfoBlock),
IBLK_EXT2_MSD_CSR13(pInfoBlock),
IBLK_EXT2_MSD_CSR13(pInfoBlock), 0, 0, 0);
DEC_CSR_WRITE (CSR13, IBLK_EXT2_MSD_CSR13(pInfoBlock));
DEC_CSR_WRITE (CSR14, IBLK_EXT2_MSD_CSR13(pInfoBlock));
DEC_CSR_WRITE (CSR15, IBLK_EXT2_MSD_CSR13(pInfoBlock));
}
/* setup the GP port */
DRV_LOG ( DRV_DEBUG_LOAD, "GP Ctrl=%#x GP Data=%#xn",
IBLK_EXT2_GPC(pInfoBlock),
IBLK_EXT2_GPD(pInfoBlock), 0, 0, 0, 0);
DEC_CSR_UPDATE(CSR15, IBLK_EXT2_GPC(pInfoBlock) << 8);
DEC_CSR_UPDATE(CSR15, IBLK_EXT2_GPD(pInfoBlock) << 8);
DEC_NSDELAY(500);
/* see if we want to setup for HomePNA */
switch (IBLK_EXT2_MCODE(pInfoBlock))
{
case EXT2_MEDIA_10TP:
DRV_LOG ( DRV_DEBUG_LOAD, "EXT2: Media 10Base-Tn",
1,2,3,4,5,6);
/* enable collison detect, receive squelch, decoder/encoder */
DEC_CSR_WRITE(CSR14, CSR14_CLD | CSR14_RSQ |
CSR14_DREN | CSR14_ECEN);
DEC_CSR_UPDATE(CSR14, CSR14_21143_TAS | CSR14_SPP |
CSR14_APE | CSR14_LTE | CSR14_SQE |
CSR14_21143_ANE | CSR14_CPEN_NC |
CSR14_LSE | CSR14_21143_TH );
/* disable receive watchdog, and jabber timer*/
DEC_CSR_WRITE(CSR15, 0);
DEC_CSR_WRITE(CSR13,
((pDrvCtrl->pHomePNAPhyInfo->sp_csr13)
<<16) |
CSR13_SRL_SIA);
*pCsr6Val &= ~CSR6_FD;
mediaOK = TRUE;
/* if we fail, go back to the higher priority link */
pDrvCtrl->mediaCurrent = 0xff;
break;
case EXT2_MEDIA_10FD:
DRV_LOG (DRV_DEBUG_LOAD,
"EXT2: Media 10Base-T Full Duplexn",
1,2,3,4,5,6);
/*
* enable collison detect, receive squelch,
* decoder/encoder
*/
DEC_CSR_WRITE(CSR14, CSR14_CLD | CSR14_RSQ |
CSR14_DREN | CSR14_ECEN);
DEC_CSR_UPDATE(CSR14, CSR14_21143_TAS | CSR14_SPP |
CSR14_APE | CSR14_LTE | CSR14_SQE |
CSR14_21143_ANE | CSR14_CPEN_NC |
CSR14_LSE | CSR14_21143_TH );
/* disable receive watchdog, and jabber timer*/
DEC_CSR_WRITE(CSR15, 0);
DEC_CSR_WRITE(CSR13,
((pDrvCtrl->pHomePNAPhyInfo->sp_csr13)
<<16) |
CSR13_SRL_SIA);
*pCsr6Val |= CSR6_FD;
mediaOK = TRUE;
/* if we fail, go back to the higher priority link */
pDrvCtrl->mediaCurrent = 0xff;
break;
case EXT2_MEDIA_HOMEPNA:
DRV_LOG ( DRV_DEBUG_LOAD, "EXT2: Media HomePNAn",
1,2,3,4,5,6);
/*
* HomePNA operates at half duplex and
* Heartbeat disabled
*/
*pCsr6Val &= ~CSR6_FD;
*pCsr6Val |= CSR6_21140_HBD;
/* set TX treshold */
*pCsr6Val |= CSR6_THR_096;
/*
* see if we can find PNA PHY values in SROM
* as type EXT7
*/
if(pDrvCtrl->homePNAPhyValuesFound == FALSE)
{
if(dec21145FindHomePNAPhyValues(pDrvCtrl,
infoBlockPtrs )
== ERROR)
{
DRV_LOG ( DRV_DEBUG_LOAD,
"EXT2: Media HomePNA No Phy Values"
"Foundn",
1,2,3,4,5,6);
/*
* attach BSP hook here to provide
* PNA PHY defaults
*/
return(ERROR);
}
}
if(dec21145HomePNAInit ( pDrvCtrl, pCsr6Val) == ERROR)
return (ERROR);
/* we have determined this is the media we are using */
mediaOK = TRUE;
break;
}
break;
case IBLK_IS_EXT3 : /* Extended format block - type 3 */
DRV_LOG (DRV_DEBUG_LOAD,
"EXT3: PHY#=%#x InitLen=%#x resetLen=%#x n",
IBLK_EXT3_PHY(pInfoBlock),
IBLK_EXT3_INIT_LEN(pInfoBlock),
IBLK_EXT3_RESET_LEN(pInfoBlock), 0, 0, 0);
DRV_LOG (DRV_DEBUG_LOAD,
"mediaCap=%#x autoAd=%#x FDMap=%#x"
"TTMmap=%#x MIIci=%#xn",
IBLK_EXT3_MEDIA_CAP(pInfoBlock),
IBLK_EXT3_AUTO_AD(pInfoBlock),
IBLK_EXT3_FD_MAP(pInfoBlock),
IBLK_EXT3_TTM_MAP(pInfoBlock),
IBLK_EXT3_MII_CI(pInfoBlock), 0);
if (dec21x40MiiInit (pDrvCtrl, pCsr6Val, pInfoBlock) == ERROR)
return (ERROR);
break;
case IBLK_IS_EXT4 : /* Extended format block - type 4 */
DRV_LOG (DRV_DEBUG_LOAD,
"EXT4: mediaCode=%#x GPCtrl=%#x GPData=%#x Cmd=%#xn",
IBLK_EXT4_MCODE(pInfoBlock),
IBLK_EXT4_GPC(pInfoBlock),
IBLK_EXT4_GPD(pInfoBlock),
IBLK_EXT4_CMD(pInfoBlock), 0, 0);
/* setup the GP port */
DEC_CSR_UPDATE (CSR15, IBLK_EXT4_GPC(pInfoBlock) << 8);
DEC_CSR_UPDATE (CSR15, IBLK_EXT4_GPD(pInfoBlock) << 8);
DEC_NSDELAY(150);
/* Get CSR6 settings */
mediaCmd = IBLK_EXT4_CMD(pInfoBlock);
if (mediaCmd & IBLK_EXT4_CMD_PS)
*pCsr6Val |= CSR6_21140_PS;
if (mediaCmd & IBLK_EXT4_CMD_TTM)
*pCsr6Val |= CSR6_21140_TTM;
if (mediaCmd & IBLK_EXT4_CMD_PCS)
*pCsr6Val |= CSR6_21140_PCS;
if (mediaCmd & IBLK_EXT4_CMD_SCR)
*pCsr6Val |= CSR6_21140_SCR;
break;
case IBLK_IS_EXT5 : /* Extended format block - type 5 */
DRV_LOG ( DRV_DEBUG_LOAD, "EXT5: Rst Seq length=%#xn",
IBLK_EXT5_RESET_LEN(pInfoBlock), 0, 0, 0, 0, 0);
/* Reset the media */
/* not implemented */
pDrvCtrl->mediaCurrent--;
break;
case IBLK_IS_EXT7 : /* Extended format block - type 7 */
DRV_LOG ( DRV_DEBUG_LOAD, "EXT7:n", 0, 0, 0, 0, 0, 0);
if( dec21145DecodeExt7InfoBlock(pDrvCtrl, pInfoBlock) == ERROR)
{
DRV_LOG ( DRV_DEBUG_LOAD,
"dec21145DecodeExt7InfoBlock return ERRORn",
0, 0, 0, 0, 0, 0);
return (ERROR);
}
pDrvCtrl->mediaCurrent--;
mediaOK = FALSE;
break;
default :
DRV_LOG ( DRV_DEBUG_LOAD, "Unknown EXT SROM Type %dn",
IBLK_EXT_TYPE(pInfoBlock), 0, 0, 0, 0, 0);
return (ERROR);
break;
}
}
else
{
DRV_LOG ( DRV_DEBUG_LOAD,
"No EXT types found in SROM:n", 0, 0, 0, 0, 0, 0);
return (ERROR);
}
} while (mediaOK == FALSE);
return (OK);
}
/***************************************************************************
*
* dec21x40MiiInit - initialize the chip to use the MII interface
*
* This routine initializes the chip to use the MII interface.
*
* RETURNS: OK, or ERROR
*/
LOCAL STATUS dec21x40MiiInit
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
UINT * pCsr6Val, /* pointer to location for new CSR6 value */
UCHAR * pInfoBlock /* SROM info block for this MII leaf */
)
{
/* initialize some fields in the PHY info structure */
if (dec21x40PhyPreInit (pDrvCtrl, pInfoBlock) != OK)
{
DRV_LOG (DRV_DEBUG_LOAD, ("Failed to pre-initialize PHYn"),
0, 0, 0, 0, 0, 0);
return (ERROR);
}
if (miiPhyInit (pDrvCtrl->pPhyInfo) != OK)
{
DRV_LOG (DRV_DEBUG_LOAD, "Failed to initialise PHYn", 0,0,0,0,0,0);
return (ERROR);
}
*pCsr6Val |= (CSR6_21140_HBD | CSR6_21140_PS);
/* deal with full duplex mode and speed */
if (pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_FD)
{
*pCsr6Val |= CSR6_FD;
DRV_LOG (DRV_DEBUG_LOAD, "In full duplex moden", 0,0,0,0,0,0);
}
else
{
DRV_LOG (DRV_DEBUG_LOAD, "In half duplex moden", 0,0,0,0,0,0);
}
if (pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_100)
{
*pCsr6Val &= ~CSR6_21140_TTM;
DRV_LOG (DRV_DEBUG_LOAD, "In 100Mbps moden", 0,0,0,0,0,0);
}
else
{
*pCsr6Val |= CSR6_21140_TTM;
DRV_LOG (DRV_DEBUG_LOAD, "In 10Mbps moden", 0,0,0,0,0,0);
}
return (OK);
}
/***************************************************************************
*
* dec21x40PhyPreInit - initialize some fields in the phy info structure
*
* This routine initializes some fields in the phy info structure,
* for use of the phyInit() routine.
*
* RETURNS: OK, or ERROR if could not obtain memory.
*/
LOCAL STATUS dec21x40PhyPreInit
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
UCHAR * pInfoBlock /* pointer to SROM info block for this leaf */
)
{
PHY_INFO * pPhyInfo = NULL;
/* get memory for the phyInfo structure */
if ((pDrvCtrl->pPhyInfo = calloc (sizeof (PHY_INFO), 1)) == NULL)
return (ERROR);
pPhyInfo = pDrvCtrl->pPhyInfo;
/* set some default values */
pDrvCtrl->pPhyInfo->pDrvCtrl = (void *) pDrvCtrl;
pDrvCtrl->pPhyInfo->phyAnOrderTbl = pDrvCtrl->pMiiPhyTbl;
if (pDrvCtrl->phyAddr == ((UINT8) 0xFF))
{
/* Default is to take the value from the SROM */
if (IBLK_IS_EXT1 (pInfoBlock))
{
pDrvCtrl->pPhyInfo->phyAddr = IBLK_EXT1_PHY(pInfoBlock);
}
else
{
pDrvCtrl->pPhyInfo->phyAddr = IBLK_EXT3_PHY(pInfoBlock);
}
}
else
{
/*
* Take the value specified in the load string assuming the user
* knows best...
*/
pDrvCtrl->pPhyInfo->phyAddr = pDrvCtrl->phyAddr;
}
/*
* in case of link failure, set a default mode for the PHY
* if we intend to use a different media, this flag should
* be cleared
*/
pDrvCtrl->pPhyInfo->phyFlags |= MII_PHY_DEF_SET;
pDrvCtrl->pPhyInfo->phyWriteRtn = (FUNCPTR) dec21x40MiiWrite;
pDrvCtrl->pPhyInfo->phyReadRtn = (FUNCPTR) dec21x40MiiRead;
pDrvCtrl->pPhyInfo->phyLinkDownRtn = (FUNCPTR) dec21x40MediaChange;
pDrvCtrl->pPhyInfo->phyDelayRtn = (FUNCPTR) taskDelay;
pDrvCtrl->pPhyInfo->phyMaxDelay = (sysClkRateGet() * 5);
pDrvCtrl->pPhyInfo->phyDelayParm = max (1, sysClkRateGet()/60);
/* in case the cable is not there, leave the PHY ready to auto-negotiate */
pDrvCtrl->pPhyInfo->phyDefMode = PHY_AN_ENABLE;
/* handle some user-to-physical flags */
if (!(DRV_PHY_FLAGS_ISSET (DEC_USR_MII_NO_AN)))
MII_PHY_FLAGS_SET (MII_PHY_AUTO);
else
MII_PHY_FLAGS_CLEAR (MII_PHY_AUTO);
if (DRV_PHY_FLAGS_ISSET (DEC_USR_MII_AN_TBL))
MII_PHY_FLAGS_SET (MII_PHY_TBL);
else
MII_PHY_FLAGS_CLEAR (MII_PHY_TBL);
if (DRV_PHY_FLAGS_ISSET (DEC_USR_MII_100MB))
MII_PHY_FLAGS_SET (MII_PHY_100);
else
MII_PHY_FLAGS_CLEAR (MII_PHY_100);
if (DRV_PHY_FLAGS_ISSET (DEC_USR_MII_FD))
MII_PHY_FLAGS_SET (MII_PHY_FD);
else
MII_PHY_FLAGS_CLEAR (MII_PHY_FD);
if (DRV_PHY_FLAGS_ISSET (DEC_USR_MII_10MB))
MII_PHY_FLAGS_SET (MII_PHY_10);
else
MII_PHY_FLAGS_CLEAR (MII_PHY_10);
if (DRV_PHY_FLAGS_ISSET (DEC_USR_MII_HD))
MII_PHY_FLAGS_SET (MII_PHY_HD);
else
MII_PHY_FLAGS_CLEAR (MII_PHY_HD);
if (DRV_PHY_FLAGS_ISSET (DEC_USR_MII_BUS_MON))
MII_PHY_FLAGS_SET (MII_PHY_MONITOR);
else
MII_PHY_FLAGS_CLEAR (MII_PHY_MONITOR);
/* mark it as pre-initilized */
MII_PHY_FLAGS_SET (MII_PHY_PRE_INIT);
DRV_LOG (DRV_DEBUG_LOAD, ("dec21x40PhyPreInit pPhyInfo = 0x%x read=0x%x "
"write=0x%x tbl=0x%x addr=0x%x "
"flags=0x%x n"),
(int) pDrvCtrl->pPhyInfo,
(int) pDrvCtrl->pPhyInfo->phyReadRtn,
(int) pDrvCtrl->pPhyInfo->phyWriteRtn,
(int) pDrvCtrl->pPhyInfo->phyAnOrderTbl,
(int) pDrvCtrl->pPhyInfo->phyAddr,
(int) pDrvCtrl->pPhyInfo->phyFlags);
return (OK);
}
#ifdef DRV_DEBUG
void decPoolShow
(
int inst /* instance number, starting at 0 */
)
{
DRV_CTRL *pDrvCtrl = (DRV_CTRL *)endFindByName ("dc", inst);
netPoolShow (pDrvCtrl->endObj.pNetPool);
}
void decCsrShow
(
int inst /* instance number, starting at 0 */
)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
if (pDrvCtrl != NULL)
{
printf ("n");
printf ("CSR0t 0x%xn", (int) dec21x40CsrRead(pDrvCtrl, CSR0));
printf ("CSR1t 0x%xn", (int) dec21x40CsrRead(pDrvCtrl, CSR1));
printf ("CSR2t 0x%xn", (int) dec21x40CsrRead(pDrvCtrl, CSR2));
printf ("CSR3t 0x%xn", (int) dec21x40CsrRead(pDrvCtrl, CSR3));
printf ("CSR4t 0x%xn", (int) dec21x40CsrRead(pDrvCtrl, CSR4));
printf ("CSR5t 0x%xn", (int) dec21x40CsrRead(pDrvCtrl, CSR5));
printf ("CSR6t 0x%xn", (int) dec21x40CsrRead(pDrvCtrl, CSR6));
printf ("CSR7t 0x%xn", (int) dec21x40CsrRead(pDrvCtrl, CSR7));
printf ("CSR8t 0x%xn", (int) dec21x40CsrRead(pDrvCtrl, CSR8));
printf ("CSR9t 0x%xn", (int) dec21x40CsrRead(pDrvCtrl, CSR9));
printf ("CSR10t 0x%xn",(int) dec21x40CsrRead(pDrvCtrl, CSR10));
printf ("CSR11t 0x%xn",(int) dec21x40CsrRead(pDrvCtrl, CSR11));
printf ("CSR12t 0x%xn",(int) dec21x40CsrRead(pDrvCtrl, CSR12));
printf ("CSR13t 0x%xn",(int) dec21x40CsrRead(pDrvCtrl, CSR13));
printf ("CSR14t 0x%xn",(int) dec21x40CsrRead(pDrvCtrl, CSR14));
printf ("CSR15t 0x%xn",(int) dec21x40CsrRead(pDrvCtrl, CSR15));
}
}
void decCsrWrite
(
UINT inst,
UINT csr,
UINT value
)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
DEC_CSR_WRITE (csr, value);
}
void decTxDShow
(
int inst,
int numTxD
)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
DEC_TD *pTxD = &pDrvCtrl->txRing[numTxD];
printf ("txd[%d] at 0x%x:n", numTxD, (int)pTxD);
printf ("tDesc0=0x%x tDesc1=0x%x tDesc2=0x%x tDesc3=0x%xn",
(int) PCISWAP (pTxD->tDesc0), (int) PCISWAP (pTxD->tDesc1),
(int) PCISWAP (pTxD->tDesc2), (int) PCISWAP (pTxD->tDesc3));
}
void decRxDShow
(
int inst,
int numRxD
)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
DEC_TD *pTxD = &pDrvCtrl->txRing[numRxD];
printf ("rxd[%d] at 0x%x:n", numRxD, (int)pTxD);
printf ("tDesc0=0x%x tDesc1=0x%x tDesc2=0x%x tDesc3=0x%xn",
(int) PCISWAP (pTxD->tDesc0), (int) PCISWAP (pTxD->tDesc1),
(int) PCISWAP (pTxD->tDesc2), (int) PCISWAP (pTxD->tDesc3));
}
void decShow
(
int inst
)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
printf ("pDrvCtrl=0x%x txNum=%d txIndex=%d txDiIndex=%dn",
(int) pDrvCtrl,
pDrvCtrl->numTds,
pDrvCtrl->txIndex,
pDrvCtrl->txDiIndex);
printf ("rxNum=%d rxIndex=%dn",
pDrvCtrl->numRds,
pDrvCtrl->rxIndex);
}
int eAdrsDisplay
(
UINT8 *pAddr
)
{
printf ("EtherAddr=%x:%x:%x:%x:%x:%xn",
pAddr[0], pAddr[1], pAddr[2], pAddr[3], pAddr[4], pAddr[5]);
return 0;
}
void mcAdd (int inst, char *eAddr)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
dec21x40MCastAddrAdd (pDrvCtrl, eAddr);
}
void mcDel (int inst, char *eAddr)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
dec21x40MCastAddrDel (pDrvCtrl, eAddr);
}
void mcShow (int inst)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
ETHER_MULTI *pMCastNode;
pMCastNode = END_MULTI_LST_FIRST (&pDrvCtrl->endObj);
while (pMCastNode != NULL)
{
eAdrsDisplay (pMCastNode->addr);
pMCastNode = END_MULTI_LST_NEXT (pMCastNode);
}
}
char decSerialRom[128];
void decSerialRomUpload (int inst)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
int count;
USHORT *pSerialRom = (USHORT *)decSerialRom;
bzero (decSerialRom, 128);
for (count=0; count<64; count++)
*pSerialRom++ = dec21140SromWordRead (pDrvCtrl, count);
}
int decReset(int inst)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
dec21x40Stop (pDrvCtrl);
taskDelay (max (2, sysClkRateGet()/30));
netJobAdd ((FUNCPTR)dec21x40Restart, (int)pDrvCtrl, 0, 0, 0, 0);
return 0;
}
short decMiiRead (int inst, int phyAddr, int reg)
{
int retStat;
short miiData = 0;
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
retStat = dec21x40MiiRead(pDrvCtrl, phyAddr, reg, &miiData);
return (miiData);
}
int decMiiWrite (int inst, int phyAddr, int reg, short miiData)
{
DRV_CTRL * pDrvCtrl = (DRV_CTRL *) endFindByName ("dc", inst);
return (dec21x40MiiWrite (pDrvCtrl, phyAddr, reg, miiData));
}
#endif /* DC_DEBUG */