VxWorks

开发平台：

C/C++

gei82543End.c：源码内容

}
if (frameAccept != TRUE)
{
DRV_LOG (DRV_DEBUG_POLL_RX, "Packet Error 0x%xn", rxdErr,
2, 3, 4, 5, 6);
LOGMSG("Packet error 0x%x n",rxdErr, 2, 3, 4, 5, 6);
goto errorExit;
}
}
}
#endif /* INCLUDE_TBI_COMPATIBLE */
len -= RX_CRC_LEN;
len &= ~0xc000;
if (len > (pDrvCtrl->mtu + GEI_DEFAULT_ETHERHEADER) ||
len < MIN_ETHER_PACKET_SIZE)
{
DRV_LOG (DRV_DEBUG_POLL_RX, "invalid packet length=0x%x!n",
len, 0, 0, 0, 0, 0);
retVal = EAGAIN;
goto errorExit;
}
/* upper layer must provide a valid buffer. */
if (pMblk->mBlkHdr.mLen < len)
{
DRV_LOG (DRV_DEBUG_POLL_RX, "invalid mbuf length=0x%x!n",
pMblk->mBlkHdr.mLen, 0, 0, 0, 0, 0);
retVal = EAGAIN;
goto errorExit;
}
/* get the packet address */
GEI_READ_DESC_LONG(pRxDesc, RXDESC_BUFADRLOW_OFFSET, bufAddr);
pCluster = GEI_BUS_TO_VIRT(bufAddr);
if ((*pCluster ) & (UINT8) 0x01)
pDrvCtrl->end.mib2Tbl.ifInNUcastPkts += 1;
else
END_ERR_ADD (&pDrvCtrl->end, MIB2_IN_UCAST, +1);
/* cache coherence */
END_CACHE_INVALIDATE ((UINT32)pCluster, len);
/* process device packet into net buffer */
bcopy (pCluster, pMblk->m_data, len);
pMblk->mBlkHdr.mFlags |= M_PKTHDR; /* set the packet header */
pMblk->mBlkHdr.mLen = len; /* set the data len */
pMblk->mBlkPktHdr.len = len; /* set the total len */
DRV_LOG (DRV_DEBUG_POLL_RX, "gei82543EndPollRcv...Donen", 1, 2, 3,
4, 5, 6);
errorExit:
gei82543RxDesUpdate(pDrvCtrl, NULL);
return (retVal);
}
/*************************************************************************
*
* gei82543EndPollSend - routine to send a packet in polling mode.
*
* This routine send a packet in polling mode
*
* RETURNS: OK or ERROR
*/
LOCAL STATUS gei82543EndPollSend
(
END_DEVICE* pDrvCtrl, /* device to be polled */
M_BLK_ID pMblk /* packet to send */
)
{
int len; /* packet length */
volatile UINT16 txHead; /* TX descriptor head index */
volatile UINT16 txTail; /* TX descriptor tail index */
UINT32 tmp; /* temparary variable for register */
char * pDesc; /* descriptor pointer */
int tempTail; /* temp variable for tail */
BOOL complete = FALSE;
DRV_LOG (DRV_DEBUG_POLL_TX, "gei82543EndPollSend...n", 1, 2, 3, 4, 5, 6);
/* check if the transmitter idle */
GEI_READ_REG(INTEL_82543GC_TDH, tmp);
txHead = (UINT16) tmp;
GEI_READ_REG(INTEL_82543GC_TDT, tmp);
txTail = (UINT16) tmp;
if (txHead != txTail)
{
DRV_LOG (DRV_DEBUG_POLL_TX, "gei82543EndPollSend: TX Activen",
1, 2, 3, 4, 5, 6);
return (EAGAIN);
}
/* check if any TX descriptor available */
GEI_GET_TX_DESC_TAIL_UPDATE(tempTail, 1);
pDesc = GEI_GET_TX_DESC_ADDR(tempTail);
if (!(GEI_READ_DESC_BYTE(pDesc, TXDESC_STATUS_OFFSET) & TXD_STAT_DD))
{
DRV_LOG (DRV_DEBUG_POLL_TX, ("gei82543EndPollSend...no TX descriptor
availablen"), 1, 2, 3, 4, 5, 6);
return (EAGAIN);
}
/* Ok, we have TX descriptor */
pDesc = GEI_GET_TX_DESC_ADDR(pDrvCtrl->txDescTail);
tmp = ((UINT32)(pDrvCtrl->pTxPollBufAdr) + (GEI_DESC_ALIGN_BYTE - 1)) &
~(GEI_DESC_ALIGN_BYTE - 1);
GEI_WRITE_DESC_LONG(pDesc, TXDESC_BUFADRLOW_OFFSET,
(UINT32)GEI_VIRT_TO_BUS((char *)tmp));
len = netMblkToBufCopy(pMblk, (char *)tmp, NULL);
len = max (ETHERSMALL, len);
/* set up the length field */
GEI_WRITE_DESC_WORD(pDesc, TXDESC_LENGTH_OFFSET, (UINT16)len);
/* zero the status field in Tx Desc */
GEI_WRITE_DESC_LONG(pDesc, TXDESC_STATUS_OFFSET, 0);
/* set up the command field */
GEI_WRITE_DESC_BYTE(pDesc, TXDESC_CMD_OFFSET,
(TXD_CMD_EOP | TXD_CMD_IFCS |
TXD_CMD_IDE | TXD_CMD_RS));
CACHE_PIPE_FLUSH();
/* update the tail pointer in TDT register */
GEI_WRITE_REG(INTEL_82543GC_TDT, tempTail);
/* bump the statistic counter. */
if (pMblk->mBlkHdr.mData[0] & (UINT8) 0x01)
pDrvCtrl->end.mib2Tbl.ifOutNUcastPkts += 1;
else
END_ERR_ADD (&pDrvCtrl->end, MIB2_OUT_UCAST, +1);
/* wait for packet send out */
while(!complete)
{
if ((UINT8)GEI_READ_DESC_BYTE(pDesc, TXDESC_STATUS_OFFSET) &
TXD_STAT_DD)
complete = TRUE;
}
complete = FALSE;
/* wait for transmitter idle */
while (!complete)
{
GEI_READ_REG(INTEL_82543GC_TDH, tmp);
txHead = (UINT16) tmp;
GEI_READ_REG(INTEL_82543GC_TDT, tmp);
txTail = (UINT16) tmp;
if (txHead == txTail)
complete = TRUE;
}
pDrvCtrl->txDescTail = tempTail;
DRV_LOG (DRV_DEBUG_POLL_TX, "gei82543EndPollSend...donen",
1, 2, 3, 4, 5, 6);
return (OK);
}
/*************************************************************************
*
* gei82543EndPollStart - start polling mode operations
*
* This routine starts the polling mode operation
*
* RETURNS: OK or ERROR.
*/
LOCAL STATUS gei82543EndPollStart
(
END_DEVICE * pDrvCtrl /* device to be polled */
)
{
int oldLevel;
oldLevel = intLock ();
/* disable chip interrupt */
gei82543DisableChipInt(pDrvCtrl);
/* turn off system interrupts */
SYS_INT_DISABLE(pDrvCtrl);
/* set the polling flag */
pDrvCtrl->flags |= FLAG_POLLING_MODE;
intUnlock (oldLevel);
taskDelay(sysClkRateGet() / 5);
DRV_LOG (DRV_DEBUG_POLL, "Polling Start...n", 1, 2, 3, 4, 5, 6);
return (OK);
}
/*************************************************************************
*
* gei82543EndPollStop - stop polling mode operations
*
* This function terminates polled mode operation. The device returns to
* interrupt mode. The device interrupts are enabled, the current mode flag is
* switched to indicate interrupt mode and the device is then reconfigured for
* interrupt operation.
*
* RETURNS: OK or ERROR.
*/
LOCAL STATUS gei82543EndPollStop
(
END_DEVICE * pDrvCtrl /* device to be polled */
)
{
int oldLevel;
oldLevel = intLock ();
pDrvCtrl->txDescFreeNum = 0;
gei82543TxDesCleanGet (pDrvCtrl, FREE_ALL_FORCE);
/* update the txDescLastCheck */
pDrvCtrl->txDescLastCheck = (pDrvCtrl->txDescTail +
pDrvCtrl->txDescNum - 1) % (pDrvCtrl->txDescNum);
pDrvCtrl->flags &= ~FLAG_POLLING_MODE;
/* clean pending interrupts */
gei82543DisableChipInt (pDrvCtrl);
/* turn on system interrupts */
SYS_INT_ENABLE(pDrvCtrl);
/* enable chip interrupt */
gei82543EnableChipInt (pDrvCtrl);
intUnlock (oldLevel);
taskDelay (sysClkRateGet() / 5);
DRV_LOG (DRV_DEBUG_POLL, "Polling stop ...donen", 1, 2, 3, 4, 5, 6);
return (OK);
}
/*************************************************************************
*
* gei82543TxMblkWaitClean - return borrowed mBlk/clDesc
*
* This function returns borrowed mBlk(s) when transmitting can be done
* in 5 seconds. Otherwise, it will forcefully return those mBlk(s).
*
* RETURNS: N/A
*/
LOCAL void gei82543TxMblkWaitClean
(
END_DEVICE * pDrvCtrl /* device to return mBlk(s) */
)
{
int ix;
/* wait until rx done */
for (ix = 50; ix; ix--)
{
/* clean up all loaned mbuf */
if (pDrvCtrl->txDescFreeNum < (pDrvCtrl->txDescNum - 1))
gei82543TxMblkFree (pDrvCtrl, FREE_ALL_AUTO);
if (pDrvCtrl->rxtxHandling != TRUE &&
pDrvCtrl->txDescFreeNum == (pDrvCtrl->txDescNum - 1))
break;
taskDelay (sysClkRateGet () / 10);
}
if (pDrvCtrl->rxtxHandling)
{
DRV_LOG (DRV_DEBUG_LOAD, "pDrvCtrl->rxtxHandling= TRUE%d, n", 1,
2, 3, 4, 5, 6);
}
/* force free all loaned mBlk */
if (pDrvCtrl->txDescFreeNum < (pDrvCtrl->txDescNum -1))
gei82543TxMblkFree (pDrvCtrl, FREE_ALL_FORCE);
}
/*************************************************************************
*
* gei82543EndStop - stop the device
*
* This function calls BSP functions to disconnect interrupts and stop
* the device from operating in interrupt mode.
*
* RETURNS: OK or ERROR.
*/
LOCAL STATUS gei82543EndStop
(
END_DEVICE *pDrvCtrl /* device to be stopped */
)
{
STATUS result = OK;
if (pDrvCtrl->attach != TRUE)
return ERROR;
/* mark interface down */
END_FLAGS_CLR (&pDrvCtrl->end, (IFF_UP | IFF_RUNNING));
/* turn off system interrupts */
SYS_INT_DISABLE(pDrvCtrl);
/* disable TX/RX operation */
gei82543TxRxDisable (pDrvCtrl);
gei82543DisableChipInt (pDrvCtrl);
/* cancel the timer if needed */
if (pDrvCtrl->timerId)
wdCancel (pDrvCtrl->timerId);
/* check device start flag */
if (pDrvCtrl->devStartFlag != TRUE)
return OK;
if (INT_CONTEXT())
{
netJobAdd ((FUNCPTR) gei82543TxMblkWaitClean, (int)pDrvCtrl,
0, 0, 0, 0);
}
else
{
gei82543TxMblkWaitClean (pDrvCtrl);
}
if (pDrvCtrl->pPhyInfo != NULL && pDrvCtrl->cableType == GEI_COPPER_MEDIA)
{
if (INT_CONTEXT())
{
netJobAdd ((FUNCPTR) miiPhyUnInit, (int)(pDrvCtrl->pPhyInfo),
0, 0, 0, 0);
netJobAdd ((FUNCPTR) cfree, (int)(pDrvCtrl->pPhyInfo),
0, 0, 0, 0);
}
else
{
if (miiPhyUnInit (pDrvCtrl->pPhyInfo) != OK)
{
LOGMSG("miiPhyUnInit failsn", 0,0,0,0,0,0);
}
cfree ((char *)pDrvCtrl->pPhyInfo);
}
}
/* disconnect interrupt handler */
SYS_INT_DISCONNECT(pDrvCtrl, gei82543EndInt, (int)pDrvCtrl, &result);
if (result == ERROR)
{
DRV_LOG (DRV_DEBUG_LOAD, "Could not disconnect interrupt!n", 1, 2,
3, 4, 5, 6);
}
pDrvCtrl->devStartFlag = FALSE;
return (result);
}
/*************************************************************************
*
* gei82543EndUnload - unload a driver from the system
*
* This function first brings down the device, and then frees any
* stuff that was allocated by the driver in the load function.
*
* RETURNS: OK or ERROR.
*/
LOCAL STATUS gei82543EndUnload
(
END_DEVICE* pDrvCtrl /* device to be unloaded */
)
{
/* delay a while in case device tries to stop */
taskDelay (sysClkRateGet () * 2);
END_OBJECT_UNLOAD (&pDrvCtrl->end);
/* free allocated memory */
gei82543MemAllFree (pDrvCtrl);
if (pDrvCtrl->timerId)
wdDelete (pDrvCtrl->timerId);
pDrvCtrl->attach = FALSE;
return (OK);
}
/**************************************************************************
*
* gei82543TxSetup - configure and setup TX for running
*
* This routine sets up the data structure for TX and configures transmitter
*
* RETURNS: N/A
*/
LOCAL void gei82543TxSetup
(
END_DEVICE * pDrvCtrl /* device to set up TX descriptors */
)
{
UINT32 tctlVal; /* transmit register value */
int ix;
/* initialization for TX operation*/
pDrvCtrl->txDescTail = 0;
pDrvCtrl->txStall = FALSE;
pDrvCtrl->txDescFreeNum = pDrvCtrl->txDescNum - 1;
pDrvCtrl->txDescLastCheck = pDrvCtrl->txDescNum - 1;
/* carve the transmit buffer memory */
for (ix = 0; ix < pDrvCtrl->txDescNum; ix++)
{
P_TX_DESCTL pDescCtl;
pDescCtl = pDrvCtrl->pTxDesCtlBase + ix;
pDescCtl->mBlk = NULL;
}
/* pre-init the transmit buffer memory */
for (ix = 0; ix < pDrvCtrl->txDescNum; ix++)
{
char * pTxDesc;
pTxDesc = GEI_GET_TX_DESC_ADDR(ix);
/* set up the command field */
GEI_WRITE_DESC_BYTE(pTxDesc, TXDESC_CMD_OFFSET,
(TXD_CMD_EOP | TXD_CMD_IFCS |
TXD_CMD_IDE | TXD_CMD_RS));
/* set DD bits in STATUS field */
GEI_WRITE_DESC_BYTE(pTxDesc, TXDESC_STATUS_OFFSET, TXD_STAT_DD);
}
/* set the TX descriptor BASE register */
GEI_WRITE_REG(INTEL_82543GC_TDBAL,
(UINT32) GEI_VIRT_TO_BUS((void *)(pDrvCtrl->pTxDescBase)));
GEI_WRITE_REG(INTEL_82543GC_TDBAH, 0);
/* set the length field */
GEI_WRITE_REG(INTEL_82543GC_TDLEN, (TXDESC_SIZE * pDrvCtrl->txDescNum));
/* initialize tail and head registers */
GEI_WRITE_REG(INTEL_82543GC_TDH, 0);
GEI_WRITE_REG(INTEL_82543GC_TDT, 0);
/* Set up the interrupt delay for Transmit*/
GEI_WRITE_REG(INTEL_82543GC_TIDV, pDrvCtrl->txIntDelay);
/* Set up LWTHRESH */
if (pDrvCtrl->adaptor.boardType == PRO1000_546_BOARD)
{
UINT32 txdctlVal; /* TXDCTL register value */
UINT32 count; /* temp var */
GEI_READ_REG(INTEL_82543GC_TXDCTL, txdctlVal);
count = pDrvCtrl->txDescNum / 8 - 1;
txdctlVal = ((txdctlVal & 0x1ffffff) | (count << 25));
GEI_WRITE_REG(INTEL_82543GC_TXDCTL, txdctlVal);
}
/* set up the IPG register */
if (pDrvCtrl->cableType == GEI_FIBER_MEDIA)
{
GEI_WRITE_REG(INTEL_82543GC_TIPG, DEFAULT_TIPG_IPGT_F
| (DEFAULT_TIPG_IPGR1 << TIPG_IPGR1_SHIFT)
| (DEFAULT_TIPG_IPGR2 << TIPG_IPGR2_SHIFT));
if (pDrvCtrl->duplex == FULL_DUPLEX_MODE)
GEI_WRITE_REG(INTEL_82543GC_TCTL, (TCTL_PSP_BIT
| (TX_COLLISION_THRESHOLD << TCLT_CT_SHIFT)
| (FDX_COLLISION_DISTANCE << TCTL_COLD_SHIFT)));
else
GEI_WRITE_REG(INTEL_82543GC_TCTL, (TCTL_PSP_BIT
| (TX_COLLISION_THRESHOLD << TCLT_CT_SHIFT)
| (HDX_COLLISION_DISTANCE << TCTL_COLD_SHIFT)));
}
else if (pDrvCtrl->cableType == GEI_COPPER_MEDIA)
{
GEI_WRITE_REG(INTEL_82543GC_TIPG, DEFAULT_TIPG_IPGT_T
| (DEFAULT_TIPG_IPGR1 << TIPG_IPGR1_SHIFT)
| (DEFAULT_TIPG_IPGR2 << TIPG_IPGR2_SHIFT));
GEI_READ_REG(INTEL_82543GC_TCTL, tctlVal);
GEI_WRITE_REG(INTEL_82543GC_TCTL, tctlVal | (TCTL_PSP_BIT
| (TX_COLLISION_THRESHOLD << TCLT_CT_SHIFT)));
}
CACHE_PIPE_FLUSH();
return;
}
/*************************************************************************
*
* gei82543RxSetup - configure and setup RX for running
*
* This routine sets up the data structure for RX and configures transmitter
*
* RETURNS: N/A
*/
LOCAL void gei82543RxSetup
(
END_DEVICE * pDrvCtrl /* device to do RX descriptor setting */
)
{
int ix; /* index */
UINT32 rctl = 0; /* rctl register value */
/* initialize the SW/HW for RX */
DRV_LOG (DRV_DEBUG_LOAD, "gei82543EndStart: set up RX structuren",
1, 2, 3, 4, 5, 6);
pDrvCtrl->rxDescTail = 0;
pDrvCtrl->rxtxHandling = FALSE;
/* hook up receive buffers to clusters in netpool */
for (ix = 0; ix < pDrvCtrl->rxDescNum; ix++)
{
char * pTempBuf;
char * pTempRxDesc;
if ((pTempBuf = (char *)netClusterGet(pDrvCtrl->end.pNetPool,
pDrvCtrl->pClPoolId)) == NULL)
{
DRV_LOG (DRV_DEBUG_LOAD, "gei82543EndMemInit: Could not get a
buffern", 1, 2, 3, 4, 5, 6);
return;
}
pTempBuf += pDrvCtrl->offset;
pTempRxDesc = GEI_GET_RX_DESC_ADDR(ix);
GEI_WRITE_DESC_LONG(pTempRxDesc, RXDESC_BUFADRLOW_OFFSET,
(UINT32)GEI_VIRT_TO_BUS(pTempBuf));
GEI_WRITE_DESC_LONG(pTempRxDesc, RXDESC_BUFADRHIGH_OFFSET, 0);
/* set up STATUS field */
GEI_WRITE_DESC_BYTE(pTempRxDesc,RXDESC_STATUS_OFFSET, 0);
}
GEI_WRITE_REG(INTEL_82543GC_RDTR, (pDrvCtrl->rxIntDelay | RDTR_FPD_BIT));
/* set up BASE register */
GEI_WRITE_REG(INTEL_82543GC_RDBAL,
(UINT32) GEI_VIRT_TO_BUS((void *)(pDrvCtrl->pRxDescBase)));
GEI_WRITE_REG(INTEL_82543GC_RDBAH, 0);
/* set up the LENGTH register*/
GEI_WRITE_REG(INTEL_82543GC_RDLEN, RXDESC_SIZE * (pDrvCtrl->rxDescNum));
/* set up head/tail registers */
GEI_WRITE_REG(INTEL_82543GC_RDH, 0);
GEI_WRITE_REG(INTEL_82543GC_RDT, (pDrvCtrl->rxDescNum - 1));
/* set up rctl register */
rctl = (pDrvCtrl->multiCastFilterType << RCTL_MO_SHIFT);
if (pDrvCtrl->usrFlags & GEI_END_JUMBO_FRAME_SUPPORT)
{
rctl |= RCTL_LPE_BIT;
/* equal transmit and receive storage in FIFO for jumbo frames */
if (pDrvCtrl->mtu > ETHERMTU)
{
GEI_WRITE_REG(INTEL_82543GC_PBA, 0x20); /* 24KB for RX/TX buf */
}
}
if (pDrvCtrl->rxBufSize == 2048)
rctl |= RCTL_BSIZE_2048;
else if (pDrvCtrl->rxBufSize == 4096)
rctl |= (RCTL_BSIZE_4096 | RCTL_BSEX_BIT);
else if (pDrvCtrl->rxBufSize == 8192)
rctl |= (RCTL_BSIZE_8192 | RCTL_BSEX_BIT);
else if (pDrvCtrl->rxBufSize == 16384)
rctl |= (RCTL_BSIZE_16384 | RCTL_BSEX_BIT);
else
{
LOGMSG ("Error: gei82543End.c : invalid rxBufSize =%dn",
pDrvCtrl->rxBufSize, 2, 3, 4, 5, 6);
/* in case */
rctl |= RCTL_BSIZE_2048;
}
#ifdef INCLUDE_TBI_COMPATIBLE
if (pDrvCtrl->tbiCompatibility)
rctl |= RCTL_SBP_BIT;
#endif /* INCLUDE_TBI_COMPATIBLE */
GEI_WRITE_REG(INTEL_82543GC_RCTL, rctl);
CACHE_PIPE_FLUSH();
return;
}
/*************************************************************************
*
* gei82543HwInit - Initialize 82543 MAC chip
*
* This routine initializes MAC and set up link
*
* RETURN: OK if success
*/
LOCAL STATUS gei82543HwInit
(
END_DEVICE * pDrvCtrl
)
{
/* clean up all receive address */
gei82543AllRxAdrClean (pDrvCtrl);
/* clean up all MTA registers */
gei82543AllMtaAdrClean (pDrvCtrl);
/* clean up VLAN stuff */
gei82543AllVlanClean (pDrvCtrl);
/* set up the IA for receive */
gei82543EtherRxAdrSet (pDrvCtrl, pDrvCtrl->adaptor.enetAddr, 0);
return (gei82543linkInit (pDrvCtrl));
}
/*************************************************************************
*
* gei82543linkInit - set up link for device operation
*
* This routine gets the configuration parameters from eeprom and configure
* device for linking
*
* RETURNS: OK if setup success
*/
LOCAL STATUS gei82543linkInit
(
END_DEVICE *pDrvCtrl
)
{
STATUS status = OK;
UINT32 tmp;
UINT32 tclRegVal;
UINT32 eepromWord = 0;
UINT32 extDevCtrlRegVal;
UINT32 staReg;
/* check copper or fiber based adapter */
GEI_READ_REG(INTEL_82543GC_STATUS, staReg);
if (staReg & STATUS_TBIMODE_BIT)
{
pDrvCtrl->cableType = GEI_FIBER_MEDIA;
}
else
{
pDrvCtrl->cableType = GEI_COPPER_MEDIA;
}
pDrvCtrl->devCtrlRegVal = 0;
/* compose control register value based on EEPROM config value */
if (pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD)
{
eepromWord = (UINT32) pDrvCtrl->adaptor.eeprom_icw1;
tmp = (eepromWord & EEPROM_ICW1_SWDPIO_BITS) >> EEPROM_ICW1_SWDPIO_SHIFT;
pDrvCtrl->devCtrlRegVal = tmp << CTRL_SWDPIOLO_SHIFT;
}
tmp = (eepromWord & EEPROM_ICW1_ILOS_BIT) >> EEPROM_ICW1_ILOS_SHIFT;
pDrvCtrl->devCtrlRegVal |= (tmp << CTRL_ILOS_SHIFT);
/* get the duplex configuration in EEPROM */
if (pDrvCtrl->duplex == DUPLEX_HW)
{
if (eepromWord & EEPROM_ICW1_FRCSPD_BIT)
pDrvCtrl->duplex = FULL_DUPLEX_MODE;
else
pDrvCtrl->duplex = HALF_DUPLEX_MODE;
}
/* get the flow control value in EEPROM */
eepromWord = (UINT32) pDrvCtrl->adaptor.eeprom_icw2;
if (pDrvCtrl->flowCtrl == FLOW_CONTRL_HW)
{
if ((eepromWord & EEPROM_ICW2_PAUSE_BITS) == 0)
pDrvCtrl->flowCtrl = FLOW_CONTRL_NONE;
else if ((eepromWord & EEPROM_ICW2_PAUSE_BITS) == EEPROM_ICW2_ASM_DIR)
pDrvCtrl->flowCtrl = FLOW_CONTRL_TRANSMIT;
else
pDrvCtrl->flowCtrl = FLOW_CONTRL_ALL;
}
DRV_LOG (DRV_DEBUG_LOAD, "gei82543SetLinkFlowCtrl: pDrvCtrl->flowCtrl=
%dn", pDrvCtrl->flowCtrl, 2, 3, 4, 5, 6);
/* program the extend control register */
if (pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD)
{
tmp = (eepromWord & EEPROM_ICW2_SWDPIO_EXE_BITS) >>
EEPROM_ICW2_SWDPIO_EXE_SHIFT;
extDevCtrlRegVal = tmp << CTRL_EXT_SWDPIOHI_SHIFT;
GEI_WRITE_REG(INTEL_82543GC_CTRL_EXT, extDevCtrlRegVal);
}
/* program the transmit control register */
GEI_READ_REG(INTEL_82543GC_TCTL, tclRegVal);
tclRegVal |= (FDX_COLLISION_DISTANCE << TCTL_COLD_SHIFT);
GEI_WRITE_REG(INTEL_82543GC_TCTL, tclRegVal);
/* set user's preference of DMA configuration */
if (pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD)
{
if (pDrvCtrl->dmaPriority == DMA_RX_PRIORITY)
{
pDrvCtrl->devCtrlRegVal &= ~CTRL_PRIOR_BIT;
}
else if (pDrvCtrl->dmaPriority == DMA_FAIR_RX_TX)
{
pDrvCtrl->devCtrlRegVal |= CTRL_PRIOR_BIT;
}
}
else
{
pDrvCtrl->devCtrlRegVal &= ~CTRL_PRIOR_BIT;
}
/* establish a link */
if (pDrvCtrl->cableType == GEI_FIBER_MEDIA)
status = gei82543linkTBISetup (pDrvCtrl, TRUE);
else if (pDrvCtrl->cableType == GEI_COPPER_MEDIA)
status = gei82543linkGMIISetup (pDrvCtrl);
else
{
DRV_LOG (DRV_DEBUG_LOAD, "Do not recognize media typen",
1, 2, 3, 4, 5, 6);
return ERROR;
}
pDrvCtrl->linkInitStatus = status;
if (pDrvCtrl->linkInitStatus != OK)
{
DRV_LOG (DRV_DEBUG_LOAD, ("gei82543EndStart: link setup failsn"),
1, 2, 3, 4, 5, 6);
LOGMSG("link failsn", 1, 2, 3, 4, 5, 6);
}
return status;
}
/*************************************************************************
*
* gei82543linkTBISetup - set up link to partner in TBI mode
*
* This routine set the link with partner in TBI mode
*
* RETURNS: OK if link success
*/
LOCAL STATUS gei82543linkTBISetup
(
END_DEVICE * pDrvCtrl,
BOOL firstTime /* TRUE for the first time calling */
)
{
UINT32 devStatus =0;
UINT32 intSet;
STATUS status = ERROR;
/* only TBI mode used*/
GEI_READ_REG(INTEL_82543GC_STATUS, devStatus);
if (!(devStatus & STATUS_TBIMODE_BIT))
{
LOGMSG("The adaptor is not configured in TBI moden", 1,2,3,4,5,6);
return ERROR;
}
/* disable chip interrupts */
intSet = gei82543DisableChipInt (pDrvCtrl);
/* set up txConfigure Word */
if (pDrvCtrl->flowCtrl == FLOW_CONTRL_NONE)
pDrvCtrl->txConfigureWord = (TXCW_ANE_BIT | TXCW_FD_BIT);
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_TRANSMIT)
pDrvCtrl->txConfigureWord = (TXCW_ANE_BIT | TXCW_FD_BIT |
TXCW_ASM_DIR);
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_ALL ||
pDrvCtrl->flowCtrl == FLOW_CONTRL_RECEIVE)
pDrvCtrl->txConfigureWord = (TXCW_ANE_BIT | TXCW_FD_BIT |
TXCW_PAUSE_BITS);
else
{
LOGMSG("Flow control parameter invalidn", 1, 2, 3, 4, 5, 6);
return ERROR;
}
status = gei82543TBIHwAutoNegotiate (pDrvCtrl, TRUE, firstTime);
if (status == ERROR &&
gei82543TBIlinkForce (pDrvCtrl, TRUE, FALSE) == OK)
{
UINT32 rxcwRegVal;
UINT32 ctrlRegVal;
status = OK;
GEI_READ_REG(INTEL_82543GC_CTRL, ctrlRegVal);
GEI_READ_REG(INTEL_82543GC_RXCW, rxcwRegVal);
if ((ctrlRegVal & CTRL_SLU_BIT) && (rxcwRegVal & RXCW_C_BIT))
{
status = gei82543TBIHwAutoNegotiate (pDrvCtrl, TRUE, FALSE);
if (status != OK)
{
DRV_LOG (DRV_DEBUG_LOAD, "Force link OK and receive RXCW;
But HW auto Failn",1, 2, 3, 4, 5, 6);
/* force link again */
status = gei82543TBIlinkForce (pDrvCtrl, TRUE, FALSE);
}
}
}
/* one more try */
if (status == ERROR)
status = gei82543TBIHwAutoNegotiate (pDrvCtrl, TRUE, FALSE);
pDrvCtrl->linkStatus = (status == OK)? LINK_STATUS_OK : LINK_STATUS_ERROR;
if (status == OK)
{
gei82543DuplexGet (pDrvCtrl);
gei82543SpeedGet (pDrvCtrl);
gei82543FlowCtrlRegsSet(pDrvCtrl);
LOGMSG("Link Establish OK. n", 1, 2, 3, 4, 5, 6);
}
else
{
DRV_LOG (DRV_DEBUG_LOAD, "Link setup fail", 1, 2, 3, 4, 5, 6);
}
if (firstTime != TRUE)
GEI_WRITE_REG(INTEL_82543GC_IMS, intSet);
return status;
}
/*************************************************************************
*
* gei82543TBIHwAutoNegotiate - link with hardware auto-negotiation
*
* This routine starts hardware auto-negotiation process
*
* RETURN: OK, or ERROR if link fail
*/
LOCAL STATUS gei82543TBIHwAutoNegotiate
(
END_DEVICE * pDrvCtrl,
BOOL waitStatus,
BOOL firstTime
)
{
UINT32 regVal;
int ix = LINK_TIMEOUT_IN_QUAR_SEC;
/* ack all interrupts again */
GEI_READ_REG(INTEL_82543GC_ICR, regVal);
pDrvCtrl->linkStatus = LINK_STATUS_UNKNOWN;
/* disable RXCFG interrupt */
if (pDrvCtrl->linkMethod == GEI82543_HW_AUTO)
GEI_WRITE_REG(INTEL_82543GC_IMC, IMC_RXCFG_BIT);
/* set up TXCW, start negotiation process */
GEI_WRITE_REG(INTEL_82543GC_TXCW, pDrvCtrl->txConfigureWord);
if (firstTime)
GEI_WRITE_REG(INTEL_82543GC_CTRL, pDrvCtrl->devCtrlRegVal);
else
{
GEI_READ_REG(INTEL_82543GC_CTRL, regVal);
GEI_WRITE_REG(INTEL_82543GC_CTRL, (regVal & ~CTRL_SLU_BIT));
}
pDrvCtrl->linkMethod = GEI82543_HW_AUTO;
if (waitStatus == FALSE)
return OK;
do {
/* wait... */
taskDelay(sysClkRateGet() / 4);
if (gei82543linkStatusCheck (pDrvCtrl) == OK)
return OK;
} while (ix--);
return ERROR;
}
/****************************************************************************
*
* gei82543TBIlinkForce - proceed force link
*
* This routine tries to link partner manually
*
* RETURNS: OK, or ERROR if fail
*/
LOCAL STATUS gei82543TBIlinkForce
(
END_DEVICE * pDrvCtrl, /* device to force link */
BOOL waitStatus, /* indicator to wait status */
BOOL rxcfgEnable /* indicator to enable RXCFG interrupt */
)
{
int ix = LINK_TIMEOUT_IN_QUAR_SEC;
UINT32 statusRegVal; /* status register value */
UINT32 rxcwRegVal; /* RXCW register value */
UINT32 ctrlRegVal; /* control register value */
UINT32 regVal;
/* ack all interrupts again */
GEI_READ_REG(INTEL_82543GC_ICR, regVal);
pDrvCtrl->linkStatus = LINK_STATUS_UNKNOWN;
/* read status register */
GEI_READ_REG(INTEL_82543GC_STATUS, statusRegVal);
/* read receive control register */
GEI_READ_REG(INTEL_82543GC_RXCW, rxcwRegVal);
if ((statusRegVal & STATUS_LU_BIT) || (rxcwRegVal & RXCW_C_BIT))
return ERROR;
DRV_LOG (DRV_DEBUG_LOAD, "Force Link... n", 1, 2, 3, 4, 5, 6);
GEI_READ_REG(INTEL_82543GC_CTRL, ctrlRegVal);
/* full duplex is assumed */
ctrlRegVal |= (CTRL_SLU_BIT | CTRL_FD_BIT);
/* disable HW auto-negotiation */
GEI_WRITE_REG(INTEL_82543GC_TXCW, pDrvCtrl->txConfigureWord &
~TXCW_ANE_BIT);
/* enable RXCFG interrupt if needed*/
if (rxcfgEnable == TRUE)
GEI_WRITE_REG(INTEL_82543GC_IMS, IMS_RXCFG_BIT);
GEI_WRITE_REG(INTEL_82543GC_CTRL, ctrlRegVal);
pDrvCtrl->linkMethod = GEI82543_FORCE_LINK;
/* read control register for later use */
GEI_READ_REG(INTEL_82543GC_CTRL, ctrlRegVal);
if (pDrvCtrl->flowCtrl == FLOW_CONTRL_NONE)
ctrlRegVal &= ~(CTRL_TFCE_BIT | CTRL_RFCE_BIT);
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_TRANSMIT)
{
ctrlRegVal &= ~CTRL_RFCE_BIT;
ctrlRegVal |= CTRL_TFCE_BIT;
}
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_RECEIVE)
{
ctrlRegVal &= ~CTRL_TFCE_BIT;
ctrlRegVal |= CTRL_RFCE_BIT;
}
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_ALL )
ctrlRegVal |= (CTRL_TFCE_BIT | CTRL_RFCE_BIT);
else
{
LOGMSG("invalid flow control parametersn", 1, 2, 3, 4, 5, 6);
return ERROR;
}
/* force link ... */
GEI_WRITE_REG(INTEL_82543GC_CTRL, ctrlRegVal);
if (waitStatus == FALSE)
return OK;
/* check status */
do {
/* wait... */
taskDelay(sysClkRateGet() / 4);
if (gei82543linkStatusCheck (pDrvCtrl) == OK)
return OK;
} while (ix--);
return ERROR;
}
/*************************************************************************
*
* gei82543linkGMIISetup - link set up with PHY device
*
* This routine sets up link with PHY device
*
* RETURN: OK if link succeed
*/
LOCAL STATUS gei82543linkGMIISetup
(
END_DEVICE * pDrvCtrl /* driver structure */
)
{
STATUS status = ERROR;
/* pre-init for PHY's GMII */
if ((status = gei82543linkGMIIPreInit(pDrvCtrl)) != OK )
{
DRV_LOG (DRV_DEBUG_LOAD, ("Failed to pre-initialize PHYn"),
0, 0, 0, 0, 0, 0);
return ERROR;
}
pDrvCtrl->pPhyInfo->phyFlags = pDrvCtrl->phyInitFlags;
/* call miiLib's functions */
if (miiPhyInit (pDrvCtrl->pPhyInfo) != OK)
{
DRV_LOG (DRV_DEBUG_LOAD, "fail to initialize PHYn", 0,0,0,0,0,0);
return (ERROR);
}
/* perform vendor specific register initialization */
pDrvCtrl->adaptor.phySpecInit (pDrvCtrl->pPhyInfo,
pDrvCtrl->pPhyInfo->phyAddr);
/* configure device after establishing a link */
gei82543GMIIphyConfig (pDrvCtrl);
return OK;
}
/*************************************************************************
*
* gei82543GMIIphyConfig - set up registers after PHY link done
*
* This routine configures chip after link is established. It gets the link
* results from PHY, and configure the device based on that.
*
* RETURNS: N/A
*/
LOCAL void gei82543GMIIphyConfig
(
END_DEVICE * pDrvCtrl /* device to config GMII */
)
{
UINT32 ctrlRegVal; /* control register value */
UINT32 tctlRegVal; /* transmit ctrl reg value */
UINT32 speed; /* link speed */
UINT32 duplex; /* link duplex mode */
/* get the speed setting from PHY */
speed = pDrvCtrl->pPhyInfo->phySpeed;
/* get the duplex setting from PHY */
if (pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_FD)
duplex = FULL_DUPLEX_MODE;
else
duplex = HALF_DUPLEX_MODE;
/* get the flow control setting from PHY */
if ((pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_TX_FLOW_CTRL) &&
(pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_RX_FLOW_CTRL))
pDrvCtrl->flowCtrl = FLOW_CONTRL_ALL;
else if (!(pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_TX_FLOW_CTRL) &&
(pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_RX_FLOW_CTRL))
pDrvCtrl->flowCtrl = FLOW_CONTRL_RECEIVE;
else if ((pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_TX_FLOW_CTRL) &&
!(pDrvCtrl->pPhyInfo->phyFlags & MII_PHY_RX_FLOW_CTRL))
pDrvCtrl->flowCtrl = FLOW_CONTRL_TRANSMIT;
else
pDrvCtrl->flowCtrl = FLOW_CONTRL_NONE;
/* prepare re-configure general/transmit control register */
GEI_READ_REG(INTEL_82543GC_CTRL, ctrlRegVal);
ctrlRegVal |= (CTRL_FRCSPD_BIT | CTRL_FRCDPX_BIT);
ctrlRegVal &= ~(CTRL_SPEED_MASK | CTRL_ILOS_BIT );
GEI_READ_REG(INTEL_82543GC_TCTL, tctlRegVal);
tctlRegVal &= ~TCTL_COLD_BIT;
/* configure duplex information */
if (duplex == FULL_DUPLEX_MODE)
{
ctrlRegVal |= CTRL_FD_BIT;
tctlRegVal |= (FDX_COLLISION_DISTANCE << TCTL_COLD_SHIFT);
}
else /* half duplex mode */
{
ctrlRegVal &= ~CTRL_FD_BIT;
if (speed == MII_1000MBS)
tctlRegVal |= (BIG_HDX_COLLISION_DISTANCE << TCTL_COLD_SHIFT) |
TCTL_PBE_BIT;
else
tctlRegVal |= (HDX_COLLISION_DISTANCE << TCTL_COLD_SHIFT);
}
/* configure speed info */
if (speed == MII_1000MBS)
ctrlRegVal |= CTRL_SPD_1000_BIT;
else if (speed == MII_100MBS)
ctrlRegVal |= CTRL_SPD_100_BIT;
else
{
ctrlRegVal &= ~(CTRL_SPD_1000_BIT | CTRL_SPD_100_BIT);
}
/* no flow control with half duplex mode */
if (duplex == HALF_DUPLEX_MODE)
pDrvCtrl->flowCtrl = FLOW_CONTRL_NONE;
/* configure flow control */
if (pDrvCtrl->flowCtrl == FLOW_CONTRL_NONE)
ctrlRegVal &= ~(CTRL_TFCE_BIT | CTRL_RFCE_BIT);
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_TRANSMIT)
{
ctrlRegVal &= ~CTRL_RFCE_BIT;
ctrlRegVal |= CTRL_TFCE_BIT;
}
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_RECEIVE)
{
ctrlRegVal &= ~CTRL_TFCE_BIT;
ctrlRegVal |= CTRL_RFCE_BIT;
}
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_ALL)
ctrlRegVal |= (CTRL_TFCE_BIT | CTRL_RFCE_BIT);
/* re-program general/transmit control registers */
GEI_WRITE_REG(INTEL_82543GC_TCTL, tctlRegVal);
GEI_WRITE_REG(INTEL_82543GC_CTRL, ctrlRegVal);
/* program flow control accordingly */
gei82543FlowCtrlRegsSet(pDrvCtrl);
#ifdef INCLUDE_TBI_COMPATIBLE
{
UINT32 rctlVal;
/*
* TBI compatibility bug occurred only in :
* 82543 based silicon, and
* copper-based media, and
* link parnter is advertised only 1000Base-T capability.
* we currently can not determine whether the link partner also
* supports other capabilities except 1000Base-T, thus we will
* enable workaround as the link partner has the 1000Base-T capability.
*/
GEI_READ_REG(INTEL_82543GC_RCTL, rctlVal);
if ((pDrvCtrl->usrFlags & GEI_END_TBI_COMPATIBILITY) &&
(pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD) &&
(speed == MII_1000MBS))
{
pDrvCtrl->tbiCompatibility = TRUE;
GEI_WRITE_REG(INTEL_82543GC_RCTL, (rctlVal | RCTL_SBP_BIT));
}
else
{
pDrvCtrl->tbiCompatibility = FALSE;
GEI_WRITE_REG(INTEL_82543GC_RCTL, (rctlVal & ~RCTL_SBP_BIT));
}
}
CACHE_PIPE_FLUSH ();
#endif /* INCLUDE_TBI_COMPATIBLE */
/* set the speed/duplex in the END_DEVICE structure */
gei82543DuplexGet (pDrvCtrl);
gei82543SpeedGet (pDrvCtrl);
return;
}
/*************************************************************************
*
* gei82543GMIIphyReConfig - re-configure 82543 chip after link is restarted
*
* This routine re-configures PHY chip after link is restarted and established.
* It gets the link results from PHY, and configure the device based on that.
*
* NOTE: *pPhyInfo should have a valid PHY bus number (phyAddr); Its phyFlags
* should be the one we configured the PHY for Auto-negotiaton last time.
*
* RETURNS: N/A
*/
LOCAL void gei82543GMIIphyReConfig
(
END_DEVICE * pDrvCtrl /* device to do PHY checking */
)
{
/* in case that the first time initialization fails */
if (pDrvCtrl->linkInitStatus != OK)
{
pDrvCtrl->linkInitStatus = gei82543linkGMIISetup (pDrvCtrl);
return;
}
/* we don't support force link case */
if (pDrvCtrl->pPhyInfo->phyLinkMethod != MII_PHY_LINK_AUTO)
return;
/* restore phyFlags with the flags for Auto-Negotiation */
pDrvCtrl->pPhyInfo->phyFlags = pDrvCtrl->pPhyInfo->phyAutoNegotiateFlags;
/* check/update MII auto-negotiation results */
miiAnCheck (pDrvCtrl->pPhyInfo, pDrvCtrl->pPhyInfo->phyAddr);
/* configure 82543 chip again */
gei82543GMIIphyConfig (pDrvCtrl);
}
/*************************************************************************
*
* gei82543linkGMIIPreInit - pre-init PHY for GMII link setup
*
* This routine resets PHY devices through 82543 chip, set up PHY_INFO
* structure
*
* RETURN: OK or ERROR
*/
LOCAL STATUS gei82543linkGMIIPreInit
(
END_DEVICE * pDrvCtrl /* device to do GMII pre-init */
)
{
UINT32 extCtrlRegVal; /* extended control reg value */
/*
* We will establish a link through PHY, and then manually
* configure the 82543 chip based on PHY's negotiation results
*/
pDrvCtrl->devCtrlRegVal |= (CTRL_FRCSPD_BIT | CTRL_FRCDPX_BIT |
CTRL_SLU_BIT);
GEI_WRITE_REG(INTEL_82543GC_CTRL, (pDrvCtrl->devCtrlRegVal));
if (pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD)
{
/*
* SDP_4 pin is also wired to PHY_RST, assert SDP_4(low)
* could reset PHY device
*/
/* reset the PHY device from 82543 chip */
GEI_READ_REG(INTEL_82543GC_CTRL_EXT, extCtrlRegVal);
extCtrlRegVal |= CTRL_PHY_RESET_DIR4_BIT;
GEI_WRITE_REG(INTEL_82543GC_CTRL_EXT, extCtrlRegVal);
taskDelay(sysClkRateGet() / 10);
GEI_READ_REG(INTEL_82543GC_CTRL_EXT, extCtrlRegVal);
extCtrlRegVal &= ~CTRL_PHY_RESET4_BIT;
GEI_WRITE_REG(INTEL_82543GC_CTRL_EXT, extCtrlRegVal);
taskDelay(sysClkRateGet() / 10);
GEI_READ_REG(INTEL_82543GC_CTRL_EXT, extCtrlRegVal);
extCtrlRegVal |= CTRL_PHY_RESET4_BIT;
GEI_WRITE_REG(INTEL_82543GC_CTRL_EXT, extCtrlRegVal);
taskDelay(sysClkRateGet() / 10);
}
else if (pDrvCtrl->adaptor.boardType == PRO1000_544_BOARD ||
pDrvCtrl->adaptor.boardType == PRO1000_546_BOARD)
{
GEI_WRITE_REG(INTEL_82543GC_CTRL,
(pDrvCtrl->devCtrlRegVal) | CTRL_PHY_RST_BIT);
/* wait PHY settle down */
taskDelay (sysClkRateGet () / 10);
GEI_WRITE_REG(INTEL_82543GC_CTRL, (pDrvCtrl->devCtrlRegVal));
taskDelay (sysClkRateGet () / 10);
}
/* allocate memory for PHY_INFO structure */
if ((pDrvCtrl->pPhyInfo = calloc (sizeof (PHY_INFO), 1)) == NULL)
return (ERROR);
/* clean up PHY_INFO structure */
memset (pDrvCtrl->pPhyInfo, 0, sizeof (PHY_INFO));
/* set up phyInfo structure */
pDrvCtrl->pPhyInfo->pDrvCtrl = (void *) pDrvCtrl;
pDrvCtrl->pPhyInfo->phyAddr = MII_PHY_DEF_ADDR;
/* PHY's read/write operation routine */
if (pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD)
{
pDrvCtrl->pPhyInfo->phyWriteRtn = (FUNCPTR) gei82543PhyWrite;
pDrvCtrl->pPhyInfo->phyReadRtn = (FUNCPTR) gei82543PhyRead;
}
else if (pDrvCtrl->adaptor.boardType == PRO1000_544_BOARD ||
pDrvCtrl->adaptor.boardType == PRO1000_546_BOARD)
{
pDrvCtrl->pPhyInfo->phyWriteRtn = (FUNCPTR) gei82544PhyWrite;
pDrvCtrl->pPhyInfo->phyReadRtn = (FUNCPTR) gei82544PhyRead;
}
if (pDrvCtrl->adaptor.phyAddr > 0 &&
pDrvCtrl->adaptor.phyAddr < MII_MAX_PHY_NUM)
pDrvCtrl->pPhyInfo->phyAddr = pDrvCtrl->adaptor.phyAddr;
else
pDrvCtrl->pPhyInfo->phyAddr = 0;
if (pDrvCtrl->adaptor.phyDelayRtn != (FUNCPTR) NULL)
{
pDrvCtrl->pPhyInfo->phyDelayRtn =
(FUNCPTR) (pDrvCtrl->adaptor.phyDelayRtn);
pDrvCtrl->pPhyInfo->phyMaxDelay =
pDrvCtrl->adaptor.phyMaxDelay;
pDrvCtrl->pPhyInfo->phyDelayParm =
pDrvCtrl->adaptor.phyDelayParm;
}
else
{
pDrvCtrl->pPhyInfo->phyDelayRtn = (FUNCPTR) taskDelay;
pDrvCtrl->pPhyInfo->phyMaxDelay = MII_PHY_DEF_DELAY;
pDrvCtrl->pPhyInfo->phyDelayParm = 5;
}
pDrvCtrl->pPhyInfo->phyAnOrderTbl = NULL;
pDrvCtrl->pPhyInfo->phyLinkDownRtn = (FUNCPTR) NULL;
/*
* All hardware capabilities will be advertised, and let auto-negotiation
* process figures out the max common ability; half duplex 1000T mode is NOT
* supported in the 82543-based adapter(Intel 82543 spec update Rev 0.5)
*/
if (pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD)
{
pDrvCtrl->pPhyInfo->phyFlags = GEI_MII_PHY_CAP_FLAGS; /* ability flags */
}
else if (pDrvCtrl->adaptor.boardType == PRO1000_544_BOARD ||
pDrvCtrl->adaptor.boardType == PRO1000_546_BOARD)
{
pDrvCtrl->pPhyInfo->phyFlags = GEI_MII_PHY_CAP_FLAGS | MII_PHY_1000T_HD;
}
if (pDrvCtrl->adaptor.phyType == GEI_PHY_GMII_TYPE)
pDrvCtrl->pPhyInfo->phyFlags |= MII_PHY_GMII_TYPE; /* GMII type */
else
pDrvCtrl->pPhyInfo->phyFlags &= ~MII_PHY_GMII_TYPE;
pDrvCtrl->pPhyInfo->phyFlags |= MII_PHY_AUTO; /* allow auto-negotiation */
/* set the flow control bits in phyFlags */
if (pDrvCtrl->flowCtrl == FLOW_CONTRL_NONE )
pDrvCtrl->pPhyInfo->phyFlags &= ~(MII_PHY_TX_FLOW_CTRL |
MII_PHY_RX_FLOW_CTRL);
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_TRANSMIT)
{
pDrvCtrl->pPhyInfo->phyFlags |= MII_PHY_TX_FLOW_CTRL;
pDrvCtrl->pPhyInfo->phyFlags &= ~MII_PHY_RX_FLOW_CTRL;
}
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_ALL ||
pDrvCtrl->flowCtrl == FLOW_CONTRL_RECEIVE)
pDrvCtrl->pPhyInfo->phyFlags |= (MII_PHY_TX_FLOW_CTRL |
MII_PHY_RX_FLOW_CTRL);
else
{
LOGMSG(" invalid flow control parametern",1,2,3,4,5,6);
}
/* mark phyflags to indicated pre-initialization */
pDrvCtrl->pPhyInfo->phyFlags |= MII_PHY_PRE_INIT;
/* save flags for later reference */
pDrvCtrl->phyInitFlags = pDrvCtrl->pPhyInfo->phyFlags;
return OK;
}
/***************************************************************************
*
* gei82543EtherRxAdrSet - set up the first entry on Receive Address Table
*
* This routine sets up the MAC address
*
* RETURNS: N/A
*/
LOCAL void gei82543EtherRxAdrSet
(
END_DEVICE * pDrvCtrl,
UINT8 adr[],
int index
)
{
UINT32 ral = 0;
UINT32 rah = 0;
UINT32 reg;
/* split the address to RAH/RAL */
ral = (adr[0] | (adr[1] << 8) | (adr[2] << 16) | (adr[3] << 24) );
rah = (adr[4] | (adr[5] << 8) | (RAH_AV_BIT));
reg = INTEL_82543GC_RAL + index * 8;
GEI_WRITE_REG(reg, ral);
reg = INTEL_82543GC_RAH + index * 8;
GEI_WRITE_REG(reg, rah);
return;
}
/*************************************************************************
*
* gei82543Delay - delay function to be used for PHY read/write operation
*
* This routine delays for a specified time in the unit of ns
*
* RETURN: N/A
*/
LOCAL void gei82543Delay
(
END_DEVICE * pDrvCtrl,
UINT32 timeDelay /* in unit of ns */
)
{
int count;
/*
* we hope BSP can provide a delay routine with higher time resolution.
* if using taskDelay(), it probably results in a slower initialization
* process for hardware, such as MII/GMII read/write operations
*/
if (pDrvCtrl->adaptor.delayFunc == NULL ||
pDrvCtrl->adaptor.delayUnit == 0)
{
/* convert to ticks */
count = (sysClkRateGet () * timeDelay / 1000000) / 1000 + 1;
taskDelay (count);
return;
}
count = (timeDelay / (pDrvCtrl->adaptor.delayUnit)) + 1;
for ( ; count > 0; count--)
{
(FUNCPTR) pDrvCtrl->adaptor.delayFunc ();
}
return;
}
/**************************************************************************
*
* gei82543Reset - reset 82543/4/5/6 chips
*
* This routine resets 82543/4/5/6 chips
*
* RETURNS: N/A
*/
LOCAL void gei82543Reset
(
END_DEVICE * pDrvCtrl
)
{
/* disable all interrupt */
gei82543DisableChipInt (pDrvCtrl);
/* disable/clean RX CTL */
GEI_WRITE_REG(INTEL_82543GC_RCTL, 0);
/* disable/clean TX CTL */
GEI_WRITE_REG(INTEL_82543GC_TCTL, 0);
/* reset the chip */
GEI_WRITE_REG(INTEL_82543GC_CTRL, CTRL_RST_BIT);
/* wait hardware ready */
taskDelay (sysClkRateGet() / 6);
/* clean up CTRL_EXT for 82543/82544 MACs */
if (pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD ||
pDrvCtrl->adaptor.boardType == PRO1000_544_BOARD)
{
GEI_WRITE_REG(INTEL_82543GC_CTRL_EXT, 0);
}
/* clean all pending interrupts */
gei82543DisableChipInt (pDrvCtrl);
return;
}
/****************************************************************************
*
* gei82543AllVlanClean - cleans up all VLAN table entry
*
* This routine cleans up all entries in the VLAN table
*
* RETURNS: N/A
*/
LOCAL void gei82543AllVlanClean
(
END_DEVICE * pDrvCtrl
)
{
UINT32 ix;
UINT32 reg;
GEI_WRITE_REG(INTEL_82543GC_VET, 0x0);
for (ix = 0; ix < NUM_VLAN; ix++)
{
reg = INTEL_82543GC_VLAN + ix * 4;
GEI_WRITE_REG(reg, 0);
}
return;
}
/****************************************************************************
*
* gei82543McastAdrClean - clean up all Multicasting address
*
* This routine cleans up all entries in MTA table and Multicasting Address in
* RTA table
*
* RETURNS: N/A
*/
LOCAL void gei82543McastAdrClean
(
END_DEVICE * pDrvCtrl
)
{
UINT32 ix;
UINT32 regVal;
for (ix = 1; ix < NUM_RAR; ix++)
{
GEI_READ_REG((INTEL_82543GC_RAL + ix * 8), regVal);
/* check multicast address */
if (regVal & 0x1)
{
GEI_WRITE_REG((INTEL_82543GC_RAL + ix * 8), 0);
GEI_WRITE_REG((INTEL_82543GC_RAH + ix * 8), 0);
}
}
/* clean up MTA entries */
gei82543AllMtaAdrClean (pDrvCtrl);
return;
}
/****************************************************************************
*
* gei82543AllMtaAdrClean - clean up all MTA table entries
*
* This routine cleans up all entries in MTA table.
*
* RETURNS: N/A
*/
LOCAL void gei82543AllMtaAdrClean
(
END_DEVICE * pDrvCtrl /* device to clean up MTA table */
)
{
UINT32 ix; /* index */
UINT32 reg; /* register offset */
/* clean up MTA */
for (ix = 0; ix < NUM_MTA; ix++)
{
reg = INTEL_82543GC_MTA + ix * 4;
GEI_WRITE_REG(reg, 0);
}
return;
}
/****************************************************************************
*
* gei82543AllRxAdrClean - clean up all entry in receive address table
*
* This routine clean up receive address table (RTA)
*
* RETURNS: N/A
*/
LOCAL void gei82543AllRxAdrClean
(
END_DEVICE * pDrvCtrl /* device to clean up RAT */
)
{
int ix;
UINT32 regAdr; /* register offset */
/* clean up RTA */
for (ix = 0; ix < NUM_RAR; ix ++)
{
regAdr = INTEL_82543GC_RAL + ix * 8;
GEI_WRITE_REG(regAdr, 0);
regAdr = INTEL_82543GC_RAH + ix * 8;
GEI_WRITE_REG(regAdr, 0);
}
return;
}
/****************************************************************************
*
* gei82543FlowCtrlRegsSet - set up the flow control registers
*
* This routine set up the flow control registers
*
* RETURNS: N/A
*/
LOCAL void gei82543FlowCtrlRegsSet
(
END_DEVICE * pDrvCtrl /* device to set flow control register */
)
{
/* set up flow control registers */
GEI_WRITE_REG(INTEL_82543GC_FCAL, FLOW_CONTROL_LOW_ADR);
GEI_WRITE_REG(INTEL_82543GC_FCAH, FLOW_CONTROL_HIGH_ADR);
GEI_WRITE_REG(INTEL_82543GC_FCT, FLOW_CONTROL_TYPE);
GEI_WRITE_REG(INTEL_82543GC_FCTTV, FLOW_CONTROL_TIMER_VALUE);
if ((pDrvCtrl->flowCtrl == FLOW_CONTRL_RECEIVE) ||
(pDrvCtrl->flowCtrl == FLOW_CONTRL_ALL) )
{
GEI_WRITE_REG(INTEL_82543GC_FCRTL,
FCRTL_XONE_BIT | FLOW_CONTROL_LOW_THRESH );
GEI_WRITE_REG(INTEL_82543GC_FCRTH, FLOW_CONTROL_HIGH_THRESH);
}
else
{
GEI_WRITE_REG(INTEL_82543GC_FCRTL, 0);
GEI_WRITE_REG(INTEL_82543GC_FCRTH, 0);
}
return;
}
/*************************************************************************
*
* gei82543SpeedGet - get the speed from device
*
* This routine get the speed from device control register
*
* RETURN: N/A
*/
LOCAL void gei82543SpeedGet
(
END_DEVICE * pDrvCtrl /* device to get speed */
)
{
UINT32 val; /* register value */
if (pDrvCtrl->cableType == GEI_FIBER_MEDIA)
{
/* only 1000Mbs supported */
pDrvCtrl->speed = END_SPEED_1000M;
return;
}
else if (pDrvCtrl->cableType == GEI_COPPER_MEDIA)
{
/* get status register */
GEI_READ_REG(INTEL_82543GC_STATUS, val);
if (val & STATUS_SPEED_1000_BIT)
pDrvCtrl->speed = END_SPEED_1000M;
else if (val & STATUS_SPEED_100_BIT)
pDrvCtrl->speed = END_SPEED_100M;
else
pDrvCtrl->speed = END_SPEED_10M;
}
else
pDrvCtrl->speed = UNKNOWN;
return;
}
/*************************************************************************
*
* gei82543DuplexGet - get the duplex mode
*
* This routine gets duplex mode from device status register
*
* RETURN: N/A
*/
LOCAL void gei82543DuplexGet
(
END_DEVICE * pDrvCtrl /* device to get duplex */
)
{
UINT32 val; /* register value */
GEI_READ_REG(INTEL_82543GC_STATUS, val);
if (val & STATUS_FD_BIT)
pDrvCtrl->duplex = FULL_DUPLEX_MODE;
else
{
DRV_LOG (DRV_DEBUG_LOAD, "Half duplex moden...", 1, 2, 3, 4, 5, 6);
pDrvCtrl->duplex = HALF_DUPLEX_MODE;
}
return;
}
/*************************************************************************
*
* gei82543linkStatusCheck - check link status
*
* This routine checks link status
*
* RETURN: OK or ERROR
*/
LOCAL STATUS gei82543linkStatusCheck
(
END_DEVICE * pDrvCtrl /* device to check link status */
)
{
register UINT32 ctrlVal; /* control register value */
register UINT32 statusVal; /* status register value */
GEI_READ_REG(INTEL_82543GC_CTRL, ctrlVal);
GEI_READ_REG(INTEL_82543GC_STATUS, statusVal);
if (pDrvCtrl->cableType == GEI_COPPER_MEDIA ||
pDrvCtrl->adaptor.boardType == PRO1000_544_BOARD ||
pDrvCtrl->adaptor.boardType == PRO1000_546_BOARD)
{
if (statusVal & STATUS_LU_BIT)
return OK;
}
else /* FIBER media and 82543 based adaptor */
{
if (!(ctrlVal & CTRL_SWDPIN1_BIT) && (statusVal & STATUS_LU_BIT))
return OK;
}
return ERROR;
}
/*************************************************************************
*
* gei82543TxRxDisable - disable TX/RX of MAC
*
* This routine disable TX/RX
*
* RETURN: N/A
*/
LOCAL void gei82543TxRxDisable
(
END_DEVICE *pDrvCtrl /* driver to disable TX/RX */
)
{
UINT32 regVal; /* register value */
/* disable chip RX/TX */
GEI_READ_REG(INTEL_82543GC_RCTL, regVal);
GEI_WRITE_REG(INTEL_82543GC_RCTL, (regVal & ~RCTL_EN_BIT));
GEI_READ_REG(INTEL_82543GC_TCTL,regVal);
GEI_WRITE_REG(INTEL_82543GC_TCTL, (regVal & ~TCTL_EN_BIT));
}
/*************************************************************************
*
* gei82543TxRxEnable - Enable TX/RX operation
*
* This routine enable TX/RX operation
*
* RETURN: N/A
*/
LOCAL void gei82543TxRxEnable
(
END_DEVICE * pDrvCtrl /* driver to enable TX/RX */
)
{
UINT32 regVal; /* register value */
/* enable chip RX/TX */
GEI_READ_REG(INTEL_82543GC_RCTL, regVal);
GEI_WRITE_REG(INTEL_82543GC_RCTL, (regVal | RCTL_EN_BIT));
GEI_READ_REG(INTEL_82543GC_TCTL, regVal);
GEI_WRITE_REG(INTEL_82543GC_TCTL, (regVal | TCTL_EN_BIT));
return;
}
/*************************************************************************
*
* gei82543EnableChipInt - enable 82543 chip interrupt
*
* This routine enables 82543 chip interrupt
*
* RETURNS: N/A
*/
LOCAL void gei82543EnableChipInt
(
END_DEVICE * pDrvCtrl /* enable chip interrupt */
)
{
UINT32 intSet; /* interrupt setting */
if (pDrvCtrl->linkMethod == GEI82543_FORCE_LINK)
intSet = (AVAIL_RX_TX_INT | AVAIL_LINK_INT | INT_RXCFG_BIT);
else
intSet = (AVAIL_RX_TX_INT | AVAIL_LINK_INT );
GEI_WRITE_REG(INTEL_82543GC_IMS, intSet);
return;
}
/*************************************************************************
*
* gei82543DisableChipInt - disable 82543 chip interrupt
*
* This routine disables 82543 chip interrupts
*
* RETURNS: Interrupt setting before disable
*/
LOCAL UINT32 gei82543DisableChipInt
(
END_DEVICE * pDrvCtrl /* driver structure */
)
{
volatile UINT32 intSet; /* interrupt setting before */
GEI_READ_REG(INTEL_82543GC_IMS, intSet);
GEI_WRITE_REG(INTEL_82543GC_IMC, IMC_ALL_BITS);
/* read back icr to clean up all pending interruots */
GEI_READ_REG(INTEL_82543GC_ICR, intSet);
return intSet;
}
/*************************************************************************
*
* gei82543miiReadData - shift data in from MDIO pin
*
* This routine shifts data in from MDIO pin.
*
* RETURN: data from MDIO
*/
LOCAL UINT16 gei82543miiReadData
(
END_DEVICE * pDrvCtrl /* driver structure */
)
{
volatile UINT32 ctrlRegVal; /* control register value */
UINT16 data = 0; /* read-back data */
UINT8 i; /* index */
/* clean up */
GEI_READ_REG(INTEL_82543GC_CTRL, ctrlRegVal);
ctrlRegVal &= ~(CTRL_MDIO_DIR_BIT | CTRL_MDIO_BIT);
GEI_WRITE_REG(INTEL_82543GC_CTRL, ctrlRegVal);
/* raise clk */
GEI_WRITE_REG(INTEL_82543GC_CTRL, (ctrlRegVal | CTRL_MDC_BIT));
gei82543Delay (pDrvCtrl, 1000);
/* lower clk */
GEI_WRITE_REG(INTEL_82543GC_CTRL, (ctrlRegVal & ~CTRL_MDC_BIT));
gei82543Delay (pDrvCtrl, 1000);
/* read data which is always 16 bits */
for (i = 0; i < 16; i++)
{
/* raise clk */
GEI_WRITE_REG(INTEL_82543GC_CTRL, (ctrlRegVal | CTRL_MDC_BIT));
gei82543Delay (pDrvCtrl, 1000);
GEI_READ_REG(INTEL_82543GC_CTRL, ctrlRegVal);
data = (data << 1) | ((ctrlRegVal & CTRL_MDIO_BIT) ? 1 : 0);
/* lower clk */
GEI_WRITE_REG(INTEL_82543GC_CTRL, (ctrlRegVal & ~CTRL_MDC_BIT));
gei82543Delay (pDrvCtrl, 1000);
}
/* raise clk */
GEI_WRITE_REG(INTEL_82543GC_CTRL, (ctrlRegVal | CTRL_MDC_BIT));
gei82543Delay (pDrvCtrl, 1000);
/* lower clk */
GEI_WRITE_REG(INTEL_82543GC_CTRL, (ctrlRegVal & ~CTRL_MDC_BIT));
gei82543Delay (pDrvCtrl, 1000);
return (data);
}
/****************************************************************************
*
* gei82543miiWriteData - shift the data out to MDIO pin
*
* This routine shifts data out to MDIO pin.
*
* RETURN: N/A
*/
LOCAL void gei82543miiWriteData
(
END_DEVICE * pDrvCtrl, /* driver structure */
UINT32 data, /* data to shift */
UINT32 numBits /* number of bits to shift */
)
{
volatile UINT32 ctrlRegVal; /* control register value */
UINT32 mask; /* mask bits */
int ix; /* index */
GEI_READ_REG(INTEL_82543GC_CTRL, ctrlRegVal);
ctrlRegVal |= (CTRL_MDIO_DIR_BIT | CTRL_MDC_DIR_BIT);
for (ix = numBits - 1 ; ix >= 0; ix--)
{
mask = 1 << ix;
ctrlRegVal = (data & mask) ? (ctrlRegVal | CTRL_MDIO_BIT) :
(ctrlRegVal & ~CTRL_MDIO_BIT);
GEI_WRITE_REG(INTEL_82543GC_CTRL, ctrlRegVal);
gei82543Delay (pDrvCtrl, 1000);
GEI_WRITE_REG(INTEL_82543GC_CTRL, (ctrlRegVal | CTRL_MDC_BIT));
gei82543Delay (pDrvCtrl, 1000);
GEI_WRITE_REG(INTEL_82543GC_CTRL, (ctrlRegVal & ~CTRL_MDC_BIT));
gei82543Delay (pDrvCtrl, 1000);
}
return;
}
/*************************************************************************
*
* gei82543PhyRead - read MII register
*
* This routine performs reading of MII registers in PHY devices
*
* RETURN: OK if read correct
*/
LOCAL STATUS gei82543PhyRead
(
END_DEVICE * pDrvCtrl, /* device structure */
UINT8 phyAddr, /* PHY device bus number */
UINT8 phyReg, /* register offset to read */
UINT16 * data /* return data address */
)
{
UINT32 cmd; /* command data */
UINT32 val; /* read-back data */
/*
* compose cmd in the reverse order because the most significant
* bits of phyAddr and phyReg should be shifted out first
*/
cmd = (phyReg | (phyAddr << 5) | (PHY_RD_OP << 10) | (PHY_MARK) << 12);
/* shift the PREMABLE bits out first */
gei82543miiWriteData (pDrvCtrl, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
/* shift the command out */
gei82543miiWriteData (pDrvCtrl, cmd, 14);
/* read return register value */
val = gei82543miiReadData(pDrvCtrl);
if (val & MDI_ERR_BIT)
return ERROR;
*data = (UINT16)val;
return OK;
}
/*************************************************************************
*
* gei82543PhyWrite - write MII registers in PHY
*
* This routine performs write operation to MII registers in a PHY device
*
* RETURN: OK
*/
LOCAL STATUS gei82543PhyWrite
(
END_DEVICE * pDrvCtrl, /* driver structure */
UINT8 phyAddr, /* PHY bus number */
UINT8 phyReg, /* PHY's register to write */
UINT16 data /* data to write */
)
{
UINT32 cmd; /* command */
cmd = (data | (PHY_TURNAR << 16) | (phyReg << 18 ) |
(phyAddr << 23) | (PHY_WR_OP << 28) | (PHY_MARK) << 30) ;
gei82543miiWriteData (pDrvCtrl, PHY_PREAMBLE, PHY_PREAMBLE_SIZE);
gei82543miiWriteData (pDrvCtrl, cmd, 32);
return OK;
}
/*************************************************************************
*
* gei82544PhyRead - read MII register of 82544 chip
*
* This routine performs reading of MII registers in the internal PHY
*
* RETURN: OK if read correct
*/
LOCAL STATUS gei82544PhyRead
(
END_DEVICE * pDrvCtrl, /* device structure */
UINT8 phyAddr, /* PHY device bus number */
UINT8 phyReg, /* register offset to read */
UINT16 * data /* return data address */
)
{
int count = 6; /* counter */
volatile UINT32 mdicRegVal;
mdicRegVal = (MDI_READ_BIT | phyAddr << MDI_PHY_SHIFT |
phyReg << MDI_REG_SHIFT);
GEI_WRITE_REG(INTEL_82543GC_MDI, mdicRegVal);
gei82543Delay (pDrvCtrl, 32000); /* wait 32 microseconds */
while (count--) /* wait max 96 microseconds */
{
GEI_READ_REG(INTEL_82543GC_MDI, mdicRegVal);
if (mdicRegVal & MDI_READY_BIT)
break;
gei82543Delay (pDrvCtrl, 16000);
}
if ((mdicRegVal & (MDI_READY_BIT | MDI_ERR_BIT)) != MDI_READY_BIT)
{
DRV_LOG (DRV_DEBUG_LOAD, "Error: MII read PhyAddr=%d, phyReg=%dn...",
phyAddr, phyReg, 3, 4, 5, 6);
}
*data = (UINT16) mdicRegVal;
return OK;
}
/*************************************************************************
*
* gei82544PhyWrite - write MII registers in the internal PHY of 82544
*
* This routine performs write operation to MII registers in the internal
* PHY device
*
* RETURN: OK if success
*/
LOCAL STATUS gei82544PhyWrite
(
END_DEVICE * pDrvCtrl, /* driver structure */
UINT8 phyAddr, /* PHY bus number */
UINT8 phyReg, /* PHY's register to write */
UINT16 data /* data to write */
)
{
int count = 6; /* counter */
volatile UINT32 mdicRegVal;
mdicRegVal = (MDI_WRITE_BIT | phyAddr << MDI_PHY_SHIFT |
phyReg << MDI_REG_SHIFT | data);
GEI_WRITE_REG(INTEL_82543GC_MDI, mdicRegVal);
gei82543Delay (pDrvCtrl, 32000); /* wait 32 microseconds */
while (count--) /* wait max 96 microseconds */
{
GEI_READ_REG(INTEL_82543GC_MDI, mdicRegVal);
if (mdicRegVal & MDI_READY_BIT)
break;
gei82543Delay (pDrvCtrl, 16000);
}
if ((mdicRegVal & (MDI_READY_BIT | MDI_ERR_BIT)) != MDI_READY_BIT)
{
DRV_LOG (DRV_DEBUG_LOAD, "Error: MII write PhyAddr=%d, phyReg=%dn...",
phyAddr, phyReg, 3, 4, 5, 6);
}
return OK;
}
/**************************************************************************
*
* gei82543HwStatusDump - get and clean up statistic registers
*
* This routine gets/cleans up all statistic registers
*
* RETURNS: N/A
*/
LOCAL void gei82543HwStatusDump
(
END_DEVICE * pDrvCtrl /* device to dump statistic registers */
)
{
GEI_READ_REG(INTEL_82543GC_CRCERRS, pDrvCtrl->staRegs.crcerrs);
GEI_READ_REG(INTEL_82543GC_ALGNERRC, pDrvCtrl->staRegs.algnerrc);
GEI_READ_REG(INTEL_82543GC_SYMERRS, pDrvCtrl->staRegs.symerrs);
GEI_READ_REG(INTEL_82543GC_RXERRC, pDrvCtrl->staRegs.rxerrc);
GEI_READ_REG(INTEL_82543GC_MPC, pDrvCtrl->staRegs.mpc);
GEI_READ_REG(INTEL_82543GC_SCC, pDrvCtrl->staRegs.scc);
GEI_READ_REG(INTEL_82543GC_ECOL,pDrvCtrl->staRegs.ecol);
GEI_READ_REG(INTEL_82543GC_MCC, pDrvCtrl->staRegs.mcc);
GEI_READ_REG(INTEL_82543GC_LATECOL, pDrvCtrl->staRegs.latecol);
GEI_READ_REG(INTEL_82543GC_COLC, pDrvCtrl->staRegs.colc);
GEI_READ_REG(INTEL_82543GC_TUC, pDrvCtrl->staRegs.tuc);
GEI_READ_REG(INTEL_82543GC_DC, pDrvCtrl->staRegs.dc);
GEI_READ_REG(INTEL_82543GC_TNCRS,pDrvCtrl->staRegs.tncrs);
GEI_READ_REG(INTEL_82543GC_SEC, pDrvCtrl->staRegs.sec);
GEI_READ_REG(INTEL_82543GC_CEXTEER, pDrvCtrl->staRegs.cexteer);
GEI_READ_REG(INTEL_82543GC_RLEC, pDrvCtrl->staRegs.rlec);
GEI_READ_REG(INTEL_82543GC_XONRXC, pDrvCtrl->staRegs.xonrxc);
GEI_READ_REG(INTEL_82543GC_XONTXC, pDrvCtrl->staRegs.xontxc);
GEI_READ_REG(INTEL_82543GC_XOFFRXC, pDrvCtrl->staRegs.xoffrxc);
GEI_READ_REG(INTEL_82543GC_XOFFTXC, pDrvCtrl->staRegs.xofftxc);
GEI_READ_REG(INTEL_82543GC_FCRUC, pDrvCtrl->staRegs.fcruc);
GEI_READ_REG(INTEL_82543GC_PRC64, pDrvCtrl->staRegs.prc64);
GEI_READ_REG(INTEL_82543GC_PRC127, pDrvCtrl->staRegs.prc127);
GEI_READ_REG(INTEL_82543GC_PRC255, pDrvCtrl->staRegs.prc255);
GEI_READ_REG(INTEL_82543GC_PRC511, pDrvCtrl->staRegs.prc511);
GEI_READ_REG(INTEL_82543GC_PRC1023, pDrvCtrl->staRegs.prc1023);
GEI_READ_REG(INTEL_82543GC_PRC1522, pDrvCtrl->staRegs.prc1522);
GEI_READ_REG(INTEL_82543GC_GPRC, pDrvCtrl->staRegs.gprc);
GEI_READ_REG(INTEL_82543GC_BPRC, pDrvCtrl->staRegs.bprc);
GEI_READ_REG(INTEL_82543GC_MPRC, pDrvCtrl->staRegs.mprc);
GEI_READ_REG(INTEL_82543GC_GPTC, pDrvCtrl->staRegs.gptc);
GEI_READ_REG(INTEL_82543GC_GORL, pDrvCtrl->staRegs.gorl);
GEI_READ_REG(INTEL_82543GC_GORH, pDrvCtrl->staRegs.gorh);
GEI_READ_REG(INTEL_82543GC_GOTL, pDrvCtrl->staRegs.gotl);
GEI_READ_REG(INTEL_82543GC_GOTH, pDrvCtrl->staRegs.goth);
GEI_READ_REG(INTEL_82543GC_RNBC, pDrvCtrl->staRegs.rnbc);
GEI_READ_REG(INTEL_82543GC_RUC, pDrvCtrl->staRegs.ruc);
GEI_READ_REG(INTEL_82543GC_RFC, pDrvCtrl->staRegs.rfc);
GEI_READ_REG(INTEL_82543GC_ROC, pDrvCtrl->staRegs.roc);
GEI_READ_REG(INTEL_82543GC_RJC, pDrvCtrl->staRegs.rjc);
GEI_READ_REG(INTEL_82543GC_TORL, pDrvCtrl->staRegs.torl);
GEI_READ_REG(INTEL_82543GC_TORH, pDrvCtrl->staRegs.torh);
GEI_READ_REG(INTEL_82543GC_TOTL, pDrvCtrl->staRegs.totl);
GEI_READ_REG(INTEL_82543GC_TOTH, pDrvCtrl->staRegs.toth);
GEI_READ_REG(INTEL_82543GC_TPR, pDrvCtrl->staRegs.tpr);
GEI_READ_REG(INTEL_82543GC_TPT, pDrvCtrl->staRegs.tpt);
GEI_READ_REG(INTEL_82543GC_PTC64, pDrvCtrl->staRegs.ptc64);
GEI_READ_REG(INTEL_82543GC_PTC127, pDrvCtrl->staRegs.ptc127);
GEI_READ_REG(INTEL_82543GC_PTC255, pDrvCtrl->staRegs.ptc255);
GEI_READ_REG(INTEL_82543GC_PTC511, pDrvCtrl->staRegs.ptc511);
GEI_READ_REG(INTEL_82543GC_PTC1023, pDrvCtrl->staRegs.ptc1023);
GEI_READ_REG(INTEL_82543GC_PTC1522, pDrvCtrl->staRegs.ptc1522);
GEI_READ_REG(INTEL_82543GC_MPTC, pDrvCtrl->staRegs.mptc);
GEI_READ_REG(INTEL_82543GC_BPTC, pDrvCtrl->staRegs.bptc);
GEI_READ_REG(INTEL_82543GC_TSCTC, pDrvCtrl->staRegs.tsctc);
GEI_READ_REG(INTEL_82543GC_TSCTFC, pDrvCtrl->staRegs.tsctfc);
GEI_READ_REG(INTEL_82543GC_RDFH, pDrvCtrl->staRegs.rdfh);
GEI_READ_REG(INTEL_82543GC_RDFT, pDrvCtrl->staRegs.rdft);
GEI_READ_REG(INTEL_82543GC_RDFHS, pDrvCtrl->staRegs.rdfhs);
GEI_READ_REG(INTEL_82543GC_RDFTS, pDrvCtrl->staRegs.rdfts);
GEI_READ_REG(INTEL_82543GC_RDFPC, pDrvCtrl->staRegs.rdfpc);
GEI_READ_REG(INTEL_82543GC_TDFH, pDrvCtrl->staRegs.tdfh);
GEI_READ_REG(INTEL_82543GC_TDFT, pDrvCtrl->staRegs.tdft);
GEI_READ_REG(INTEL_82543GC_TDFHS, pDrvCtrl->staRegs.tdfhs);
GEI_READ_REG(INTEL_82543GC_TDFTS, pDrvCtrl->staRegs.tdfts);
GEI_READ_REG(INTEL_82543GC_TDFPC, pDrvCtrl->staRegs.tdfpc);
return;
}
#ifdef INCLUDE_GEI82543_DEBUG_ROUTINE
/***************************************************************************
*
* gei82543StatusShow - show statistic registers
*
* This routine dumps and shows statistic registers
*
* RETURNS: N/A
*/
LOCAL void gei82543StatusShow
(
int unit /* device unit */
)
{
END_DEVICE * pDrvCtrl;
/* sanity check */
if (unit >= GEI543_MAX_DEV_UNIT)
{
printf ("Invalid unit numbern");
return;
}
pDrvCtrl = (END_DEVICE *) endFindByName (DEVICE_NAME, unit);
printf ("n");
printf ("*****************************************************n");
printf ("********** Intel 82543 status show ******************n");
printf ("*****************************************************n");
printf ("n");
/* get speed info */
gei82543SpeedGet (pDrvCtrl);
printf (" Device speed: ttt%dn", pDrvCtrl->speed);
/* get duplex info */
gei82543DuplexGet (pDrvCtrl);
printf (" Device duplex mode: tt%sn",
(pDrvCtrl->duplex == FULL_DUPLEX_MODE) ?
"Full duplex": "Half duplex mode");
/* get flow control info */
if (pDrvCtrl->flowCtrl == FLOW_CONTRL_TRANSMIT)
printf (" Flow control mode: tt%sn", "Transmit flow control");
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_RECEIVE)
printf (" Flow control mode: tt%sn", "RECEIVE flow control");
else if (pDrvCtrl->flowCtrl == FLOW_CONTRL_ALL)
printf (" Flow control mode: tt%sn",
"RECEIVE/TRANSMIT flow control");
else
printf (" Flow control mode: tt%sn", "No flow control");
printf ("n");
printf (" Tx descriptor tail index:t%dn", pDrvCtrl->txDescTail);
printf (" Rx descriptor tail index:t%dn", pDrvCtrl->rxDescTail);
printf (" Tx descriptor last check index:%dn",
pDrvCtrl->txDescLastCheck);
printf (" Tx descriptor available number:%dn",
pDrvCtrl->txDescFreeNum);
/* dump statistic registers */
gei82543HwStatusDump (pDrvCtrl);
/* print out statistic register */
printf ("n");
printf (" CRC error count: tt0x%xn", pDrvCtrl->staRegs.crcerrs);
printf (" Alignment error count: t0x%xn", pDrvCtrl->staRegs.algnerrc);
printf (" Symbol error count: tt0x%xn", pDrvCtrl->staRegs.symerrs);
printf (" RX error count: tt0x%xn", pDrvCtrl->staRegs.rxerrc);
printf (" Missed packet count: tt0x%xn", pDrvCtrl->staRegs.mpc);
printf (" Single collision count: t0x%xn", pDrvCtrl->staRegs.scc);
printf (" Excessive collision count: t0x%xn", pDrvCtrl->staRegs.ecol);
printf (" Multiple collision count: t0x%xn", pDrvCtrl->staRegs.mcc);
printf (" late collision count: tt0x%xn", pDrvCtrl->staRegs.latecol);
printf (" Collision count: tt0x%xn", pDrvCtrl->staRegs.colc);
printf (" Transmit underrun count: t0x%xn", pDrvCtrl->staRegs.tuc);
printf (" Defer count: ttt0x%xn", pDrvCtrl->staRegs.dc);
printf (" Transmit no CRS count: t0x%xn", pDrvCtrl->staRegs.tncrs);
printf (" Sequence error count: tt0x%xn", pDrvCtrl->staRegs.sec);
printf (" Carrier extension err count:t0x%xn",
pDrvCtrl->staRegs.cexteer);
printf (" Receive length error count: t0x%xn", pDrvCtrl->staRegs.rlec);
printf (" Xon receive count: tt0x%xn", pDrvCtrl->staRegs.xonrxc);
printf (" Xon transmit count: tt0x%xn", pDrvCtrl->staRegs.xontxc);
printf (" Xoff receive count: tt0x%xn", pDrvCtrl->staRegs.xoffrxc);
printf (" Xoff transmit count: tt0x%xn", pDrvCtrl->staRegs.xofftxc);
printf (" FC received unsupported count:t0x%xn",
pDrvCtrl->staRegs.fcruc);
printf ("n");
printf (" Packet received 64 byte count:tt0x%xn",
pDrvCtrl->staRegs.prc64);
printf (" Packet received 65-127 byte count:t0x%xn",
pDrvCtrl->staRegs.prc127);
printf (" Packet received 128-255 byte count:t0x%xn",
pDrvCtrl->staRegs.prc255);
printf (" Packet received 256-511 byte count:t0x%xn",
pDrvCtrl->staRegs.prc511);
printf (" Packet received 512-1023 byte count:t0x%xn",
pDrvCtrl->staRegs.prc1023);
printf (" Packet received 1024-1522 byte count:t0x%xn",
pDrvCtrl->staRegs.prc1522);
printf (" Good packet received count: tt0x%xn", pDrvCtrl->staRegs.gprc);
printf (" Broadcast packet received count:t0x%xn",pDrvCtrl->staRegs.bprc);
printf (" Multicast packet received count:t0x%xn",pDrvCtrl->staRegs.mprc);
printf ("n");
printf (" Good packet transmit count: tt0x%xn", pDrvCtrl->staRegs.gptc);
printf (" Good octets received count (lo):t0x%xn",pDrvCtrl->staRegs.gorl);
printf (" Good octets received count (hi):t0x%xn",pDrvCtrl->staRegs.gorh);
printf (" Good octets transmit count (lo):t0x%xn",pDrvCtrl->staRegs.gotl);
printf (" Good octets transmit count (hi):t0x%xn",pDrvCtrl->staRegs.goth);
printf (" Receive no buffer count: tt0x%xn", pDrvCtrl->staRegs.rnbc);
printf (" Receive under size count: tt0x%xn", pDrvCtrl->staRegs.ruc);
printf (" Receive fragment count: tt0x%xn", pDrvCtrl->staRegs.rfc);
printf (" Receive oversize count: tt0x%xn", pDrvCtrl->staRegs.roc);
printf (" Receive jabber count: ttt0x%xn", pDrvCtrl->staRegs.rjc);
printf (" Total octets receive(lo): tt0x%xn",pDrvCtrl->staRegs.torl);
printf (" Total octets receive(hi): tt0x%xn",pDrvCtrl->staRegs.torh);
printf (" Total octets transmit(lo):tt0x%xn",pDrvCtrl->staRegs.totl);
printf (" Total octets transmit(hi): tt0x%xn",pDrvCtrl->staRegs.toth);
printf (" Total packet receive: ttt0x%xn", pDrvCtrl->staRegs.tpr);
printf (" Total packet transmit: tt0x%xn", pDrvCtrl->staRegs.tpt);
printf ("n");
printf (" Packet transmit 64 byte count:tt0x%xn",
pDrvCtrl->staRegs.ptc64);
printf (" Packet transmit 65-127 byte count:t0x%xn",
pDrvCtrl->staRegs.ptc127);
printf (" Packet transmit 128-255 byte count:t0x%xn",
pDrvCtrl->staRegs.ptc255);
printf (" Packet transmit 256-511 byte count:t0x%xn",
pDrvCtrl->staRegs.ptc511);
printf (" Packet transmit 512-1023 byte count:t0x%xn",
pDrvCtrl->staRegs.ptc1023);
printf (" Packet transmit 1024-1522 byte count:t0x%xn",
pDrvCtrl->staRegs.ptc1522);
printf (" Multicast packet transmit count:t0x%xn",
pDrvCtrl->staRegs.mptc);
printf (" Broadcast packet transmit count:t0x%xn",
pDrvCtrl->staRegs.bptc);
printf ("n");
printf (" TCP segmentation context transmit count:t0x%xn",
pDrvCtrl->staRegs.tsctc);
printf (" TCP segmentation context transmit fail count:t0x%xn",
pDrvCtrl->staRegs.tsctfc);
printf (" receive data FIFO head: ttt0x%xn", pDrvCtrl->staRegs.rdfh);
printf (" receive data FIFO tail: ttt0x%xn", pDrvCtrl->staRegs.rdft);
printf (" receive data FIFO head save register: tt0x%xn",
pDrvCtrl->staRegs.rdfhs);
printf (" receive data FIFO tail save register: tt0x%xn",
pDrvCtrl->staRegs.rdfts);
printf (" receive data FIFO packet count:tt0x%xn",
pDrvCtrl->staRegs.rdfpc);
printf (" transmit data FIFO head: ttt0x%xn", pDrvCtrl->staRegs.tdfh);
printf (" transmit data FIFO tail: ttt0x%xn", pDrvCtrl->staRegs.tdft);
printf (" transmit data FIFO head save register: t0x%xn",
pDrvCtrl->staRegs.tdfhs);
printf (" transmit data FIFO tail save register: t0x%xn",
pDrvCtrl->staRegs.tdfts);
printf (" transmit data FIFO packet count:tt0x%xn",
pDrvCtrl->staRegs.tdfpc);
printf ("*************************************************************n");
return;
}
/****************************************************************************
*
* gei82543RegGet - get the specified register value in 82543 chip
*
* This routine gets and shows the specified register value in 82543 chip
*
* RETURNS: Register value
*/
LOCAL UINT32 gei82543RegGet
(
int unit, /* device unit */
UINT32 offset /* register offset */
)
{
UINT32 regVal;
END_DEVICE * pDrvCtrl;
if (unit >= GEI543_MAX_DEV_UNIT)
{
printf ("Invalid unit numbern");
return 0;
}
if (offset % 4 != 0)
{
printf ("Invalid register indexn");
return 0;
}
pDrvCtrl = (END_DEVICE *) endFindByName (DEVICE_NAME, unit);
GEI_READ_REG(offset, regVal);
printf ("unit: %d, register: 0x%x, value:0x%xn", unit, offset, regVal);
return regVal;
}
/****************************************************************************
*
* gei82543RegSet - set the specified register value
*
* This routine sets the specified register value
*
* RETURNS: N/A
*/
LOCAL void gei82543RegSet
(
int unit, /* device unit */
UINT32 offset, /* register offset */
UINT32 regVal /* value to write */
)
{
END_DEVICE * pDrvCtrl; /* driver structure */
if (unit >= GEI543_MAX_DEV_UNIT)
{
printf ("Invalid unit numbern");
return;
}
if (offset % 4 != 0)
{
printf ("Invalid register indexn");
return;
}
pDrvCtrl = (END_DEVICE *) endFindByName (DEVICE_NAME, unit);
GEI_WRITE_REG(offset, regVal);
return;
}
/****************************************************************************
*
* gei82543LedOn - turn on LED
*
* This routine turns LED on
*
* RETURNS: N/A
*/
LOCAL void gei82543LedOn
(
int unit /* device unit */
)
{
UINT32 ctrlRegVal; /* control register value */
END_DEVICE * pDrvCtrl; /* driver structure */
pDrvCtrl = (END_DEVICE *) endFindByName (DEVICE_NAME, unit);
GEI_READ_REG(INTEL_82543GC_CTRL, ctrlRegVal);
ctrlRegVal |= (CTRL_SWDPIO0_BIT | CTRL_SWDPIN0_BIT);
GEI_WRITE_REG(INTEL_82543GC_CTRL, ctrlRegVal);
return;
}
/***************************************************************************
*
* gei82543LedOff - turn off LED
*
* This routine turns LED off
*
* RETURNS: N/A
*/
LOCAL void gei82543LedOff
(
int unit /* device unit */
)
{
END_DEVICE * pDrvCtrl; /* driver structure */
UINT32 ctrlRegVal; /* control register value */
pDrvCtrl = (END_DEVICE *) endFindByName (DEVICE_NAME, unit);
GEI_READ_REG(INTEL_82543GC_CTRL, ctrlRegVal);
ctrlRegVal |= CTRL_SWDPIO0_BIT;
ctrlRegVal &= ~CTRL_SWDPIN0_BIT;
GEI_WRITE_REG(INTEL_82543GC_CTRL, ctrlRegVal);
return;
}
/***************************************************************************
*
* gei82543PhyRegGet - get the register value in PHY
*
* This routine returns the PHY's register value
*
* RETURNS: PHY's register value
*/
LOCAL UINT16 gei82543PhyRegGet
(
int unit, /* device unit */
int reg /* PHY's register */
)
{
END_DEVICE * pDrvCtrl; /* driver structure */
UINT16 tmp;
pDrvCtrl = (END_DEVICE *) endFindByName (DEVICE_NAME, unit);
if (pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD)
{
gei82543PhyRead (pDrvCtrl, pDrvCtrl->pPhyInfo->phyAddr, reg, &tmp);
}
else if (pDrvCtrl->adaptor.boardType == PRO1000_544_BOARD ||
pDrvCtrl->adaptor.boardType == PRO1000_546_BOARD)
{
gei82544PhyRead (pDrvCtrl, pDrvCtrl->pPhyInfo->phyAddr, reg, &tmp);
}
printf ("PHY Device, Reg:%d, value:0x%xn", reg, tmp);
return tmp;
}
/***************************************************************************
*
* gei82543PhyRegSet - set the register value in PHY
*
* This routine returns the PHY's register value
*
* RETURNS: PHY's register value
*/
LOCAL UINT16 gei82543PhyRegSet
(
int unit, /* device unit */
int reg, /* PHY's register */
UINT16 tmp
)
{
END_DEVICE * pDrvCtrl; /* driver structure */
pDrvCtrl = (END_DEVICE *) endFindByName (DEVICE_NAME, unit);
if (pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD)
{
gei82543PhyWrite (pDrvCtrl, pDrvCtrl->pPhyInfo->phyAddr, reg, tmp);
}
else if (pDrvCtrl->adaptor.boardType == PRO1000_544_BOARD ||
pDrvCtrl->adaptor.boardType == PRO1000_546_BOARD)
{
gei82544PhyWrite (pDrvCtrl, pDrvCtrl->pPhyInfo->phyAddr, reg, tmp);
}
printf ("PHY Device, Reg:%d, value:0x%xn", reg, tmp);
return tmp;
}
#ifdef INCLUDE_TBI_COMPATIBLE
/***************************************************************************
*
* gei82543TbiCompWr - enable/disable the TBI compatibility workaround
*
* This routine enables/disables TBI compatibility workaround if needed
*
* Input: unit - unit number of the gei device
* flag - 0 to turn off TBI compatibility, others to turn on
*
* RETURNS: N/A
*/
LOCAL void gei82543TbiCompWr
(
int unit, /* device unit */
int flag /* 0 - off, and others on */
)
{
END_DEVICE * pDrvCtrl; /* driver structure */
UINT32 rctlVal;
pDrvCtrl = (END_DEVICE *) endFindByName (DEVICE_NAME, unit);
GEI_READ_REG(INTEL_82543GC_RCTL, rctlVal);
gei82543SpeedGet (pDrvCtrl);
/* check conditions again */
if (flag)
{
pDrvCtrl->usrFlags |= GEI_END_TBI_COMPATIBILITY;
if (pDrvCtrl->adaptor.boardType == PRO1000_543_BOARD &&
pDrvCtrl->cableType == GEI_COPPER_MEDIA &&
pDrvCtrl->speed == MII_1000MBS)
{
pDrvCtrl->tbiCompatibility = TRUE;
GEI_WRITE_REG(INTEL_82543GC_RCTL, (rctlVal | RCTL_SBP_BIT));
CACHE_PIPE_FLUSH ();
printf ("TBI compatibility workaround is enabled for gei%dn", unit);
return;
}
}
else
{
pDrvCtrl->usrFlags &= ~GEI_END_TBI_COMPATIBILITY;
}
pDrvCtrl->tbiCompatibility = FALSE;
GEI_WRITE_REG(INTEL_82543GC_RCTL, (rctlVal & ~RCTL_SBP_BIT));
printf ("TBI compatibility workaround is not enabled for gei%dn", unit);
CACHE_PIPE_FLUSH ();
return;
}
#endif /* INCLUDE_TBI_COMPATIBLE */
#endif /* INCLUDE_GEI82543_DEBUG_ROUTINE */