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motFccEnd.c：源码内容

}
else
{
pTbdList = &pDrvCtrl->pTbdList[pDrvCtrl->usedTbdIndex];
/* free the Mblk or the cluster, whichever is appropriate */
if ((bdStatus & M8260_FETH_TBD_L) && (pBuf = pTbdList->pBuf))
{
motFccJobQAdd(pDrvCtrl, (FUNCPTR)motFccTxFreeJob,
(int) pDrvCtrl, (int) pBuf, pTbdList->info,
0, 0);
/* If motFccJobQueue() isn't on the netJobRing put it on */
if (!pDrvCtrl->txJobQState)
{
pDrvCtrl->txJobQState = TRUE;
netJobAdd((FUNCPTR)motFccJobQueue,
(int)pDrvCtrl, 0, 0, 0, 0);
}
}
pTbdList->pBuf = NULL;
pTbdList->info = 0;
++pDrvCtrl->cleanTbdNum;
pDrvCtrl->usedTbdIndex = (pDrvCtrl->usedTbdIndex + 1) %
(pDrvCtrl->tbdNum);
}
}
}
/* notify upper protocols TBDs are available */
if (pDrvCtrl->txStall &&
(pDrvCtrl->cleanTbdNum >= pDrvCtrl->unStallThresh))
{
MOT_FCC_LOG (MOT_FCC_DBG_TX,"Restart mux n",0,0,0,0,0,0);
if (netJobAdd ((FUNCPTR)muxTxRestart,(int)&pDrvCtrl->endObj,
0,0,0,0) == OK)
{
++pDrvCtrl->Stats->numStallsCleared;
pDrvCtrl->txStall = FALSE;
}
}
/* handle graceful transmit stop */
if (status & M8260_FEM_ETH_GRA)
{
MOT_FCC_LOG (MOT_FCC_DBG_INT,
"motFccInt: graceful stopn", 0, 0, 0, 0, 0, 0);
/* signal the Stop task that TX_STOP has happened */
MOT_FCC_GRA_SEM_GIVE;
}
if ((pDrvCtrl->RxBufCount && !pDrvCtrl->rxHandling) ||
(!pDrvCtrl->RxFree && pDrvCtrl->RxEmpty))
{
if (netJobAdd((FUNCPTR)motFccHandleRXFrames,
(int)pDrvCtrl,0,0,0,0)== OK)
{
pDrvCtrl->rxHandling = 1 ;
}
else
{
logMsg("netJobAdd((FUNCPTR)motFccHandleRXFrames() failed",
0,0,0,0,0,0);
}
}
++pDrvCtrl->Stats->numIsrExits;
}
/******************************************************************************
*
* motFccPhyLSCInt -
*
*
* RETURNS: None
*/
LOCAL void motFccPhyLSCInt
(
DRV_CTRL *pDrvCtrl
)
{
/* if no link status change job is pending */
if(!pDrvCtrl->lscHandling)
{
/* and the BSP has supplied a duplex mode function */
if(_func_motFccPhyDuplex)
{
if(!netJobAdd((FUNCPTR)motFccHandleLSCJob,(int)pDrvCtrl,0,0,0,0))
{
pDrvCtrl->lscHandling = 1;
}
}
else
{
/*
* If the BSP didn't supply a FUNC for getting duplex mode
* there's no reason to schedule the link status change job.
*/
}
}
}
/******************************************************************************
*
* motFccPktTransmit - transmit a packet
*
* This routine transmits the packet described by the given parameters
* over the network, without copying the mBlk to a driver buffer.
* It also updates statistics.
*
* RETURNS: OK, or ERROR if no resources were available.
*/
LOCAL STATUS motFccPktTransmit
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
M_BLK * pMblk, /* pointer to the mBlk */
UINT8 fragNum, /* number of fragments */
UINT16 pktType /* packet type */
)
{
int intLevel; /* current intr level */
int bufLen; /* length of this fragment */
char *pBuf; /* pointer to data to be sent */
FCC_BD *pTbd = NULL, *pFirst; /* pointer to the current ready TBD */
FCC_TBD_LIST *pTbdList = NULL; /* pointer to the TBD list*/
M_BLK *pCurr; /* holder for the current mBlk */
UINT16 status;
int workIx;
MOT_FCC_LOG(MOT_FCC_DBG_TX,"motFccPktTransmit...n",1,2,3,4,5,6);
++pDrvCtrl->Stats->numZcopySends;
pFirst = &pDrvCtrl->tbdBase[pDrvCtrl->tbdIndex];
status = 0;
pCurr = pMblk;
workIx = pDrvCtrl->tbdIndex;
while (pCurr)
{
/* for each mBlk fragment, set up a BD */
pTbd = &pDrvCtrl->tbdBase[workIx];
pTbdList = &pDrvCtrl->pTbdList[workIx];
pTbdList->pBuf = 0; /* clear the BD 'list' array */
pTbdList->info = 0; /* as we go through 'real' BDs */
pTbd->bdAddr = (ULONG)pBuf = pCurr->mBlkHdr.mData;
pTbd->bdLen = bufLen = pCurr->mBlkHdr.mLen;
if (workIx == (pDrvCtrl->tbdNum - 1))
{
pTbd->word1 = status | M8260_FETH_TBD_W;
}
else
{
pTbd->word1 = status;
}
MOT_FCC_CACHE_FLUSH(pBuf, bufLen); /* flush cache, if necessary */
/* bump the working BD index */
workIx = (workIx + 1) % pDrvCtrl->tbdNum;
pCurr = (M_BLK *)pCurr->mBlkHdr.mNext;
if(!status)
{
/* OR in the READY bit for rest of BDs */
status |= M8260_FETH_TBD_R;
}
}
/*
* we exited the above loop with pTbd pointing at the last BD
* of the frame, pFirst pointing at the first BD of the frame,
* and pTbdList pointing at the BD list element corresponding to
* the last BD for this frame. pTbd and pFirst will be the same
* when there is only one fragment in the mBlk chain.
*/
intLevel = intLock();
/* only the BD list element corresponding to the final 'real' BD */
/* (the last in a frame) gets any info -- all the others are cleared. */
/* store the Mblk pointer */
pTbdList->pBuf = pMblk;
/* so we know what to free in ISR */
pTbdList->info = (pktType | BUF_TYPE_MBLK);
/* keep accurate count of clean BDs */
pDrvCtrl->cleanTbdNum -= fragNum;
/* only update index while interrupts are disabled */
pDrvCtrl->tbdIndex = workIx;
pTbd->word1 |=
( M8260_FETH_TBD_R
| M8260_FETH_TBD_L
| M8260_FETH_TBD_TC
| M8260_FETH_TBD_I
| M8260_FETH_TBD_PAD
);
if(pTbd != pFirst)
{
/*
* if pTbd == pFirst, there is only one BD and we just
* set its READY bit -- it must not be set twice.
*/
pFirst->word1 |= M8260_FETH_TBD_R;
}
intUnlock (intLevel);
CACHE_PIPE_FLUSH (); /* Flush the write pipe */
return OK;
}
/******************************************************************************
*
* motFccPktCopyTransmit - copy and transmit a packet
*
* This routine transmits the packet described by the given parameters
* over the network, after copying the mBlk to the driver's buffer.
* It also updates statistics.
*
* RETURNS: OK, or END_ERR_BLOCK if no resources were available.
*/
LOCAL STATUS motFccPktCopyTransmit
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
M_BLK * pMblk, /* pointer to the mBlk */
UINT16 pktType /* packet type */
)
{
int intLevel; /* current intr level */
int len; /* length of data to be sent */
char *pBuf; /* pointer to data to be sent */
FCC_BD *pTbd; /* pointer to the current ready TBD */
FCC_TBD_LIST* pTbdList; /* pointer to the TBD list*/
MOT_FCC_LOG (MOT_FCC_DBG_TX, "motFccPktCopyTransmit...n",
1, 2, 3, 4, 5, 6);
pTbd = &pDrvCtrl->tbdBase[pDrvCtrl->tbdIndex];
pTbdList = &pDrvCtrl->pTbdList[pDrvCtrl->tbdIndex];
if(!(pBuf = NET_BUF_ALLOC()))
{
return END_ERR_BLOCK;
}
++pDrvCtrl->Stats->numNonZcopySends;
/* copy data and free the Mblk */
len = netMblkToBufCopy(pMblk,pBuf,NULL);
netMblkClChainFree(pMblk);
/* flush the cache, if necessary */
MOT_FCC_CACHE_FLUSH(pBuf,len);
pTbd->bdLen = len;
pTbd->bdAddr = (unsigned long)pBuf;
pTbdList->pBuf = pBuf; /* store the Cluster pointer */
pTbdList->info = (pktType | BUF_TYPE_CL); /* what to free in ISR */
intLevel = intLock();
pDrvCtrl->cleanTbdNum -= 1; /* keep accurate count of clean BDs */
if (pDrvCtrl->tbdIndex == (pDrvCtrl->tbdNum - 1))
{
pTbd->word1 =
( M8260_FETH_TBD_R
| M8260_FETH_TBD_L
| M8260_FETH_TBD_TC
| M8260_FETH_TBD_I
| M8260_FETH_TBD_W
| M8260_FETH_TBD_PAD
);
}
else
{
pTbd->word1 =
( M8260_FETH_TBD_R
| M8260_FETH_TBD_L
| M8260_FETH_TBD_TC
| M8260_FETH_TBD_I
| M8260_FETH_TBD_PAD
);
}
/* move on to the next element */
pDrvCtrl->tbdIndex = (pDrvCtrl->tbdIndex + 1) % pDrvCtrl->tbdNum;
intUnlock (intLevel);
CACHE_PIPE_FLUSH (); /* Flush the write pipe */
return OK;
}
/*******************************************************************************
* motFccSend - send an Ethernet packet
*
* This routine() takes a M_BLK_ID and sends off the data in the M_BLK_ID.
* The buffer must already have the addressing information properly installed
* in it. This is done by a higher layer.
*
* muxSend() calls this routine each time it wants to send a packet.
*
* RETURNS: OK, or END_ERR_BLOCK, if no resources are available, or ERROR,
* if the device is currently working in polling mode.
*/
LOCAL STATUS motFccSend
(
DRV_CTRL *pDrvCtrl, M_BLK *pMblk
)
{
int intLevel; /* current intr level */
int fragNum = 0; /* number of fragments in this mBlk */
UINT16 pktType = 0; /* packet type (unicast or multicast) */
M_BLK *pCurr;
BOOL zFlag;
MOT_FCC_LOG (MOT_FCC_DBG_TX, "motFccSend...n", 1, 2, 3, 4, 5, 6);
END_TX_SEM_TAKE(&pDrvCtrl->endObj, WAIT_FOREVER);
if (MOT_FCC_FLAG_ISSET(MOT_FCC_POLLING))
{ /* check device mode */
netMblkClChainFree(pMblk); /* free the given mBlk chain */
END_TX_SEM_GIVE(&pDrvCtrl->endObj);
errno = EINVAL;
return ERROR;
}
/* check we are not already stalled and have enough resources */
if (pDrvCtrl->txStall || (pDrvCtrl->cleanTbdNum < (MOT_FCC_TBD_MIN / 2)))
{
/* the choice of 1/2 min tbds as a stall threshold is arbitrary. */
goto tx_stall_exit;
}
if (pMblk->mBlkHdr.mData[0] & (UINT8)0x01)
{
pktType = PKT_TYPE_MULTI; /* packet type is multicast */
}
else
{
pktType = PKT_TYPE_UNI; /* packet type is unicast */
}
fragNum = -1;
if ((zFlag = pDrvCtrl->zeroBufFlag) )
{
if ((pCurr = pMblk) != NULL)
{
while(pCurr)
{
if(pCurr->mBlkHdr.mLen)
{
++fragNum;
pCurr = (M_BLK*)pCurr->mBlkHdr.mNext;
}
else
{
fragNum = 1; /* force a copy send */
zFlag = 0; /* force a copy send */
break;
}
}
++fragNum;
}
if(fragNum <= 0 || fragNum > (pDrvCtrl->tbdNum / 2))
{
netMblkClChainFree(pMblk); /* free the given mBlk chain */
END_ERR_ADD(&pDrvCtrl->endObj, MIB2_OUT_ERRS, +1);
END_TX_SEM_GIVE(&pDrvCtrl->endObj);
return ERROR;
}
}
else
{
fragNum = 1;
}
if(zFlag && pDrvCtrl->cleanTbdNum > fragNum)
{
/* transmit the packet in zero-copy mode */
if(motFccPktTransmit(pDrvCtrl, pMblk, fragNum, pktType) != OK)
{
goto tx_stall_exit;
}
}
else
{
/* transmit the packet in copy mode */
if(motFccPktCopyTransmit(pDrvCtrl, pMblk, pktType) != OK)
{
goto tx_stall_exit;
}
}
END_TX_SEM_GIVE(&pDrvCtrl->endObj);
MOT_FCC_LOG(MOT_FCC_DBG_TX, "motFccSend...Donen", 1, 2, 3, 4, 5, 6);
return OK;
tx_stall_exit:
END_ERR_ADD(&pDrvCtrl->endObj, MIB2_OUT_ERRS, +1);
intLevel = intLock();
if(!pDrvCtrl->txStall)
{
pDrvCtrl->txStall = TRUE;
++pDrvCtrl->Stats->numStallsEntered;
}
intUnlock (intLevel);
END_TX_SEM_GIVE (&pDrvCtrl->endObj);
return END_ERR_BLOCK;
}
/**************************************************************************
*
* motFccTbdInit - initialize the transmit buffer ring
*
* This routine initializes the transmit buffer descriptors ring.
*
* SEE ALSO: motFccRbdInit()
*
* RETURNS: OK, or ERROR.
*/
LOCAL STATUS motFccTbdInit
(
DRV_CTRL *pDrvCtrl
)
{
UINT16 ix; /* a counter */
FCC_BD *pTbd; /* generic TBD pointer */
/* carve up the shared-memory region */
pDrvCtrl->tbdBase = pTbd = (FCC_BD *)pDrvCtrl->pBdBase;
for(ix = 0; ix < pDrvCtrl->tbdNum; ix++)
{
pTbd->word1 = 0;
++pTbd;
}
/* set the wrap bit in last BD */
--pTbd;
pTbd->word1 = M8260_FETH_TBD_W;
/* get a cluster buffer from the pool */
pDrvCtrl->pTxPollBuf = NET_BUF_ALLOC();
if (pDrvCtrl->pTxPollBuf == NULL)
return ERROR;
return OK;
}
/******************************************************************************
*
* motFccHandleRXFrames - task-level receive frames processor
*
* This routine is run in netTask's context.
*
* RETURNS: N/A
*/
LOCAL void motFccHandleRXFrames
(
DRV_CTRL *pDrvCtrl
)
{
UINT16 rbdStatus = 0; /* holder for the status of this rbd */
BPOOL *bpoolp;
FCC_BD *pRbd;
M_BLK *pMblk; /* MBLK to send upstream */
CL_BLK *pClBlk; /* pointer to clBlk */
int len,s;
/* A replacement buffer for the current container */
char *pBuf;
char *pData; /* Data pointer for the current container */
void *retVal;
MOT_FCC_LOG (MOT_FCC_DBG_RX, "motFccHandleRecvInt: n", 0, 0, 0, 0, 0, 0);
++pDrvCtrl->Stats->numRXFHandlerEntries;
/*
* empty containers have no buffer associated with them.
* here, we try to get buffers for as many empties as can.
*/
while (pDrvCtrl->RxEmpty)
{
if (!(pBuf = NET_BUF_ALLOC()))
{
++pDrvCtrl->Stats->numRXFHandlerEmptyLoopBreaks;
break;
}
/*
* since the empty list is only manipulated here in this function,
* we don't need to lock out interrupts while we remove empties.
*/
bpoolp = pDrvCtrl->RxEmpty;
pDrvCtrl->RxEmpty = bpoolp->next;
bpoolp->pBuf = pBuf;
/* ISR code also manipulates the free list, so do intLock(). */
s = intLock(); /* start critical region */
bpoolp->next = pDrvCtrl->RxFree;
pDrvCtrl->RxFree = bpoolp;
intUnlock(s); /* end critical region */
}
pMblk = NULL;
pClBlk = NULL;
while (pDrvCtrl->RxBufCount)
{
if (!pMblk)
pMblk = NET_MBLK_ALLOC();
if (!pClBlk)
pClBlk = NET_CL_BLK_ALLOC();
if (!pMblk || !pClBlk)
{
/* If we couldn't obtain the resources to send this packet up
* the ladder right now, we'll just leave it at the head of the
* receive linked list and return.
* If either ptr is not NULL, it will be freed outside this loop.
*/
/* Tell the mux to give back some clusters */
pDrvCtrl->lastError.errCode = END_ERR_NO_BUF;
muxError(&pDrvCtrl->endObj, &pDrvCtrl->lastError);
MOT_FCC_RX_MEM_ADD(pDrvCtrl);
MOT_FCC_LOG (MOT_FCC_DBG_RX,
"motFccReceive mem problemn", 0, 0, 0, 0, 0, 0);
++pDrvCtrl->Stats->numRXFHandlerErrQuits;
break;
}
s = intLock(); /* start critical region */
bpoolp = pDrvCtrl->RxHead;
pDrvCtrl->RxHead = bpoolp->next; /* remove BD container from RX chain */
if ( --pDrvCtrl->RxBufCount == 0 )
{
pDrvCtrl->RxHead = NULL;
pDrvCtrl->RxTail = NULL;
}
intUnlock(s); /* end critical region */
/*
* At this point, the container is off the input chain
* take what we need out of it and, if the frame is OK,
* pass it up to the stack
*/
++pDrvCtrl->Stats->numRXFHandlerFramesProcessed;
pRbd = &bpoolp->desc;
/*
* Get the original cluster buffer address which we must pass to
* NET_CL_BLK_JOIN
*/
pBuf = bpoolp->pBuf;
/*
* get the actual receive buffer address -- the
* rounded-up-to-cache-boundary address
*/
pData = (char*)pRbd->bdAddr;
len = pRbd->bdLen;
rbdStatus = pRbd->word1;
if (rbdStatus & (M8260_FETH_RBD_MC|M8260_FETH_RBD_BC))
{
pDrvCtrl->endObj.mib2Tbl.ifInNUcastPkts += 1;
}
else
{
END_ERR_ADD(&pDrvCtrl->endObj, MIB2_IN_UCAST, +1);
}
/*
* Handle errata CPM-21... this code should NOT break the driver
* when CPM-21 is ultimately fixed.
*/
if ((rbdStatus &
(M8260_FETH_RBD_CL | M8260_FETH_RBD_CR)) == M8260_FETH_RBD_CL)
{
rbdStatus &= (UINT16)(~M8260_FETH_RBD_CL);
}
if(rbdStatus & MOT_FCC_RBD_ERR)
{
++pDrvCtrl->Stats->numRXFHandlerFramesRejected;
logMsg("RX addr = 0x%x Len = 0x%x Stat = 0x%xn",
(unsigned int)pData,len,rbdStatus,0,0,0);
/*
* This container already has a buffer in it, but contains a bad
* frame just put it back onto the free chain and we'll re-use
* the buffer
*/
s = intLock(); /* start critical region */
/* memset((void*)&bpoolp->desc,0,8); */
bpoolp->next = pDrvCtrl->RxFree;
pDrvCtrl->RxFree = bpoolp;
intUnlock(s); /* end critical region */
continue; /* go back and process remaining (if any) containers */
/*
* note that pMblk and pClBlk are not NULL and will be used in
* next iteration
*/
}
NET_CL_BLK_JOIN (pClBlk, pBuf, MOT_FCC_MAX_CL_LEN, retVal);
NET_MBLK_CL_JOIN(pMblk, pClBlk, retVal);
/*
* After joining the original cluster address, adjust the M_BLK to
* account for alignment
*/
pMblk->mBlkHdr.mData += ( (unsigned int)pData - (unsigned int)pBuf );
pMblk->mBlkHdr.mFlags |= M_PKTHDR; /* set the packet header flag */
pMblk->mBlkHdr.mLen = (len - MII_CRC_LEN) & ~0xc000;
pMblk->mBlkPktHdr.len = pMblk->mBlkHdr.mLen;
/* Make cache consistent with memory */
MOT_FCC_CACHE_INVAL(pData, pMblk->mBlkHdr.mLen);
/* send the frame to the upper layer */
END_RCV_RTN_CALL(&pDrvCtrl->endObj,pMblk);
CACHE_PIPE_FLUSH(); /* Flush the write pipe */
/* at this point, we're done with pMblk and pClBlk -- NULL them out */
pMblk = NULL;
pClBlk = NULL;
/* Now try to allocate a replacement buffer for the container */
pBuf = NET_BUF_ALLOC();
s = intLock(); /* start critical region */
/* memset((void*)&bpoolp->desc,0,8); */
if ((bpoolp->pBuf = pBuf))
{
/* buf_alloc succeeded */
bpoolp->next = pDrvCtrl->RxFree; /* put container on free list */
pDrvCtrl->RxFree = bpoolp;
}
else
{
bpoolp->next = pDrvCtrl->RxEmpty; /* buf_alloc failed */
pDrvCtrl->RxEmpty = bpoolp; /* put container on empty list */
}
intUnlock(s); /* end critical region */
}
s = intLock(); /* start critical region */
pDrvCtrl->rxHandling = FALSE;
++pDrvCtrl->Stats->numRXFHandlerExits;
intUnlock(s); /* end critical region */
/* if the only (or last) frame had an error, these pointers
* will not have been freed so do it now...
*/
if(pMblk)
NET_MBLK_FREE(pMblk);
if(pClBlk)
NET_CL_BLK_FREE(pClBlk);
MOT_FCC_LOG (MOT_FCC_DBG_RX, "motFccHandleRecvInt... Done, n",
0, 0, 0, 0, 0, 0);
}
/**************************************************************************
*
* motFccRbdInit - initialize the receive buffer ring
*
* This routine initializes the receive buffer descriptors ring.
*
* SEE ALSO: motFccTbdInit()
*
* RETURNS: OK, or ERROR if not enough clusters were available.
*/
LOCAL STATUS motFccRbdInit
(
DRV_CTRL *pDrvCtrl
)
{
char *pBuf; /* a rx data pointer */
FCC_BD *pRbd; /* generic rbd pointer */
BPOOL *bpoolp;
void **pRbuf;
int ix,nContainers;
nContainers = pDrvCtrl->rbdNum;
#define EXTRA_CONTAINERS 1
#if EXTRA_CONTAINERS
nContainers += pDrvCtrl->rbdNum /* / 2 */ ;
#endif
if (!pDrvCtrl->RxContainers)
{
pDrvCtrl->RxContainers = (BPOOL *)calloc(sizeof(BPOOL),nContainers + 1);
pDrvCtrl->RxFree = NULL;
pDrvCtrl->RxEmpty = NULL;
pDrvCtrl->RxHead = NULL;
pDrvCtrl->RxTail = NULL;
}
for (ix = 0; ix < nContainers; ix++)
{
if (!(pBuf = NET_BUF_ALLOC()))
{
logMsg("motFCCRbdInit() need more clustersn",0,0,0,0,0,0);
return ERROR;
}
bpoolp = &pDrvCtrl->RxContainers[ix];
bpoolp->pBuf = pBuf;
bpoolp->next = pDrvCtrl->RxFree;
pDrvCtrl->RxFree = bpoolp;
}
/* the receive ring is located right after the transmit ring */
pDrvCtrl->rbdBase = (FCC_BD *) (pDrvCtrl->pBdBase +
(MOT_FCC_TBD_SZ * pDrvCtrl->tbdNum));
pRbd = pDrvCtrl->rbdBase;
pRbuf = pDrvCtrl->rBufList;
for (ix = 0; ix < pDrvCtrl->rbdNum; ix++)
{
if (!(pBuf = NET_BUF_ALLOC()))
{
logMsg("motFCCRbdInit() need more clustersn",0,0,0,0,0,0);
return ERROR;
}
pRbd->bdLen = 0;
*pRbuf = pBuf;
pRbd->bdAddr = ROUND_UP( (unsigned long)pBuf, MOT_FCC_BUF_ALIGN );
pRbd->word1 = (M8260_FETH_RBD_E | M8260_FETH_RBD_I);
++pRbd;
++pRbuf;
}
--pRbd;
pRbd->word1 |= M8260_FETH_RBD_W;
return OK;
}
/**************************************************************************
*
* motFccBufFree - free the receive and transmit buffers
*
* This routine frees the netpool clusters associated with the receive
* buffer descriptors ring. It is called by motFccStop(), in order to
* properly release the driver's resources when the device is stopped.
*
* SEE ALSO: motFccStop()
*
* RETURNS: OK, always.
*/
LOCAL STATUS motFccBdFree
(
DRV_CTRL *pDrvCtrl
)
{
MOT_FCC_RBD_ID pRbd = NULL; /* generic rbd pointer */
void *pBuf;
UINT16 ix; /* a counter */
pRbd = (MOT_FCC_RBD_ID) (pDrvCtrl->rbdBase);
for (ix = 0; ix < pDrvCtrl->rbdNum; ix++)
{
/* return the cluster buffer to the pool */
if((pBuf = pDrvCtrl->rBufList[ix]))
NET_BUF_FREE(pBuf);
}
/* free lists and clusters */
for (ix = 0; ix < pDrvCtrl->tbdNum; ix++)
{
if((pBuf = pDrvCtrl->pTbdList[ix].pBuf))
{
/* free the Mblk or the cluster, whichever is appropriate */
if(pDrvCtrl->pTbdList[ix].info & BUF_TYPE_MBLK)
{
netMblkClChainFree((M_BLK*)pBuf);
}
else if(pDrvCtrl->pTbdList[ix].info & BUF_TYPE_CL)
{
NET_BUF_FREE(pBuf);
}
}
pDrvCtrl->pTbdList[ix].pBuf = NULL;
pDrvCtrl->pTbdList[ix].info = 0;
}
/* free the transmit poll buffer */
if ((pDrvCtrl->pTxPollBuf) != NULL)
NET_BUF_FREE ((UCHAR *) (pDrvCtrl->pTxPollBuf));
return OK;
}
/**************************************************************************
*
* motFccInit - initialize the chip
*
* This routine programs both the internal ram registers and the parameter
* RAM in the DPRAM for Ethernet operation. It calls motFccPramInit () and
* motFccIramInit () to do the job.
*
* SEE ALSO: motFccPramInit (), motFccIramInit ().
*
* RETURNS: OK, or ERROR.
*/
LOCAL STATUS motFccInit
(
DRV_CTRL *pDrvCtrl
)
{
/* initialize the parameter RAM for Ethernet operation */
if (motFccPramInit (pDrvCtrl) != OK)
return ERROR;
/* initialize the internal RAM for Ethernet operation */
if (motFccIramInit (pDrvCtrl) != OK)
return ERROR;
return OK;
}
/**************************************************************************
*
* motFccPramInit - initialize the parameter RAM for this FCC
*
* This routine programs the parameter ram registers for this FCC and set it
* to work for Ethernet operation. It follows the initialization sequence
* recommended in the MPC8260 PowerQuicc II User's Manual.
*
* SEE ALSO: motFccIramInit (), motFccInit ().
*
* RETURNS: OK, always.
*/
LOCAL STATUS motFccPramInit
(
DRV_CTRL *pDrvCtrl
)
{
UINT32 fcrVal;
FCC_PARAM_T *pParam;
FCC_ETH_PARAM_T *pEthPar;
/* get to the beginning of the parameter area */
pParam = pDrvCtrl->fccPar;
pEthPar = pDrvCtrl->fccEthPar;
memset(pParam,0,sizeof(*pParam));
/* figure out the value for the FCR registers */
fcrVal = MOT_FCC_FCR_DEF_VAL;
if (MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_BD_LBUS))
{
fcrVal |= M8260_FCR_BDB;
}
if (MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_BUF_LBUS))
{
fcrVal |= M8260_FCR_DTB;
}
fcrVal <<= M8260_FCR_SHIFT;
/* Allocate DPRAM memory for the riptr & tiptr */
if (MOT_FCC_USR_FLAG_ISSET(MOT_FCC_USR_DPRAM_ALOC))
{
/* Use auto allocation */
/* Test that function pointers are populated. */
if (_func_m82xxDpramFccMalloc == NULL || _func_m82xxDpramFree == NULL ||
_func_m82xxDpramFccFree == NULL )
{
return ERROR;
}
else
{
if ((pParam->riptr = (0xffff &
(ULONG)_func_m82xxDpramFccMalloc(32,32))) == 0)
{
return ERROR;
}
if ((pParam->tiptr = (0xffff &
(ULONG)_func_m82xxDpramFccMalloc(32,32))) == 0)
{
return ERROR;
}
}
}
else
{
/* Use hardcoded allocation */
pParam->riptr = MOT_FCC_RIPTR_VAL;
pParam->tiptr = MOT_FCC_TIPTR_VAL;
}
pParam->mrblr = 1536; /* MII_ETH_MAX_PCK_SZ; */
pParam->rstate = fcrVal;
pParam->rbase = (unsigned long)pDrvCtrl->rbdBase;
pParam->tstate = fcrVal;
pParam->tbase = (unsigned long)pDrvCtrl->tbdBase;
pEthPar->c_mask = MOT_FCC_C_MASK_VAL;
pEthPar->c_pres = MOT_FCC_C_PRES_VAL;
pEthPar->ret_lim = /* 4 */ MOT_FCC_RET_LIM_VAL;
pEthPar->maxflr = MII_ETH_MAX_PCK_SZ;
pEthPar->minflr = MOT_FCC_MINFLR_VAL;
pEthPar->maxd1 = MOT_FCC_MAXD_VAL;
pEthPar->maxd2 = MOT_FCC_MAXD_VAL;
pEthPar->pad_ptr = MOT_FCC_PAD_VAL;
/* program the individual physical address */
if (motFccAddrSet (pDrvCtrl, (UCHAR *) MOT_FCC_ADDR_GET (&pDrvCtrl->endObj),
M8260_FCC_PADDR_H_OFF) != OK)
{
return ERROR;
}
CACHE_PIPE_FLUSH (); /* Flush the write pipe */
return OK;
}
/**************************************************************************
*
* motFccIramInit - initialize the internal RAM for this FCC
*
* This routine programs the internal ram registers for this FCC and set it
* to work for Ethernet operation. It follows the initialization sequence
* recommended in the MPC8260 PowerQuicc II User's Manual. It also issues
* a rx/tx init command to the CP.
*
* SEE ALSO: motFccPramInit (), motFccInit ().
*
* RETURNS: OK, always.
*/
LOCAL STATUS motFccIramInit
(
DRV_CTRL *pDrvCtrl
)
{
UINT32 fccIramAddr = 0; /* a convenience */
UINT8 command = 0; /* command to issue to the CP */
fccIramAddr = pDrvCtrl->fccIramAddr;
/*
* program the GSMR, but enable neither the transmitter
* nor the receiver for now.
*/
#ifdef INCLUDE_GFMR_TCI
MOT_FCC_REG_LONG_WR (fccIramAddr + M8260_FCC_GFMR_OFF,
(M8260_GFMR_ETHERNET | M8260_GFMR_NORM
| M8260_GFMR_RENC_NRZ | M8260_GFMR_TCI));
#else
/* Leave TCI low to correct problem in 100Base-TX mode */
MOT_FCC_REG_LONG_WR (fccIramAddr + M8260_FCC_GFMR_OFF,
(M8260_GFMR_ETHERNET | M8260_GFMR_NORM
| M8260_GFMR_RENC_NRZ));
#endif
/* program the DSR */
MOT_FCC_REG_WORD_WR (fccIramAddr + M8260_FCC_FDSR_OFF, MOT_FCC_DSR_VAL);
/* zero-out the TODR for the sake of clarity */
MOT_FCC_REG_WORD_WR (fccIramAddr + M8260_FCC_FTODR_OFF, MOT_FCC_CLEAR_VAL);
/* the value for the FPSMR */
if (motFccFpsmrValSet (pDrvCtrl) != OK)
return ERROR;
/*
* we enable the following event interrupts:
* graceful transmit command;
* tx error;
* rx frame;
* busy condition;
* tx buffer, although we'll only enable the last TBD in a frame
* to generate interrupts. See motFccSend ();
*/
pDrvCtrl->intMask = (M8260_FEM_ETH_GRA | M8260_FEM_ETH_TXE
| M8260_FEM_ETH_RXF | M8260_FEM_ETH_BSY
| M8260_FEM_ETH_TXB);
MOT_FCC_REG_WORD_WR (fccIramAddr + M8260_FCC_FCCMR_OFF,
(pDrvCtrl->intMask));
/* clear all events */
MOT_FCC_REG_WORD_WR (fccIramAddr + M8260_FCC_FCCER_OFF, MOT_FCC_FCCE_VAL);
/* issue a init rx/tx command to the CP */
command = M8260_CPCR_RT_INIT;
return motFccCpcrCommand (pDrvCtrl, command);
}
/**************************************************************************
*
* motFccAddrSet - set an address to some internal register
*
* This routine writes the address pointed to by <pAddr> to some FCC's internal
* register. It may be used to set the individual physical address, or
* an address to be added to the hash table filter. It assumes that <offset>
* is the offset in the parameter RAM to the highest-order halfword that
* will contain the address.
*
* RETURNS: OK, always.
*/
LOCAL STATUS motFccAddrSet
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
UCHAR * pAddr, /* address to write to register */
UINT32 offset /* offset to highest-word in register */
)
{
UINT16 word; /* a convenience */
UINT32 fccPramAddr = 0; /* a convenience */
/* get to the beginning of the parameter area */
fccPramAddr = pDrvCtrl->fccPramAddr;
word = (((UINT16) (pAddr [5])) << 8) | (pAddr [4]);
MOT_FCC_REG_WORD_WR (fccPramAddr + offset,
word);
word = (((UINT16) (pAddr [3])) << 8) | (pAddr [2]);
MOT_FCC_REG_WORD_WR (fccPramAddr + offset + 2,
word);
word = (((UINT16) (pAddr [1])) << 8) | (pAddr [0]);
MOT_FCC_REG_WORD_WR (fccPramAddr + offset + 4,
word);
return (OK);
}
/**************************************************************************
*
* motFccFpsmrValSet - set the proper value for the FPSMR
*
* This routine finds out the proper value to be programmed in the
* FPSMR register by looking at some of the user/driver flags. It deals
* with options like promiscous mode, full duplex, loopback mode, RMON
* mode, and heartbeat control. It then writes to the FPSMR.
*
* SEE ALSO: motFccIramInit (), motFccInit ()
*
* RETURNS: OK, always.
*/
LOCAL STATUS motFccFpsmrValSet
(
DRV_CTRL *pDrvCtrl
)
{
UINT32 fpsmrVal = 0; /* a convenience */
UINT32 fccIramAddr = 0; /* a convenience */
/* get to the beginning of the internal memory for this FCC */
fccIramAddr = pDrvCtrl->fccIramAddr;
/* use the standard CCITT CRC */
fpsmrVal |= M8260_FPSMR_ETH_CRC_32;
/* set the heartbeat check if the user wants it */
if (MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_HBC))
{
fpsmrVal |= M8260_FPSMR_ETH_HBC;
MOT_FCC_LOG (MOT_FCC_DBG_START,
("motFccFpsmrValSet: heartbeat control n"),
0, 0, 0, 0, 0, 0);
}
else
{
fpsmrVal &= ~M8260_FPSMR_ETH_HBC;
}
/* set RMON mode if the user requests it */
if (MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_RMON))
{
fpsmrVal |= M8260_FPSMR_ETH_MON;
MOT_FCC_LOG (MOT_FCC_DBG_START,
("motFccFpsmrValSet: heartbeat control n"),
0, 0, 0, 0, 0, 0);
}
else
{
fpsmrVal &= ~M8260_FPSMR_ETH_MON;
}
/* deal with promiscous mode */
if (MOT_FCC_FLAG_ISSET (MOT_FCC_PROM))
{
fpsmrVal |= M8260_FPSMR_ETH_PRO;
MOT_FCC_LOG (MOT_FCC_DBG_START,
("motFccFpsmrValSet: promiscous mode n"),
0, 0, 0, 0, 0, 0);
}
else
{
fpsmrVal &= ~M8260_FPSMR_ETH_PRO;
}
/*
* Handle user's diddling with LPB first. That way, if we must
* set LPB due to FD it will stick.
*/
/*
* If the user wishes to go in external loopback mode,
* enable it. Do not enable internal loopback mode.
*/
if (MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_LOOP))
{
fpsmrVal |= M8260_FPSMR_ETH_LPB;
MOT_FCC_LOG (MOT_FCC_DBG_START,
("motFccFpsmrValSet: loopback mode n"), 0, 0, 0, 0, 0, 0);
}
else
{
fpsmrVal &= ~M8260_FPSMR_ETH_LPB;
}
/*
* Enable full duplex mode if the PHY was configured to work in
* full duplex mode.
*/
if (MOT_FCC_PHY_FLAGS_ISSET (MII_PHY_FD))
{
fpsmrVal |= (M8260_FPSMR_ETH_LPB | M8260_FPSMR_ETH_FDE);
MOT_FCC_LOG (MOT_FCC_DBG_START,
("motFccFpsmrValSet: full duplex n"), 0, 0, 0, 0, 0, 0);
}
else
{
fpsmrVal &= ~M8260_FPSMR_ETH_FDE;
}
MOT_FCC_REG_LONG_WR (fccIramAddr + M8260_FCC_FPSMR_OFF, fpsmrVal);
return OK;
}
/*******************************************************************************
* motFccIoctl - interface ioctl procedure
*
* Process an interface ioctl request.
*
* RETURNS: OK, or ERROR.
*/
LOCAL int motFccIoctl
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
int cmd, /* command to process */
caddr_t data /* pointer to data */
)
{
int error = OK;
INT8 savedFlags;
long value;
END_OBJ * pEndObj=&pDrvCtrl->endObj;
MOT_FCC_LOG (MOT_FCC_DBG_IOCTL,
("Ioctl unit=0x%x cmd=%d data=0x%xn"),
pDrvCtrl->unit, cmd, (int)data, 0, 0, 0);
switch (cmd)
{
case EIOCSADDR:
if (data == NULL)
error = EINVAL;
else
{
/* Copy and install the new address */
bcopy ((char *) data,
(char *) MOT_FCC_ADDR_GET (&pDrvCtrl->endObj),
MOT_FCC_ADDR_LEN_GET (&pDrvCtrl->endObj));
/* stop the FCC */
if (motFccStop (pDrvCtrl) != OK)
return (ERROR);
/* program the individual enet address */
if (motFccAddrSet (pDrvCtrl, (UCHAR *) data,
M8260_FCC_PADDR_H_OFF)
!= OK)
return (ERROR);
/* restart the FCC */
if (motFccStart (pDrvCtrl) != OK)
return (ERROR);
}
break;
case EIOCGADDR:
if (data == NULL)
error = EINVAL;
else
bcopy ((char *) MOT_FCC_ADDR_GET (&pDrvCtrl->endObj),
(char *) data,
MOT_FCC_ADDR_LEN_GET (&pDrvCtrl->endObj));
break;
case EIOCSFLAGS:
value = (long) data;
if (value < 0)
{
value = -value;
value--;
END_FLAGS_CLR (pEndObj, value);
}
else
END_FLAGS_SET (pEndObj, value);
MOT_FCC_LOG (MOT_FCC_DBG_IOCTL, ("endFlags=0x%x n"),
END_FLAGS_GET(pEndObj),
0, 0, 0, 0, 0);
/* handle IFF_PROMISC */
savedFlags = MOT_FCC_FLAG_GET();
if (END_FLAGS_ISSET (IFF_PROMISC))
{
MOT_FCC_FLAG_SET (MOT_FCC_PROM);
if ((MOT_FCC_FLAG_GET () != savedFlags) &&
(END_FLAGS_GET (pEndObj) & IFF_UP))
{
/* config down */
END_FLAGS_CLR (pEndObj, IFF_UP | IFF_RUNNING);
/* program the FPSMR to promiscous mode */
if (motFccFpsmrValSet (pDrvCtrl) == ERROR)
return (ERROR);
/* config up */
END_FLAGS_SET (pEndObj, IFF_UP | IFF_RUNNING);
}
}
else
MOT_FCC_FLAG_CLEAR (MOT_FCC_PROM);
MOT_FCC_LOG (MOT_FCC_DBG_IOCTL, ("EIOCSFLAGS: 0x%x: 0x%xn"),
pEndObj->flags, savedFlags,
0, 0, 0, 0);
break;
case EIOCGFLAGS:
MOT_FCC_LOG (MOT_FCC_DBG_IOCTL, ("EIOCGFLAGS: 0x%x: 0x%xn"),
pEndObj->flags, *(long *)data,
0, 0, 0, 0);
if (data == NULL)
error = EINVAL;
else
*(long *)data = END_FLAGS_GET(pEndObj);
break;
case EIOCMULTIADD:
error = motFccMCastAddrAdd (pDrvCtrl, (UCHAR *) data);
break;
case EIOCMULTIDEL:
error = motFccMCastAddrDel (pDrvCtrl, (UCHAR *) data);
break;
case EIOCMULTIGET:
error = motFccMCastAddrGet (pDrvCtrl, (MULTI_TABLE *) data);
break;
case EIOCPOLLSTART:
MOT_FCC_LOG (MOT_FCC_DBG_POLL, ("IOCTL call motFccPollStartn"),
0, 0, 0, 0, 0, 0);
motFccPollStart (pDrvCtrl);
break;
case EIOCPOLLSTOP:
MOT_FCC_LOG (MOT_FCC_DBG_POLL, ("IOCTL call motFccPollStopn"),
0, 0, 0, 0, 0, 0);
motFccPollStop (pDrvCtrl);
break;
case EIOCGMIB2:
if (data == NULL)
error=EINVAL;
else
bcopy ((char *) &pEndObj->mib2Tbl, (char *) data,
sizeof (pEndObj->mib2Tbl));
break;
default:
MOT_FCC_LOG (MOT_FCC_DBG_IOCTL, ("INVALID IO COMMAND!! n"),
0, 0, 0, 0, 0, 0);
error = EINVAL;
}
return (error);
}
/**************************************************************************
*
* motFccCpcrCommand - issue a command to the CP
*
* This routine issues the command specified in <command> to the Communication
* Processor (CP).
*
* RETURNS: OK, or ERROR if the command was unsuccessful.
*
*/
LOCAL STATUS motFccCpcrCommand
(
DRV_CTRL *pDrvCtrl, UINT8 command
)
{
UINT32 immrVal = pDrvCtrl->immrVal; /* holder for the immr value */
volatile UINT32 cpcrVal = 0; /* a convenience */
UINT32 ix = 0; /* a counter */
UINT8 fccNum = pDrvCtrl->fccNum; /* holder for the fcc number */
UINT8 fcc = fccNum - 1; /* a convenience */
/* wait until the CP is clear */
do {
MOT_FCC_REG_LONG_RD (M8260_CPCR (immrVal), cpcrVal);
if (ix++ == M8260_CPCR_LATENCY)
break;
} while (cpcrVal & M8260_CPCR_FLG);
if (ix >= M8260_CPCR_LATENCY)
{
MOT_FCC_LOG (MOT_FCC_DBG_ANY,
"motFccCpcrCommand: cpcr problem n", 0, 0, 0, 0, 0, 0);
return ERROR;
}
/* issue the command to the CP */
cpcrVal = (M8260_CPCR_OP (command)
| M8260_CPCR_SBC (M8260_CPCR_SBC_FCC1 | (fcc * 0x1))
| M8260_CPCR_PAGE (M8260_CPCR_PAGE_FCC1 | (fcc * 0x1))
| M8260_CPCR_MCN (M8260_CPCR_MCN_ETH)
| M8260_CPCR_FLG);
MOT_FCC_LOG (MOT_FCC_DBG_START,
"motFccCpcrCommand: cpcr=0x%x n", cpcrVal, 0, 0, 0, 0, 0);
MOT_FCC_REG_LONG_WR (M8260_CPCR (immrVal), cpcrVal);
CACHE_PIPE_FLUSH (); /* Flush the write pipe */
/* wait until the CP is clear */
ix = 0;
do {
MOT_FCC_REG_LONG_RD (M8260_CPCR (immrVal), cpcrVal);
if (ix++ == M8260_CPCR_LATENCY)
break;
} while (cpcrVal & M8260_CPCR_FLG) ;
if (ix >= M8260_CPCR_LATENCY)
{
MOT_FCC_LOG (MOT_FCC_DBG_ANY,
"motFccCpcrCommand: cpcr problem n", 0, 0, 0, 0, 0, 0);
return ERROR;
}
MOT_FCC_LOG (MOT_FCC_DBG_START,
"motFccCpcrCommand: done n", 0, 0, 0, 0, 0, 0);
return OK;
}
/**************************************************************************
*
* motFccMiiRead - read the MII interface
*
* This routine reads the register specified by <phyReg> in the PHY device
* whose address is <phyAddr>. The value read is returned in the location
* pointed to by <miiData>.
*
* SEE ALSO: motFccMiiWrite()
*
* RETURNS: OK, or ERROR.
*
*/
LOCAL STATUS motFccMiiRead
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
UINT8 phyAddr, /* the PHY being read */
UINT8 regAddr, /* the PHY's register being read */
UINT16 * miiData /* value read from the MII interface */
)
{
UINT16 temp = 0; /* temporary variable */
/* write the preamble pattern first */
MOT_FCC_MII_WR (MII_MF_PREAMBLE, MII_MF_PREAMBLE_LEN);
/* write the start of frame */
MOT_FCC_MII_WR (MII_MF_ST, MII_MF_ST_LEN);
/* write the operation code */
MOT_FCC_MII_WR (MII_MF_OP_RD, MII_MF_OP_LEN);
/* write the PHY address */
MOT_FCC_MII_WR (phyAddr, MII_MF_ADDR_LEN);
/* write the PHY register */
MOT_FCC_MII_WR (regAddr, MII_MF_REG_LEN);
/* write the turnaround pattern */
SYS_FCC_MII_BIT_WR ((INT32) NONE);
SYS_FCC_MII_BIT_WR (0);
/* read the data on the MDIO */
MOT_FCC_MII_RD (temp, MII_MF_DATA_LEN);
/* leave it in idle state */
SYS_FCC_MII_BIT_WR ((INT32) NONE);
*miiData = temp;
MOT_FCC_LOG (MOT_FCC_DBG_MII, ("motFccMiiRead reg=%d
PHY=%d data=0x%xn"),
regAddr, phyAddr, *miiData, 0, 0, 0);
return (OK);
}
/**************************************************************************
*
* motFccMiiWrite - write to the MII register
*
* This routine writes the register specified by <phyReg> in the PHY device,
* whose address is <phyAddr>, with the 16-bit value included in <miiData>.
*
* SEE ALSO: motFccMiiRead()
*
* RETURNS: OK, or ERROR.
*/
LOCAL STATUS motFccMiiWrite
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
UINT8 phyAddr, /* the PHY being written */
UINT8 regAddr, /* the PHY's register being written */
UINT16 miiData /* value written to the MII interface */
)
{
/* write the preamble pattern first */
MOT_FCC_MII_WR (MII_MF_PREAMBLE, MII_MF_PREAMBLE_LEN);
/* write the start of frame */
MOT_FCC_MII_WR (MII_MF_ST, MII_MF_ST_LEN);
/* write the operation code */
MOT_FCC_MII_WR (MII_MF_OP_WR, MII_MF_OP_LEN);
/* write the PHY address */
MOT_FCC_MII_WR (phyAddr, MII_MF_ADDR_LEN);
/* write the PHY register */
MOT_FCC_MII_WR (regAddr, MII_MF_REG_LEN);
/* write the turnaround pattern */
SYS_FCC_MII_BIT_WR (1);
SYS_FCC_MII_BIT_WR (0);
/* write the data on the MDIO */
MOT_FCC_MII_WR (miiData, MII_MF_DATA_LEN);
/* leave it in idle state @@@ */
SYS_FCC_MII_BIT_WR ((INT32) NONE);
MOT_FCC_LOG (MOT_FCC_DBG_MII, ("motFccMiiWrite reg=%d
PHY=%d data=0x%xn"),
regAddr, phyAddr, miiData, 0, 0, 0);
return (OK);
}
/**************************************************************************
*
* motFccPhyPreInit - initialize some fields in the phy info structure
*
* This routine initializes some fields in the phy info structure,
* for use of the phyInit() routine.
*
* RETURNS: OK, or ERROR if could not obtain memory.
*/
LOCAL STATUS motFccPhyPreInit
(
DRV_CTRL * pDrvCtrl /* pointer to DRV_CTRL structure */
)
{
/* set some default values */
pDrvCtrl->phyInfo->pDrvCtrl = (void *) pDrvCtrl;
/* in case of link failure, set a default mode for the PHY */
pDrvCtrl->phyInfo->phyFlags = MII_PHY_DEF_SET;
pDrvCtrl->phyInfo->phyWriteRtn = (FUNCPTR) motFccMiiWrite;
pDrvCtrl->phyInfo->phyReadRtn = (FUNCPTR) motFccMiiRead;
pDrvCtrl->phyInfo->phyDelayRtn = (FUNCPTR) taskDelay;
pDrvCtrl->phyInfo->phyMaxDelay = MII_PHY_DEF_DELAY;
pDrvCtrl->phyInfo->phyDelayParm = 1;
/* handle some user-to-physical flags */
if (!(MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_PHY_NO_AN)))
MOT_FCC_PHY_FLAGS_SET (MII_PHY_AUTO);
else
MOT_FCC_PHY_FLAGS_CLEAR (MII_PHY_AUTO);
if (MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_PHY_TBL))
MOT_FCC_PHY_FLAGS_SET (MII_PHY_TBL);
else
MOT_FCC_PHY_FLAGS_CLEAR (MII_PHY_TBL);
if (!(MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_PHY_NO_100)))
MOT_FCC_PHY_FLAGS_SET (MII_PHY_100);
else
MOT_FCC_PHY_FLAGS_CLEAR (MII_PHY_100);
if (!(MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_PHY_NO_FD)))
MOT_FCC_PHY_FLAGS_SET (MII_PHY_FD);
else
MOT_FCC_PHY_FLAGS_CLEAR (MII_PHY_FD);
if (!(MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_PHY_NO_10)))
MOT_FCC_PHY_FLAGS_SET (MII_PHY_10);
else
MOT_FCC_PHY_FLAGS_CLEAR (MII_PHY_10);
if (!(MOT_FCC_USR_FLAG_ISSET (MOT_FCC_USR_PHY_NO_HD)))
MOT_FCC_PHY_FLAGS_SET (MII_PHY_HD);
else
MOT_FCC_PHY_FLAGS_CLEAR (MII_PHY_HD);
/* mark it as pre-initilized */
MOT_FCC_PHY_FLAGS_SET (MII_PHY_PRE_INIT);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("motFccPhyPreInit phyInfo = 0x%x read=0x%x
write=0x%x tbl=0x%x addr=0x%x
flags=0x%x n"),
(int) pDrvCtrl->phyInfo,
(int) pDrvCtrl->phyInfo->phyReadRtn,
(int) pDrvCtrl->phyInfo->phyWriteRtn,
(int) pDrvCtrl->phyInfo->phyAnOrderTbl,
(int) pDrvCtrl->phyInfo->phyAddr,
(int) pDrvCtrl->phyInfo->phyFlags);
return (OK);
}
/*******************************************************************************
* motFccMCastAddrAdd - add a multicast address for the device
*
* This routine adds a multicast address to whatever the driver
* is already listening for.
*
* SEE ALSO: motFccMCastAddrDel() motFccMCastAddrGet()
*
* RETURNS: OK or ERROR.
*/
LOCAL STATUS motFccMCastAddrAdd
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
UCHAR * pAddr /* address to be added */
)
{
int retVal; /* convenient holder for return value */
MOT_FCC_LOG (MOT_FCC_DBG_IOCTL, ("motFccMCastAddrAdd addr = 0x%x 0x%x
0x%x 0x%x 0x%x 0x%xn"),
(int) *(UCHAR*) (pAddr + 0),
(int) *(UCHAR*) (pAddr + 1),
(int) *(UCHAR*) (pAddr + 2),
(int) *(UCHAR*) (pAddr + 3),
(int) *(UCHAR*) (pAddr + 4),
(int) *(UCHAR*) (pAddr + 5));
retVal = etherMultiAdd (&pDrvCtrl->endObj.multiList, pAddr);
if (retVal == ENETRESET)
{
pDrvCtrl->endObj.nMulti++;
return (motFccHashTblAdd (pDrvCtrl, pAddr));
}
return ((retVal == OK) ? OK : ERROR);
}
/*****************************************************************************
*
* motFccMCastAddrDel - delete a multicast address for the device
*
* This routine deletes a multicast address from the current list of
* multicast addresses.
*
* SEE ALSO: motFccMCastAddrAdd() motFccMCastAddrGet()
*
* RETURNS: OK or ERROR.
*/
LOCAL STATUS motFccMCastAddrDel
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
UCHAR * pAddr /* address to be deleted */
)
{
int retVal; /* convenient holder for return value */
MOT_FCC_LOG (MOT_FCC_DBG_IOCTL, ("motFccMCastAddrDel addr = 0x%x 0x%x
0x%x 0x%x 0x%x 0x%xn"),
(int) *(pAddr + 0), (int) *(pAddr + 1),
(int) *(pAddr + 2), (int) *(pAddr + 3),
(int) *(pAddr + 4), (int) *(pAddr + 5));
retVal = etherMultiDel (&pDrvCtrl->endObj.multiList, pAddr);
if (retVal == ENETRESET)
{
pDrvCtrl->endObj.nMulti--;
/* stop the FCC */
if (motFccStop (pDrvCtrl) != OK)
return (ERROR);
/* populate the hash table */
retVal = motFccHashTblPopulate (pDrvCtrl);
/* restart the FCC */
if (motFccStart (pDrvCtrl) != OK)
return (ERROR);
}
return ((retVal == OK) ? OK : ERROR);
}
/*******************************************************************************
* motFccMCastAddrGet - get the current multicast address list
*
* This routine returns the current multicast address list in <pTable>
*
* SEE ALSO: motFccMCastAddrAdd() motFccMCastAddrDel()
*
* RETURNS: OK or ERROR.
*/
LOCAL STATUS motFccMCastAddrGet
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
MULTI_TABLE *pTable /* table into which to copy addresses */
)
{
MOT_FCC_LOG (MOT_FCC_DBG_IOCTL, ("motFccMCastAddrGetn"),
0, 0, 0, 0, 0, 0);
return (etherMultiGet (&pDrvCtrl->endObj.multiList, pTable));
}
/*******************************************************************************
* motFccHashTblAdd - add an entry to the hash table
*
* This routine adds an entry to the hash table for the address pointed to
* by <pAddr>.
*
* RETURNS: OK, or ERROR.
*/
LOCAL STATUS motFccHashTblAdd
(
DRV_CTRL * pDrvCtrl, /* pointer to DRV_CTRL structure */
UCHAR * pAddr /* address to be added */
)
{
UINT8 command = 0; /* command to issue to the CP */
MOT_FCC_LOG (MOT_FCC_DBG_IOCTL, ("motFccHashTblAdd addr = 0x%x 0x%x
0x%x 0x%x 0x%x 0x%xn"),
(int) *(pAddr + 0), (int) *(pAddr + 1),
(int) *(pAddr + 2), (int) *(pAddr + 3),
(int) *(pAddr + 4), (int) *(pAddr + 5));
/* program the group enet address */
if (motFccAddrSet (pDrvCtrl, (UCHAR *) pAddr,
M8260_FCC_TADDR_H_OFF) != OK)
return (ERROR);
/* issue a set group address command to the CP */
command = M8260_CPCR_SET_GROUP;
if (motFccCpcrCommand (pDrvCtrl, command) == ERROR)
return (ERROR);
MOT_FCC_LOG (MOT_FCC_DBG_IOCTL, ("motFccHashTblAdd endn"),
0, 0, 0, 0, 0, 0);
return (OK);
}
/*******************************************************************************
* motFccHashTblPopulate - populate the hash table
*
* This routine populates the hash table with the entries found in the
* multicast table. We have to reset the hash registers first, and
* populate them again, as more than one address may be mapped to
* the same bit.
*
* RETURNS: OK, or ERROR.
*/
LOCAL STATUS motFccHashTblPopulate
(
DRV_CTRL * pDrvCtrl /* pointer to DRV_CTRL structure */
)
{
ETHER_MULTI * mCastNode = NULL;
UINT32 fccPramAddr = 0; /* a convenience */
/* get to the beginning of the parameter area */
fccPramAddr = pDrvCtrl->fccPramAddr;
/* reset the hash table registers first */
MOT_FCC_REG_LONG_WR (fccPramAddr + M8260_FCC_GADDR_H_OFF,
MOT_FCC_CLEAR_VAL);
MOT_FCC_REG_LONG_WR (fccPramAddr + M8260_FCC_GADDR_L_OFF,
MOT_FCC_CLEAR_VAL);
/* scan the multicast address list */
for (mCastNode = (ETHER_MULTI *) lstFirst (&pDrvCtrl->endObj.multiList);
mCastNode != NULL;
mCastNode = (ETHER_MULTI *) lstNext (&mCastNode->node))
{
/* add this entry */
if (motFccHashTblAdd (pDrvCtrl, mCastNode->addr) == ERROR)
return (ERROR);
}
return (OK);
}
/*****************************************************************************
*
* motFccPollSend - transmit a packet in polled mode
*
* This routine is called by a user to try and send a packet on the
* device. It sends a packet directly on the network, without having to
* go through the normal process of queuing a packet on an output queue
* and then waiting for the device to decide to transmit it.
*
* These routine should not call any kernel functions.
*
* SEE ALSO: motFccPollReceive()
*
* RETURNS: OK or EAGAIN.
*/
LOCAL STATUS motFccPollSend
(
DRV_CTRL *pDrvCtrl, M_BLK_ID pMblk
)
{
UINT16 pktType = 0; /* packet type (unicast or multicast) */
int retVal = OK; /* holder for return value */
char *pBuf = NULL; /* pointer to data to be sent */
FCC_BD *pTbd = NULL; /* pointer to the current ready TBD */
int ix = 0; /* a counter */
int len = 0; /* length of data to be sent */
UINT16 tbdStatus; /* holder for the TBD status */
MOT_FCC_LOG (MOT_FCC_DBG_POLL, ("motFccPollSendn"), 0, 0, 0, 0, 0, 0);
if (!pMblk)
{
END_ERR_ADD (&pDrvCtrl->endObj, MIB2_OUT_ERRS, +1);
return EAGAIN;
}
if (pMblk->mBlkHdr.mData[0] & (UINT8)0x01)
{
pktType = PKT_TYPE_MULTI; /* packet type is multicast */
}
else
{
pktType = PKT_TYPE_UNI; /* packet type is unicast */
}
pTbd = &pDrvCtrl->tbdBase[pDrvCtrl->tbdIndex];
pBuf = pDrvCtrl->pTxPollBuf;
/* copy data but do not free the Mblk */
len = netMblkToBufCopy (pMblk, (char *) pBuf, NULL);
len = max(MOT_FCC_MIN_TX_PKT_SZ, len);
MOT_FCC_CACHE_FLUSH (pBuf, len); /* flush the cache, if necessary */
pTbd->bdAddr = (unsigned long)pBuf;
pTbd->bdLen = len;
if (pDrvCtrl->tbdIndex == (pDrvCtrl->tbdNum - 1))
{
pTbd->word1 = (M8260_FETH_TBD_R | M8260_FETH_TBD_L | M8260_FETH_TBD_TC | M8260_FETH_TBD_PAD | M8260_FETH_TBD_W);
}
else
{
pTbd->word1 = (M8260_FETH_TBD_R | M8260_FETH_TBD_L | M8260_FETH_TBD_TC |
M8260_FETH_TBD_PAD);
}
CACHE_PIPE_FLUSH (); /* Flush the write pipe */
ix = 0;
while ((tbdStatus = pTbd->word1) & M8260_FETH_TBD_R)
{
CACHE_PIPE_FLUSH (); /* Flush the write pipe */
if(++ix == MOT_FCC_WAIT_MAX)
{
END_ERR_ADD (&pDrvCtrl->endObj, MIB2_OUT_ERRS, +1);
return EAGAIN; /* going to need to do way more than this */
}
}
if (tbdStatus & (M8260_FETH_TBD_LC | M8260_FETH_TBD_RL |
M8260_FETH_TBD_UN | M8260_FETH_TBD_HB | M8260_FETH_TBD_CSL))
{
END_ERR_ADD (&pDrvCtrl->endObj, MIB2_OUT_ERRS, +1);
#ifdef MOT_FCC_DBG
if ((tbdStatus & M8260_FETH_TBD_LC))
{
MOT_FCC_LOG (MOT_FCC_DBG_TX,
("motFccTbdCheck: late collisionn"),
1, 2, 3, 4, 5, 6);
++pDrvCtrl->Stats->motFccTxLcErr;
}
if ((tbdStatus & M8260_FETH_TBD_RL))
{
MOT_FCC_LOG (MOT_FCC_DBG_TX,
("motFccTbdCheck: retransmit limitn"),
1, 2, 3, 4, 5, 6);
++pDrvCtrl->Stats->motFccTxRlErr;
}
if ((tbdStatus & M8260_FETH_TBD_UN))
{
MOT_FCC_LOG (MOT_FCC_DBG_TX,
("motFccTbdCheck: tx underrunn"), 1, 2, 3, 4, 5, 6);
++pDrvCtrl->Stats->motFccTxUrErr;
}
if ((tbdStatus & M8260_FETH_TBD_CSL))
{
MOT_FCC_LOG (MOT_FCC_DBG_TX,
("motFccTbdCheck: carrier sensen"), 1, 2, 3, 4, 5, 6);
++pDrvCtrl->Stats->motFccTxCslErr;
}
#endif /* MOT_FCC_DBG */
retVal = EAGAIN;
}
else
{
/* up-date statistics */
if(pktType == PKT_TYPE_MULTI)
{
pDrvCtrl->endObj.mib2Tbl.ifOutNUcastPkts += 1;
}
else
{
END_ERR_ADD(&pDrvCtrl->endObj, MIB2_OUT_UCAST, +1);
}
retVal = OK;
}
/* clean this buffer descriptor, mirror motFccTbdInit() */
if (pDrvCtrl->tbdIndex == (pDrvCtrl->tbdNum - 1))
{
pTbd->word1 = M8260_FETH_TBD_W;
}
else
{
pTbd->word1 = 0;
}
CACHE_PIPE_FLUSH (); /* Flush the write pipe */
/* update some indices for correct handling of the TBD ring */
pDrvCtrl->tbdIndex = (pDrvCtrl->tbdIndex + 1) % (pDrvCtrl->tbdNum);
pDrvCtrl->usedTbdIndex = (pDrvCtrl->usedTbdIndex + 1) % (pDrvCtrl->tbdNum);
return retVal;
}
/*******************************************************************************
* motFccPollReceive - receive a packet in polled mode
*
* This routine is called by a user to try and get a packet from the
* device. It returns EAGAIN if no packet is available. The caller must
* supply a M_BLK_ID with enough space to contain the received packet. If
* enough buffer is not available then EAGAIN is returned.
*
* These routine should not call any kernel functions.
*
* SEE ALSO: motFccPollSend()
*
* RETURNS: OK or EAGAIN.
*/
LOCAL STATUS motFccPollReceive
(
DRV_CTRL *pDrvCtrl, M_BLK *pMblk
)
{
int retVal = OK; /* holder for return value */
FCC_BD *pRbd = NULL; /* generic rbd pointer */
UINT16 rbdStatus = 0; /* holder for the status of this RBD */
UINT16 rbdLen = 0; /* number of bytes received */
char *pData = NULL; /* a rx data pointer */
MOT_FCC_LOG (MOT_FCC_DBG_POLL, ("motFccPollReceiven"), 0, 0, 0, 0, 0, 0);
if ((pMblk->mBlkHdr.mFlags & M_EXT) != M_EXT)
return EAGAIN;
/* get the first available RBD */
pRbd = &pDrvCtrl->rbdBase[pDrvCtrl->rbdIndex];
rbdStatus = pRbd->word1; /* read the RBD status word */
rbdLen = pRbd->bdLen; /* get the actual amount of received data */
/* if it's not ready, don't touch it! */
if ((rbdStatus & M8260_FETH_RBD_E))
return EAGAIN;
/* up-date statistics */
if (rbdStatus & (M8260_FETH_RBD_MC|M8260_FETH_RBD_BC) )
{
pDrvCtrl->endObj.mib2Tbl.ifInNUcastPkts += 1;
}
else
{
END_ERR_ADD(&pDrvCtrl->endObj, MIB2_IN_UCAST, +1);
}
/*
* Handle errata CPM-21... this code should NOT break the driver
* when CPM-21 is ultimately fixed.
*/
if ((rbdStatus & (M8260_FETH_RBD_CL | M8260_FETH_RBD_CR)) ==
M8260_FETH_RBD_CL)
{
rbdStatus &= (UINT16)(~M8260_FETH_RBD_CL);
}
/*
* pass the packet up only if reception was Ok AND buffer is large enough, */
if ((rbdStatus & MOT_FCC_RBD_ERR) || pMblk->mBlkHdr.mLen < rbdLen)
{
MOT_FCC_LOG (MOT_FCC_DBG_POLL,
("motFccReceive: bad rbdn"), 1, 2, 3, 4, 5, 6);
END_ERR_ADD (&pDrvCtrl->endObj, MIB2_IN_ERRS, +1);
retVal = EAGAIN;
}
else
{
pData = (char*)pRbd->bdAddr;
/* set up the mBlk properly */
pMblk->mBlkHdr.mFlags |= M_PKTHDR;
pMblk->mBlkHdr.mLen = (rbdLen - MII_CRC_LEN) & ~0xc000;
pMblk->mBlkPktHdr.len = pMblk->mBlkHdr.mLen;
/* Make cache consistent with memory */
MOT_FCC_CACHE_INVAL ((char *) pData, pMblk->mBlkHdr.mLen);
bcopy ((char *) pData, (char *) pMblk->mBlkHdr.mData,
((rbdLen - MII_CRC_LEN) & ~0xc000));
retVal = OK;
}
pRbd->bdLen = 0;
/* up-date the status word: treat the last RBD in the ring differently */
if ((pDrvCtrl->rbdIndex) == (pDrvCtrl->rbdNum - 1))
{
pRbd->word1 = M8260_FETH_RBD_W | M8260_FETH_RBD_E | M8260_FETH_RBD_I;
}
else
{
pRbd->word1 = M8260_FETH_RBD_E | M8260_FETH_RBD_I;
}
/* move on to the next used RBD */
pDrvCtrl->rbdIndex = (pDrvCtrl->rbdIndex + 1) % (pDrvCtrl->rbdNum);
return retVal;
}
/*******************************************************************************
* motFccPollStart - start polling mode
*
* This routine starts polling mode by disabling ethernet interrupts and
* setting the polling flag in the END_CTRL stucture.
*
* SEE ALSO: motFccPollStop()
*
* RETURNS: OK, or ERROR if polling mode could not be started.
*/
LOCAL STATUS motFccPollStart
(
DRV_CTRL * pDrvCtrl /* pointer to DRV_CTRL structure */
)
{
int intLevel; /* current intr level */
int retVal; /* convenient holder for return value */
MOT_FCC_LOG (MOT_FCC_DBG_POLL, ("motFccPollStartn"), 0, 0, 0, 0, 0, 0);
intLevel = intLock();
/* disable system interrupt: reset relevant bit in SIMNR_L */
SYS_FCC_INT_DISABLE (pDrvCtrl, retVal);
if (retVal == ERROR)
return (ERROR);
/* mask chip interrupts */
MOT_FCC_INT_DISABLE;
MOT_FCC_FLAG_SET (MOT_FCC_POLLING);
intUnlock (intLevel);
return (OK);
}
/*******************************************************************************
* motFccPollStop - stop polling mode
*
* This routine stops polling mode by enabling ethernet interrupts and
* resetting the polling flag in the END_CTRL structure.
*
* SEE ALSO: motFccPollStart()
*
* RETURNS: OK, or ERROR if polling mode could not be stopped.
*/
LOCAL STATUS motFccPollStop
(
DRV_CTRL * pDrvCtrl /* pointer to DRV_CTRL structure */
)
{
int intLevel;
int retVal; /* convenient holder for return value */
intLevel = intLock();
/* enable system interrupt: set relevant bit in SIMNR_L */
SYS_FCC_INT_ENABLE (pDrvCtrl, retVal);
if (retVal == ERROR)
return (ERROR);
/* enable chip interrupts */
MOT_FCC_INT_ENABLE;
/* set flags */
MOT_FCC_FLAG_CLEAR (MOT_FCC_POLLING);
intUnlock (intLevel);
MOT_FCC_LOG (MOT_FCC_DBG_POLL, ("motFccPollStop... endn"),
0, 0, 0, 0, 0, 0);
return (OK);
}
#ifdef MOT_FCC_DBG
void motFccIramShow
(
)
{
UINT32 temp32; /* a convenience */
volatile UINT16 temp16; /* a convenience */
DRV_CTRL * pDrvCtrl = pDrvCtrlDbg;
UINT32 fccIramAddr = 0; /* a convenience */
fccIramAddr = pDrvCtrl->fccIramAddr;
MOT_FCC_REG_LONG_RD (fccIramAddr + M8260_FCC_GFMR_OFF,
temp32);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("gfmr=0x%xn"),
temp32, 0, 0, 0, 0, 0);
MOT_FCC_REG_LONG_RD (fccIramAddr + M8260_FCC_FPSMR_OFF,
temp32);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("fpsmr=0x%xn"),
temp32, 0, 0, 0, 0, 0);
MOT_FCC_REG_WORD_RD (fccIramAddr + M8260_FCC_FDSR_OFF,
temp16);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("fdsr=0x%xn"),
temp16, 0, 0, 0, 0, 0);
MOT_FCC_REG_WORD_RD (fccIramAddr + M8260_FCC_FTODR_OFF,
temp16);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("ftodr=0x%xn"),
temp16, 0, 0, 0, 0, 0);
MOT_FCC_REG_WORD_RD (fccIramAddr + M8260_FCC_FCCMR_OFF,
temp16);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("fccmr=0x%xn"),
temp16, 0, 0, 0, 0, 0);
MOT_FCC_REG_WORD_RD (fccIramAddr + M8260_FCC_FCCER_OFF,
temp16);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("fccer=0x%xn"),
temp16, 0, 0, 0, 0, 0);
}
void motFccPramShow
(
)
{
UINT32 tempVal [6]; /* a convenience */
DRV_CTRL * pDrvCtrl = pDrvCtrlDbg; /* the driver control struct */
UINT32 fccPramAddr = 0; /* a convenience */
fccPramAddr = pDrvCtrl->fccPramAddr;
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_RIPTR_OFF,
tempVal [0]);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_TIPTR_OFF,
tempVal [1]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_RSTATE_OFF,
tempVal[2]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_RBASE_OFF,
tempVal[3]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_TSTATE_OFF,
tempVal[4]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_TBASE_OFF,
tempVal[5]);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nriptr=0x%x
tiptr=0x%x
rstate=0x%x
rbase=0x%x
tstate=0x%x
tbase=0x%xn"),
tempVal [0], tempVal [1], tempVal [2],
tempVal [3], tempVal [4], tempVal [5]);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_RET_LIM_OFF,
tempVal [0]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_C_MASK_OFF,
tempVal [1]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_C_PRES_OFF,
tempVal[2]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_CRCEC_OFF,
tempVal[3]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_ALEC_OFF,
tempVal[4]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_DISFC_OFF,
tempVal[5]);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nretry limit=%d
crc mask=0x%x
preset crc=0x%x
crc errored frames=0x%x
misaligned frames=0x%x
discarded frames=0x%xn"),
tempVal [0], tempVal [1], tempVal [2],
tempVal [3], tempVal [4], tempVal [5]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_GADDR_H_OFF,
tempVal[0]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_GADDR_L_OFF,
tempVal[1]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_IADDR_H_OFF,
tempVal[2]);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_IADDR_L_OFF,
tempVal[3]);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("ngroup addr filter high=0x%x
group addr filter low=0x%x
individual addr filter high=0x%x
individual addr filter low=0x%x n"),
tempVal [0], tempVal [1], tempVal [2],
tempVal [3], 0, 0);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_PADDR_H_OFF,
tempVal[0]);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_PADDR_M_OFF,
tempVal[1]);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_PADDR_L_OFF,
tempVal[2]);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nindividual addr high=0x%x
individual addr medium=0x%x
individual addr low=0x%x n"),
tempVal [0], tempVal [1], tempVal [2],
0, 0, 0);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_MRBLR_OFF,
tempVal[0]);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_MFLR_OFF,
tempVal[1]);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_MINFLR_OFF,
tempVal[2]);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_MAXD1_OFF,
tempVal[3]);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_MAXD2_OFF,
tempVal[4]);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nmax rx buf length=0x%x
max frame length=0x%x
min frame length=0x%x
max DMA1 length=0x%x
max DMA2 length=0x%x n"),
tempVal [0], tempVal [1], tempVal [2],
tempVal [3], tempVal [4], 0);
MOT_FCC_REG_LONG_RD (fccPramAddr + M8260_FCC_CAM_PTR_OFF,
tempVal[0]);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_P_PER_OFF,
tempVal[1]);
MOT_FCC_REG_WORD_RD (fccPramAddr + M8260_FCC_PAD_PTR_OFF,
tempVal[2]);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("ncam address pointer=0x%x
persistence=0x%x
internal pad pointer=0x%x n"),
tempVal [0], tempVal [1], tempVal [2],
0, 0, 0);
}
void motFccRbdShow(int rbdNum)
{
FCC_BD *pBd;
pBd = &global_pDrvCtrl->rbdBase[rbdNum];
MOT_FCC_LOG (MOT_FCC_DBG_ANY,
("rbdStatus=0x%x rbdLen=0x%x rbdBuf=0x%xn"),
pBd->word1, pBd->bdLen, pBd->bdAddr, 0, 0, 0);
}
void motFccTbdShow(int tbdNum)
{
FCC_BD *pBd;
pBd = &global_pDrvCtrl->tbdBase[tbdNum];
MOT_FCC_LOG (MOT_FCC_DBG_ANY,
("tbdStatus=0x%x tbdLen=0x%x tbdBuf=0x%xn"),
pBd->word1, pBd->bdLen, pBd->bdAddr, 0, 0, 0);
}
void motFccErrorShow (void)
{
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nTxErr=0x%x
RxBsy=0x%xn"),
motFccTxErr,
motFccRxBsyErr,
0, 0, 0, 0);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nTxLc=0x%x
TxUr=0x%x
TxCsl=0x%x
TxRl=0x%xn"),
motFccTxLcErr,
motFccTxUrErr,
motFccTxCslErr,
motFccTxRlErr,
0, 0);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nRxLg=0x%x
RxNo=0x%x
RxCrc=0x%x
RxOv=0x%x
RxLc=0x%x
RxSh=0x%x n"),
motFccRxLgErr,
motFccRxNoErr,
motFccRxCrcErr,
motFccRxOvErr,
motFccRxLcErr,
motFccRxShErr);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nRxMem=0x%xn"),
motFccRxMemErr,
0, 0, 0, 0, 0);
}
void motFccDrvShow
(
)
{
DRV_CTRL * pDrvCtrl = pDrvCtrlDbg;
MOT_FCC_LOG (MOT_FCC_DBG_ANY, "pDrvCtrl=0x%x pNetPool=0x%x pClPool=0x%xn",
(int) pDrvCtrl,
(int) pDrvCtrl->endObj.pNetPool,
(int) pDrvCtrl->pClPoolId, 0, 0, 0);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, "bdBase=0x%x bdSize=0x%x pClBlkArea=0x%x "
"clBlkSize=0x%x pMBlkArea=0x%x mBlkSize=0x%xn",
(int) pDrvCtrl->pBdBase,
pDrvCtrl->bdSize,
(int) pDrvCtrl->pBufBase,
pDrvCtrl->bufSize,
(int) pDrvCtrl->pMBlkArea,
pDrvCtrl->mBlkSize);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("tbdNum=%d
tbdBase=0x%x
tbdIndex=%d
usedTbdIndex=%d
cleanTbdNum=%d
txStall=%d n"),
pDrvCtrl->tbdNum,
(int) pDrvCtrl->tbdBase,
pDrvCtrl->tbdIndex,
pDrvCtrl->usedTbdIndex,
pDrvCtrl->cleanTbdNum,
pDrvCtrl->txStall);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("rbdNum=%d
rbdBase=0x%x
rbdIndex=%d
iramAddr=0x%x
pramAddr=0x%x
fccNum=%d n"),
pDrvCtrl->rbdNum,
(int) pDrvCtrl->rbdBase,
pDrvCtrl->rbdIndex,
pDrvCtrl->fccIramAddr,
pDrvCtrl->fccPramAddr,
pDrvCtrl->fccNum);
}
void motFccMiiShow
(
)
{
DRV_CTRL * pDrvCtrl = pDrvCtrlDbg;
UCHAR speed [20];
UCHAR mode [20];
strcpy ((char *) speed, (pDrvCtrl->phyInfo->phySpeed == MOT_FCC_100MBS) ?
"100Mbit/s" : "10Mbit/s");
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nphySpeed=%s
phyMode=%s
phyAddr=0x%x
phyFlags=0x%x
phyDefMode=0x%xn"),
(int) &speed[0],
(int) &mode[0],
pDrvCtrl->phyInfo->phyAddr,
pDrvCtrl->phyInfo->phyFlags,
pDrvCtrl->phyInfo->phyDefMode,
0);
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nphyStatus=0x%x
phyCtrl=0x%x
phyAds=0x%x
phyPrtn=0x%x
phyExp=0x%x
phyNext=0x%xn"),
pDrvCtrl->phyInfo->miiRegs.phyStatus,
pDrvCtrl->phyInfo->miiRegs.phyCtrl,
pDrvCtrl->phyInfo->miiRegs.phyAds,
pDrvCtrl->phyInfo->miiRegs.phyPrtn,
pDrvCtrl->phyInfo->miiRegs.phyExp,
pDrvCtrl->phyInfo->miiRegs.phyNext);
}
void motFccMibShow
(
)
{
DRV_CTRL * pDrvCtrl = pDrvCtrlDbg;
MOT_FCC_LOG (MOT_FCC_DBG_ANY, ("nifOutNUcastPkts=%d
ifOutUcastPkts=%d
ifInNUcastPkts=%d
ifInUcastPkts=%d
ifOutErrors=%dn"),
pDrvCtrl->endObj.mib2Tbl.ifOutNUcastPkts,
pDrvCtrl->endObj.mib2Tbl.ifOutUcastPkts,
pDrvCtrl->endObj.mib2Tbl.ifInNUcastPkts,
pDrvCtrl->endObj.mib2Tbl.ifInUcastPkts,
pDrvCtrl->endObj.mib2Tbl.ifOutErrors,
0);
}
UINT16 motFccMiiRegRead
(
UINT8 regAddr
)
{
int status;
UINT16 value;
status = motFccMiiRead(pDrvCtrlDbg,
pDrvCtrlDbg->phyInfo->phyAddr,
regAddr,
&value);
if (status != OK)
MOT_FCC_LOG (MOT_FCC_DBG_MII, ("motFccMiiRead failed, retval %dn"),
status, 2, 3, 4, 5, 6);
return(value);
}
#endif /* MOT_FCC_DBG */