C8051F340_H.LST
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- C51 COMPILER V7.02b C8051F340_H 08/04/2007 14:59:14 PAGE 1
- C51 COMPILER V7.02b, COMPILATION OF MODULE C8051F340_H
- OBJECT MODULE PLACED IN C8051F340_H.OBJ
- COMPILER INVOKED BY: C:KeilC51BINc51.exe C8051F340_H.h DB OE
- stmt level source
- 1 //-----------------------------------------------------------------------------
- 2 // c8051F340.h
- 3 //-----------------------------------------------------------------------------
- 4 // Copyright 2005 Silicon Laboratories, Inc.
- 5 // http://www.usbmcu.com http://www.silabs.com
- 6 //
- 7 // Program Description:
- 8 //
- 9 // Register/bit definitions for the C8051F34x family.
- 10 //
- 11 //
- 12 // FID: 34X000000
- 13 // Target: C8051F340, 'F341, 'F342, 'F343, 'F344, 'F345, 'F346, 'F347
- 14 // Tool chain: Keil
- 15 // Command Line: None
- 16 //
- 17 // Release 1.1
- 18 // -All changes by GP
- 19 // -17 NOV 2005
- 20 // -Converted file to new coding guidelines
- 21 // -Added #defines for interrupt priorities
- 22 // -Added #ifndef/#define to allow multiple includes of file
- 23 // -Converted Bit Definitions to absolute addresses for easier porting
- 24 //
- 25 // Release 1.0
- 26 // -Initial Revision (CM)
- 27 // -08 AUG 2005
- 28 // -Latest release before new firmware coding standard
- 29 //
- 30
- 31 #ifndef C8051F340_H
- 32 #define C8051F340_H
- 33
- 34 //-----------------------------------------------------------------------------
- 35 // Byte Registers
- 36 //-----------------------------------------------------------------------------
- 37
- 38 sfr P0 = 0x80; // Port 0 Latch
- 39 sfr SP = 0x81; // Stack Pointer
- 40 sfr DPL = 0x82; // Data Pointer Low
- 41 sfr DPH = 0x83; // Data Pointer High
- 42 sfr EMI0TC = 0x84; // EMIF Timing
- 43 sfr EMI0CF = 0x85; // EMIF Configuration
- 44 sfr OSCLCN = 0x86; // Internal Low-Freq Oscillator Control
- 45 sfr PCON = 0x87; // Power Control
- 46 sfr TCON = 0x88; // Timer/Counter Control
- 47 sfr TMOD = 0x89; // Timer/Counter Mode
- 48 sfr TL0 = 0x8A; // Timer/Counter 0 Low
- 49 sfr TL1 = 0x8B; // Timer/Counter 1 Low
- 50 sfr TH0 = 0x8C; // Timer/Counter 0 High
- 51 sfr TH1 = 0x8D; // Timer/Counter 1 High
- 52 sfr CKCON = 0x8E; // Clock Control
- 53 sfr PSCTL = 0x8F; // Program Store R/W Control
- 54 sfr P1 = 0x90; // Port 1 Latch
- 55 sfr TMR3CN = 0x91; // Timer/Counter 3Control
- C51 COMPILER V7.02b C8051F340_H 08/04/2007 14:59:14 PAGE 2
- 56 sfr TMR3RLL = 0x92; // Timer/Counter 3 Reload Low
- 57 sfr TMR3RLH = 0x93; // Timer/Counter 3 Reload High
- 58 sfr TMR3L = 0x94; // Timer/Counter 3Low
- 59 sfr TMR3H = 0x95; // Timer/Counter 3 High
- 60 sfr USB0ADR = 0x96; // USB0 Indirect Address Register
- 61 sfr USB0DAT = 0x97; // USB0 Data Register
- 62 sfr SCON0 = 0x98; // UART0 Control
- 63 sfr SBUF0 = 0x99; // UART0 Data Buffer
- 64 sfr CPT1CN = 0x9A; // Comparator1 Control
- 65 sfr CPT0CN = 0x9B; // Comparator0 Control
- 66 sfr CPT1MD = 0x9C; // Comparator1 Mode Selection
- 67 sfr CPT0MD = 0x9D; // Comparator0 Mode Selection
- 68 sfr CPT1MX = 0x9E; // Comparator1 MUX Selection
- 69 sfr CPT0MX = 0x9F; // Comparator0 MUX Selection
- 70 sfr P2 = 0xA0; // Port 2 Latch
- 71 sfr SPI0CFG = 0xA1; // SPI Configuration
- 72 sfr SPI0CKR = 0xA2; // SPI Clock Rate Control
- 73 sfr SPI0DAT = 0xA3; // SPI Data
- 74 sfr P0MDOUT = 0xA4; // Port 0 Output Mode Configuration
- 75 sfr P1MDOUT = 0xA5; // Port 1 Output Mode Configuration
- 76 sfr P2MDOUT = 0xA6; // Port 2 Output Mode Configuration
- 77 sfr P3MDOUT = 0xA7; // Port 3 Output Mode Configuration
- 78 sfr IE = 0xA8; // Interrupt Enable
- 79 sfr CLKSEL = 0xA9; // Clock Select
- 80 sfr EMI0CN = 0xAA; // External Memory Interface Control
- 81 sfr SBCON1 = 0xAC; // UART1 Baud Rate Generator Control
- 82 sfr P4MDOUT = 0xAE; // Port 4 Output Mode Configuration
- 83 sfr PFE0CN = 0xAF; // Prefetch Engine Control
- 84 sfr P3 = 0xB0; // Port 3 Latch
- 85 sfr OSCXCN = 0xB1; // External Oscillator Control
- 86 sfr OSCICN = 0xB2; // Internal Oscillator Control
- 87 sfr OSCICL = 0xB3; // Internal Oscillator Calibration
- 88 sfr SBRLL1 = 0xB4; // UART1 Baud Rate Generator Low
- 89 sfr SBRLH1 = 0xB5; // UART1 Baud Rate Generator High
- 90 sfr FLSCL = 0xB6; // Flash Scale
- 91 sfr FLKEY = 0xB7; // Flash Lock and Key
- 92 sfr IP = 0xB8; // Interrupt Priority
- 93 sfr CLKMUL = 0xB9; // Clock Multiplier
- 94 sfr AMX0N = 0xBA; // AMUX0 Negative Channel Select
- 95 sfr AMX0P = 0xBB; // AMUX0 Positive Channel Select
- 96 sfr ADC0CF = 0xBC; // ADC0 Configuration
- 97 sfr ADC0L = 0xBD; // ADC0 Low
- 98 sfr ADC0H = 0xBE; // ADC0 High
- 99 sfr SMB0CN = 0xC0; // SMBus Control
- 100 sfr SMB0CF = 0xC1; // SMBus Configuration
- 101 sfr SMB0DAT = 0xC2; // SMBus Data
- 102 sfr ADC0GTL = 0xC3; // ADC0 Greater-Than Compare Low
- 103 sfr ADC0GTH = 0xC4; // ADC0 Greater-Than Compare High
- 104 sfr ADC0LTL = 0xC5; // ADC0 Less-Than Compare Word Low
- 105 sfr ADC0LTH = 0xC6; // ADC0 Less-Than Compare Word High
- 106 sfr P4 = 0xC7; // Port 4 Latch
- 107 sfr TMR2CN = 0xC8; // Timer/Counter 2 Control
- 108 sfr REG0CN = 0xC9; // Voltage Regulator Control
- 109 sfr TMR2RLL = 0xCA; // Timer/Counter 2 Reload Low
- 110 sfr TMR2RLH = 0xCB; // Timer/Counter 2 Reload High
- 111 sfr TMR2L = 0xCC; // Timer/Counter 2 Low
- 112 sfr TMR2H = 0xCD; // Timer/Counter 2 High
- 113 sfr PSW = 0xD0; // Program Status Word
- 114 sfr REF0CN = 0xD1; // Voltage Reference Control
- 115 sfr SCON1 = 0xD2; // UART1 Control
- 116 sfr SBUF1 = 0xD3; // UART1 Data Buffer
- 117 sfr P0SKIP = 0xD4; // Port 0 Skip
- C51 COMPILER V7.02b C8051F340_H 08/04/2007 14:59:14 PAGE 3
- 118 sfr P1SKIP = 0xD5; // Port 1 Skip
- 119 sfr P2SKIP = 0xD6; // Port 2 Skip
- 120 sfr USB0XCN = 0xD7; // USB0 Transceiver Control
- 121 sfr PCA0CN = 0xD8; // PCA0 Control
- 122 sfr PCA0MD = 0xD9; // PCA0 Mode
- 123 sfr PCA0CPM0 = 0xDA; // PCA0 Module 0 Mode Register
- 124 sfr PCA0CPM1 = 0xDB; // PCA0 Module 1 Mode Register
- 125 sfr PCA0CPM2 = 0xDC; // PCA0 Module 2 Mode Register
- 126 sfr PCA0CPM3 = 0xDD; // PCA0 Module 3 Mode Register
- 127 sfr PCA0CPM4 = 0xDE; // PCA0 Module 4 Mode Register
- 128 sfr P3SKIP = 0xDF; // Port 3 Skip
- 129 sfr ACC = 0xE0; // Accumulator
- 130 sfr XBR0 = 0xE1; // Port I/O Crossbar Control 0
- 131 sfr XBR1 = 0xE2; // Port I/O Crossbar Control 1
- 132 sfr XBR2 = 0xE3; // Port I/O Crossbar Control 2
- 133 sfr IT01CF = 0xE4; // INT0/INT1 Configuration
- 134 sfr SMOD1 = 0xE5; // UART1 Mode
- 135 sfr EIE1 = 0xE6; // Extended Interrupt Enable 1
- 136 sfr EIE2 = 0xE7; // Extended Interrupt Enable 2
- 137 sfr ADC0CN = 0xE8; // ADC0 Control
- 138 sfr PCA0CPL1 = 0xE9; // PCA0 Capture 1 Low
- 139 sfr PCA0CPH1 = 0xEA; // PCA0 Capture 1 High
- 140 sfr PCA0CPL2 = 0xEB; // PCA0 Capture 2 Low
- 141 sfr PCA0CPH2 = 0xEC; // PCA0 Capture 2 High
- 142 sfr PCA0CPL3 = 0xED; // PCA0 Capture 3 Low
- 143 sfr PCA0CPH3 = 0xEE; // PCA0 Capture 3 High
- 144 sfr RSTSRC = 0xEF; // Reset Source Configuration/Status
- 145 sfr B = 0xF0; // B Register
- 146 sfr P0MDIN = 0xF1; // Port 0 Input Mode Configuration
- 147 sfr P1MDIN = 0xF2; // Port 1 Input Mode Configuration
- 148 sfr P2MDIN = 0xF3; // Port 2 Input Mode Configuration
- 149 sfr P3MDIN = 0xF4; // Port 3 Input Mode Configuration
- 150 sfr P4MDIN = 0xF5; // Port 4 Input Mode Configuration
- 151 sfr EIP1 = 0xF6; // Extended Interrupt Priority 1
- 152 sfr EIP2 = 0xF7; // Extended Interrupt Priority 2
- 153 sfr SPI0CN = 0xF8; // SPI0 Control
- 154 sfr PCA0L = 0xF9; // PCA0 Counter Low
- 155 sfr PCA0H = 0xFA; // PCA0 Counter High
- 156 sfr PCA0CPL0 = 0xFB; // PCA0 Capture 0 Low
- 157 sfr PCA0CPH0 = 0xFC; // PCA0 Capture 0 High
- 158 sfr PCA0CPL4 = 0xFD; // PCA0 Capture 4 Low
- 159 sfr PCA0CPH4 = 0xFE; // PCA0 Capture 4 High
- 160 sfr VDM0CN = 0xFF; // VDD Monitor Control
- 161
- 162
- 163 //-----------------------------------------------------------------------------
- 164 // Bit Definitions
- 165 //-----------------------------------------------------------------------------
- 166
- 167 // TCON 0x88
- 168 sbit TF1 = 0x8F; // Timer1 overflow flag
- 169 sbit TR1 = 0x8E; // Timer1 on/off control
- 170 sbit TF0 = 0x8D; // Timer0 overflow flag
- 171 sbit TR0 = 0x8C; // Timer0 on/off control
- 172 sbit IE1 = 0x8B; // Ext interrupt 1 edge flag
- 173 sbit IT1 = 0x8A; // Ext interrupt 1 type
- 174 sbit IE0 = 0x89; // Ext interrupt 0 edge flag
- 175 sbit IT0 = 0x88; // Ext interrupt 0 type
- 176
- 177 // SCON0 0x98
- 178 sbit S0MODE = 0x9F; // Serial mode control bit 0
- 179 // Bit6 UNUSED
- C51 COMPILER V7.02b C8051F340_H 08/04/2007 14:59:14 PAGE 4
- 180 sbit MCE0 = 0x9D; // Multiprocessor communication enable
- 181 sbit REN0 = 0x9C; // Receive enable
- 182 sbit TB80 = 0x9B; // Transmit bit 8
- 183 sbit RB80 = 0x9A; // Receive bit 8
- 184 sbit TI0 = 0x99; // Transmit interrupt flag
- 185 sbit RI0 = 0x98; // Receive interrupt flag
- 186
- 187 // IE 0xA8
- 188 sbit EA = 0xAF; // Global interrupt enable
- 189 sbit ESPI0 = 0xAE; // SPI0 interrupt enable
- 190 sbit ET2 = 0xAD; // Timer2 interrupt enable
- 191 sbit ES0 = 0xAC; // UART0 interrupt enable
- 192 sbit ET1 = 0xAB; // Timer1 interrupt enable
- 193 sbit EX1 = 0xAA; // External interrupt 1 enable
- 194 sbit ET0 = 0xA9; // Timer0 interrupt enable
- 195 sbit EX0 = 0xA8; // External interrupt 0 enable
- 196
- 197 // IP 0xB8
- 198 // Bit7 UNUSED
- 199 sbit PSPI0 = 0xBE; // SPI0 interrupt priority
- 200 sbit PT2 = 0xBD; // Timer2 priority
- 201 sbit PS0 = 0xBC; // UART0 priority
- 202 sbit PT1 = 0xBB; // Timer1 priority
- 203 sbit PX1 = 0xBA; // External interrupt 1 priority
- 204 sbit PT0 = 0xB9; // Timer0 priority
- 205 sbit PX0 = 0xB8; // External interrupt 0 priority
- 206
- 207 // SMB0CN 0xC0
- 208 sbit MASTER = 0xC7; // Master/slave indicator
- 209 sbit TXMODE = 0xC6; // Transmit mode indicator
- 210 sbit STA = 0xC5; // Start flag
- 211 sbit STO = 0xC4; // Stop flag
- 212 sbit ACKRQ = 0xC3; // Acknowledge request
- 213 sbit ARBLOST = 0xC2; // Arbitration lost indicator
- 214 sbit ACK = 0xC1; // Acknowledge flag
- 215 sbit SI = 0xC0; // SMBus interrupt flag
- 216
- 217 // TMR2CN 0xC8
- 218 sbit TF2H = 0xCF; // Timer2 high byte overflow flag
- 219 sbit TF2L = 0xCE; // Timer2 low byte overflow flag
- 220 sbit TF2LEN = 0xCD; // Timer2 low byte interrupt enable
- 221 sbit T2SOF = 0xCC; // Timer2 start-of-frame capture enable
- 222 sbit T2SPLIT = 0xCB; // Timer2 split mode enable
- 223 sbit TR2 = 0xCA; // Timer2 on/off control
- 224 // Bit1 UNUSED
- 225 sbit T2XCLK = 0xC8; // Timer2 external clock select
- 226
- 227 // PSW 0xD0
- 228 sbit CY = 0xD7; // Carry flag
- 229 sbit AC = 0xD6; // Auxiliary carry flag
- 230 sbit F0 = 0xD5; // User flag 0
- 231 sbit RS1 = 0xD4; // Register bank select 1
- 232 sbit RS0 = 0xD3; // Register bank select 0
- 233 sbit OV = 0xD2; // Overflow flag
- 234 sbit F1 = 0xD1; // User flag 1
- 235 sbit P = 0xD0; // Accumulator parity flag
- 236
- 237 // PCA0CN 0xD8
- 238 sbit CF = 0xDF; // PCA0 counter overflow flag
- 239 sbit CR = 0xDE; // PCA0 counter run control
- 240 // Bit5 UNUSED
- 241 sbit CCF4 = 0xDC; // PCA0 module4 capture/compare flag
- C51 COMPILER V7.02b C8051F340_H 08/04/2007 14:59:14 PAGE 5
- 242 sbit CCF3 = 0xDB; // PCA0 module3 capture/compare flag
- 243 sbit CCF2 = 0xDA; // PCA0 module2 capture/compare flag
- 244 sbit CCF1 = 0xD9; // PCA0 module1 capture/compare flag
- 245 sbit CCF0 = 0xD8; // PCA0 module0 capture/compare flag
- 246
- 247 // ADC0CN 0xE8
- 248 sbit AD0EN = 0xEF; // ADC0 enable
- 249 sbit AD0TM = 0xEE; // ADC0 track mode
- 250 sbit AD0INT = 0xED; // ADC0 converision complete interrupt flag
- 251 sbit AD0BUSY = 0xEC; // ADC0 busy flag
- 252 sbit AD0WINT = 0xEB; // ADC0 window compare interrupt flag
- 253 sbit AD0CM2 = 0xEA; // ADC0 conversion mode select 2
- 254 sbit AD0CM1 = 0xE9; // ADC0 conversion mode select 1
- 255 sbit AD0CM0 = 0xE8; // ADC0 conversion mode select 0
- 256
- 257 // SPI0CN 0xF8
- 258 sbit SPIF = 0xFF; // SPI0 interrupt flag
- 259 sbit WCOL = 0xFE; // SPI0 write collision flag
- 260 sbit MODF = 0xFD; // SPI0 mode fault flag
- 261 sbit RXOVRN = 0xFC; // SPI0 rx overrun flag
- 262 sbit NSSMD1 = 0xFB; // SPI0 slave select mode 1
- 263 sbit NSSMD0 = 0xFA; // SPI0 slave select mode 0
- 264 sbit TXBMT = 0xF9; // SPI0 transmit buffer empty
- 265 sbit SPIEN = 0xF8; // SPI0 SPI enable
- 266
- 267
- 268
- 269 // 16-bit SFR declarations
- 270 sfr16 DP = 0x82; // data pointer
- 271 sfr16 TMR2RL = 0xca; // Timer2 reload
- 272 sfr16 TMR2 = 0xcc; // Timer2 counter
- 273 sfr16 TMR3 = 0x94; // Timer3 counter
- 274 sfr16 TMR3RL = 0x92; // Timer3 reload
- 275 sfr16 PCA0CP1 = 0xe9; // PCA0 Module 1 Capture/Compare
- 276 sfr16 PCA0CP2 = 0xeb; // PCA0 Module 2 Capture/Compare
- 277 sfr16 PCA0CP3 = 0xed; // PCA0 Module 3 Capture/Compare
- 278 sfr16 PCA0CP4 = 0xfd; // PCA0 Module 4 Capture/Compare
- 279 sfr16 PCA0CP0 = 0xfb; // PCA0 Module 0 Capture/Compare
- 280 sfr16 PCA0 = 0xf9; // PCA0 counter
- 281 //-----------------------------------------------------------------------------
- 282 // Interrupt Priorities
- 283 //-----------------------------------------------------------------------------
- 284
- 285 #define INTERRUPT_INT0 0 // External Interrupt 0
- 286 #define INTERRUPT_TIMER0 1 // Timer0 Overflow
- 287 #define INTERRUPT_INT1 2 // External Interrupt 1
- 288 #define INTERRUPT_TIMER1 3 // Timer1 Overflow
- 289 #define INTERRUPT_UART0 4 // Serial Port 0
- 290 #define INTERRUPT_TIMER2 5 // Timer2 Overflow
- 291 #define INTERRUPT_SPI0 6 // Serial Peripheral Interface 0
- 292 #define INTERRUPT_SMBUS0 7 // SMBus0 Interface
- 293 #define INTERRUPT_USB0 8 // USB Interface
- 294 #define INTERRUPT_ADC0_WINDOW 9 // ADC0 Window Comparison
- 295 #define INTERRUPT_ADC0_EOC 10 // ADC0 End Of Conversion
- 296 #define INTERRUPT_PCA0 11 // PCA0 Peripheral
- 297 #define INTERRUPT_COMPARATOR0 12 // Comparator0
- 298 #define INTERRUPT_COMPARATOR1 13 // Comparator1
- 299 #define INTERRUPT_TIMER3 14 // Timer3 Overflow
- 300 #define INTERRUPT_VBUS_LEVEL 15 // VBUS level-triggered interrupt
- 301 #define INTERRUPT_UART1 16 // Serial Port 1
- 302
- 303 //-----------------------------------------------------------------------------
- C51 COMPILER V7.02b C8051F340_H 08/04/2007 14:59:14 PAGE 6
- 304 // Header File PreProcessor Directive
- 305 //-----------------------------------------------------------------------------
- 306
- 307 /************************************************************
- 308 * STANDARD BITS
- 309 ************************************************************/
- 310
- 311 #define BIT0 (0x0001)
- 312 #define BIT1 (0x0002)
- 313 #define BIT2 (0x0004)
- 314 #define BIT3 (0x0008)
- 315 #define BIT4 (0x0010)
- 316 #define BIT5 (0x0020)
- 317 #define BIT6 (0x0040)
- 318 #define BIT7 (0x0080)
- 319 #define BIT8 (0x0100)
- 320 #define BIT9 (0x0200)
- 321 #define BITA (0x0400)
- 322 #define BITB (0x0800)
- 323 #define BITC (0x1000)
- 324 #define BITD (0x2000)
- 325 #define BITE (0x4000)
- 326 #define BITF (0x8000)
- 327
- 328
- 329 #endif // #define C8051F340_H
- 330
- 331 //-----------------------------------------------------------------------------
- 332 // End Of File
- 333 //-----------------------------------------------------------------------------
- MODULE INFORMATION: STATIC OVERLAYABLE
- CODE SIZE = ---- ----
- CONSTANT SIZE = ---- ----
- XDATA SIZE = ---- ----
- PDATA SIZE = ---- ----
- DATA SIZE = ---- ----
- IDATA SIZE = ---- ----
- BIT SIZE = ---- ----
- END OF MODULE INFORMATION.
- C51 COMPILATION COMPLETE. 0 WARNING(S), 0 ERROR(S)
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