FM1702SL读卡器整板PCB.DRC
资源名称:FM1702.rar [点击查看]
上传用户:guangya188
上传日期:2019-10-26
资源大小:4644k
文件大小:2k
源码类别:
RFID编程
开发平台:
C/C++
- Protel Design System Design Rule Check
- PCB File : 读卡器制作dxp读卡器整版PCBFM1702SL读卡器整板PCB.PCBDOC
- Date : 2009/1/12
- Time : 12:47:10
- Processing Rule : Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=0.9mm) (InNet('RFDVDD'))
- Rule Violations :0
- Processing Rule : Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=1.1mm) (InNet('RFDVSS'))
- Rule Violations :0
- Processing Rule : Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=1.1mm) (InNet('RFAVSS'))
- Rule Violations :0
- Processing Rule : Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=0.9mm) (InNet('RFAVDD'))
- Rule Violations :0
- Processing Rule : Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=0.9mm) (InNet('VCC'))
- Rule Violations :0
- Processing Rule : Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=1.1mm) (InNet('GND'))
- Rule Violations :0
- Processing Rule : Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=0.9mm) (InNet('+5'))
- Rule Violations :0
- Processing Rule : Short-Circuit Constraint (Allowed=No) (All),(All)
- Rule Violations :0
- Processing Rule : Broken-Net Constraint ( (All) )
- Rule Violations :0
- Processing Rule : Clearance Constraint (Gap=0.254mm) (All),(All)
- Rule Violations :0
- Processing Rule : Width Constraint (Min=0.254mm) (Max=1.5mm) (Preferred=0.7mm) (All)
- Rule Violations :0
- Processing Rule : Height Constraint (Min=0mm) (Max=25.4mm) (Prefered=12.7mm) (All)
- Rule Violations :0
- Processing Rule : Hole Size Constraint (Min=0.0254mm) (Max=2.54mm) (All)
- Violation Pad Free-0(201.295mm,73.787mm) Multi-Layer Actual Hole Size = 3.2mm
- Violation Pad JP3-2(142.875mm,61.849mm) Multi-Layer Actual Hole Size = 0mm
- Rule Violations :2
- Violations Detected : 2
- Time Elapsed : 00:00:01