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cpu.hif
资源名称：115157712RISC8.rar　[点击查看]
上传用户：bltddc
上传日期：2020-07-09
资源大小：4428k
文件大小：4k
源码类别：

SCSI/ASPI

开发平台：

VHDL

cpu.hif：源码内容
  1. Version 9.0 Build 132 02/25/2009 SJ Full Version
  2. 7
  3. 3344
  4. OFF
  5. OFF
  6. OFF
  7. ON
  8. ON
  9. ON
  10. FV_OFF
  11. Level2
  12. 0
  13. 0
  14. VRSM_ON
  15. VHSM_ON
  16. 0
  17. -- Start Library Paths --
  18. -- End Library Paths --
  19. -- Start VHDL Libraries --
  20. -- End VHDL Libraries --
  21. # entity
  22. cpu
  23. # storage
  24. db|cpu.(0).cnf
  25. db|cpu.(0).cnf
  26. # logic_option {
  27. AUTO_RAM_RECOGNITION
  28. ON
  29. }
  30. # case_sensitive
  31. # source_file
  32. cpu.v
  33. f2ecdcb67c47f24bb2ec14d9eacad69
  34. 8
  35. # internal_option {
  36. HDL_INITIAL_FANOUT_LIMIT
  37. OFF
  38. AUTO_RESOURCE_SHARING
  39. OFF
  40. AUTO_RAM_RECOGNITION
  41. ON
  42. AUTO_ROM_RECOGNITION
  43. ON
  44. IGNORE_VERILOG_INITIAL_CONSTRUCTS
  45. OFF
  46. VERILOG_CONSTANT_LOOP_LIMIT
  47. 5000
  48. VERILOG_NON_CONSTANT_LOOP_LIMIT
  49. 250
  50. }
  51. # user_parameter {
  52. RESET_VECTOR
  53. 11111111111
  54. PARAMETER_UNSIGNED_BIN
  55. DEF
  56. INDF_ADDRESS
  57. 000
  58. PARAMETER_UNSIGNED_BIN
  59. DEF
  60. TMR0_ADDRESS
  61. 001
  62. PARAMETER_UNSIGNED_BIN
  63. DEF
  64. PCL_ADDRESS
  65. 010
  66. PARAMETER_UNSIGNED_BIN
  67. DEF
  68. STATUS_ADDRESS
  69. 011
  70. PARAMETER_UNSIGNED_BIN
  71. DEF
  72. FSR_ADDRESS
  73. 100
  74. PARAMETER_UNSIGNED_BIN
  75. DEF
  76. PORTA_ADDRESS
  77. 101
  78. PARAMETER_UNSIGNED_BIN
  79. DEF
  80. PORTB_ADDRESS
  81. 110
  82. PARAMETER_UNSIGNED_BIN
  83. DEF
  84. PORTC_ADDRESS
  85. 111
  86. PARAMETER_UNSIGNED_BIN
  87. DEF
  88. ALUASEL_W
  89. 00
  90. PARAMETER_UNSIGNED_BIN
  91. DEF
  92. ALUASEL_SBUS
  93. 01
  94. PARAMETER_UNSIGNED_BIN
  95. DEF
  96. ALUASEL_K
  97. 10
  98. PARAMETER_UNSIGNED_BIN
  99. DEF
  100. ALUASEL_BD
  101. 11
  102. PARAMETER_UNSIGNED_BIN
  103. DEF
  104. ALUBSEL_W
  105. 00
  106. PARAMETER_UNSIGNED_BIN
  107. DEF
  108. ALUBSEL_SBUS
  109. 01
  110. PARAMETER_UNSIGNED_BIN
  111. DEF
  112. ALUBSEL_K
  113. 10
  114. PARAMETER_UNSIGNED_BIN
  115. DEF
  116. ALUBSEL_1
  117. 11
  118. PARAMETER_UNSIGNED_BIN
  119. DEF
  120. ALUOP_ADD
  121. 0000
  122. PARAMETER_UNSIGNED_BIN
  123. DEF
  124. ALUOP_SUB
  125. 1000
  126. PARAMETER_UNSIGNED_BIN
  127. DEF
  128. ALUOP_AND
  129. 0001
  130. PARAMETER_UNSIGNED_BIN
  131. DEF
  132. ALUOP_OR
  133. 0010
  134. PARAMETER_UNSIGNED_BIN
  135. DEF
  136. ALUOP_XOR
  137. 0011
  138. PARAMETER_UNSIGNED_BIN
  139. DEF
  140. ALUOP_COM
  141. 0100
  142. PARAMETER_UNSIGNED_BIN
  143. DEF
  144. ALUOP_ROR
  145. 0101
  146. PARAMETER_UNSIGNED_BIN
  147. DEF
  148. ALUOP_ROL
  149. 0110
  150. PARAMETER_UNSIGNED_BIN
  151. DEF
  152. ALUOP_SWAP
  153. 0111
  154. PARAMETER_UNSIGNED_BIN
  155. DEF
  156. STATUS_RESET_VALUE
  157. 00011000
  158. PARAMETER_UNSIGNED_BIN
  159. DEF
  160. OPTION_RESET_VALUE
  161. 00111111
  162. PARAMETER_UNSIGNED_BIN
  163. DEF
  164. }
  165. # hierarchies {
  166. |
  167. }
  168. # macro_sequence
  170. # end
  171. # entity
  172. regs
  173. # storage
  174. db|cpu.(1).cnf
  175. db|cpu.(1).cnf
  176. # logic_option {
  177. AUTO_RAM_RECOGNITION
  178. ON
  179. }
  180. # case_sensitive
  181. # source_file
  182. regs.v
  183. ebc22d10c2fd74615c739db0a51276a1
  184. 8
  185. # internal_option {
  186. HDL_INITIAL_FANOUT_LIMIT
  187. OFF
  188. AUTO_RESOURCE_SHARING
  189. OFF
  190. AUTO_RAM_RECOGNITION
  191. ON
  192. AUTO_ROM_RECOGNITION
  193. ON
  194. IGNORE_VERILOG_INITIAL_CONSTRUCTS
  195. OFF
  196. VERILOG_CONSTANT_LOOP_LIMIT
  197. 5000
  198. VERILOG_NON_CONSTANT_LOOP_LIMIT
  199. 250
  200. }
  201. # hierarchies {
  202. regs:regs
  203. }
  204. # macro_sequence
  206. # end
  207. # entity
  208. dram
  209. # storage
  210. db|cpu.(2).cnf
  211. db|cpu.(2).cnf
  212. # logic_option {
  213. AUTO_RAM_RECOGNITION
  214. ON
  215. }
  216. # case_sensitive
  217. # source_file
  218. dram.v
  219. 877fd329b38ebc6adfef29b421c3a63
  220. 8
  221. # internal_option {
  222. HDL_INITIAL_FANOUT_LIMIT
  223. OFF
  224. AUTO_RESOURCE_SHARING
  225. OFF
  226. AUTO_RAM_RECOGNITION
  227. ON
  228. AUTO_ROM_RECOGNITION
  229. ON
  230. IGNORE_VERILOG_INITIAL_CONSTRUCTS
  231. OFF
  232. VERILOG_CONSTANT_LOOP_LIMIT
  233. 5000
  234. VERILOG_NON_CONSTANT_LOOP_LIMIT
  235. 250
  236. }
  237. # user_parameter {
  238. word_depth
  239. 70
  240. PARAMETER_SIGNED_DEC
  241. DEF
  242. }
  243. # hierarchies {
  244. regs:regs|dram:dram
  245. }
  246. # macro_sequence
  248. # end
  249. # entity
  250. alu
  251. # storage
  252. db|cpu.(3).cnf
  253. db|cpu.(3).cnf
  254. # logic_option {
  255. AUTO_RAM_RECOGNITION
  256. ON
  257. }
  258. # case_sensitive
  259. # source_file
  260. alu.v
  261. c8cab1bce095c72782b15cd5c3c96cc
  262. 8
  263. # internal_option {
  264. HDL_INITIAL_FANOUT_LIMIT
  265. OFF
  266. AUTO_RESOURCE_SHARING
  267. OFF
  268. AUTO_RAM_RECOGNITION
  269. ON
  270. AUTO_ROM_RECOGNITION
  271. ON
  272. IGNORE_VERILOG_INITIAL_CONSTRUCTS
  273. OFF
  274. VERILOG_CONSTANT_LOOP_LIMIT
  275. 5000
  276. VERILOG_NON_CONSTANT_LOOP_LIMIT
  277. 250
  278. }
  279. # user_parameter {
  280. ALUOP_ADD
  281. 0000
  282. PARAMETER_UNSIGNED_BIN
  283. DEF
  284. ALUOP_SUB
  285. 1000
  286. PARAMETER_UNSIGNED_BIN
  287. DEF
  288. ALUOP_AND
  289. 0001
  290. PARAMETER_UNSIGNED_BIN
  291. DEF
  292. ALUOP_OR
  293. 0010
  294. PARAMETER_UNSIGNED_BIN
  295. DEF
  296. ALUOP_XOR
  297. 0011
  298. PARAMETER_UNSIGNED_BIN
  299. DEF
  300. ALUOP_COM
  301. 0100
  302. PARAMETER_UNSIGNED_BIN
  303. DEF
  304. ALUOP_ROR
  305. 0101
  306. PARAMETER_UNSIGNED_BIN
  307. DEF
  308. ALUOP_ROL
  309. 0110
  310. PARAMETER_UNSIGNED_BIN
  311. DEF
  312. ALUOP_SWAP
  313. 0111
  314. PARAMETER_UNSIGNED_BIN
  315. DEF
  316. }
  317. # hierarchies {
  318. alu:alu
  319. }
  320. # macro_sequence
  322. # end
  323. # entity
  324. idec
  325. # storage
  326. db|cpu.(4).cnf
  327. db|cpu.(4).cnf
  328. # logic_option {
  329. AUTO_RAM_RECOGNITION
  330. ON
  331. }
  332. # case_sensitive
  333. # source_file
  334. idec.v
  335. d514526ab7b639204e865f8bea155b12
  336. 8
  337. # internal_option {
  338. HDL_INITIAL_FANOUT_LIMIT
  339. OFF
  340. AUTO_RESOURCE_SHARING
  341. OFF
  342. AUTO_RAM_RECOGNITION
  343. ON
  344. AUTO_ROM_RECOGNITION
  345. ON
  346. IGNORE_VERILOG_INITIAL_CONSTRUCTS
  347. OFF
  348. VERILOG_CONSTANT_LOOP_LIMIT
  349. 5000
  350. VERILOG_NON_CONSTANT_LOOP_LIMIT
  351. 250
  352. }
  353. # hierarchies {
  354. idec:idec
  355. }
  356. # macro_sequence
  358. # end
  359. # complete