cpu.map.rpt
上传用户：bltddc
上传日期：2020-07-09
资源大小：4428k
文件大小：33k
- Analysis & Synthesis report for cpu
- Mon Mar 08 21:52:14 2010
- Quartus II Version 9.0 Build 132 02/25/2009 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Analysis & Synthesis Source Files Read
- 5. Analysis & Synthesis Resource Usage Summary
- 6. Analysis & Synthesis Resource Utilization by Entity
- 7. Registers Removed During Synthesis
- 8. General Register Statistics
- 9. Multiplexer Restructuring Statistics (Restructuring Performed)
- 10. Parameter Settings for User Entity Instance: Top-level Entity: |cpu
- 11. Parameter Settings for User Entity Instance: regs:regs|dram:dram
- 12. Parameter Settings for User Entity Instance: alu:alu
- 13. Analysis & Synthesis Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2009 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +--------------------------------------------------------------------------+
- ; Analysis & Synthesis Summary ;
- +-------------------------------+------------------------------------------+
- ; Analysis & Synthesis Status ; Successful - Mon Mar 08 21:52:14 2010 ;
- ; Quartus II Version ; 9.0 Build 132 02/25/2009 SJ Full Version ;
- ; Revision Name ; cpu ;
- ; Top-level Entity Name ; cpu ;
- ; Family ; Stratix II ;
- ; Logic utilization ; N/A ;
- ; Combinational ALUTs ; 589 ;
- ; Dedicated logic registers ; 660 ;
- ; Total registers ; 660 ;
- ; Total pins ; 113 ;
- ; Total virtual pins ; 0 ;
- ; Total block memory bits ; 0 ;
- ; DSP block 9-bit elements ; 0 ;
- ; Total PLLs ; 0 ;
- ; Total DLLs ; 0 ;
- +-------------------------------+------------------------------------------+
- +----------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Settings ;
- +----------------------------------------------------------------+--------------------+--------------------+
- ; Option ; Setting ; Default Value ;
- +----------------------------------------------------------------+--------------------+--------------------+
- ; Top-level entity name ; cpu ; cpu ;
- ; Family name ; Stratix II ; Stratix II ;
- ; Use Generated Physical Constraints File ; Off ; ;
- ; Use smart compilation ; Off ; Off ;
- ; Restructure Multiplexers ; Auto ; Auto ;
- ; Create Debugging Nodes for IP Cores ; Off ; Off ;
- ; Preserve fewer node names ; On ; On ;
- ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
- ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
- ; VHDL Version ; VHDL93 ; VHDL93 ;
- ; State Machine Processing ; Auto ; Auto ;
- ; Safe State Machine ; Off ; Off ;
- ; Extract Verilog State Machines ; On ; On ;
- ; Extract VHDL State Machines ; On ; On ;
- ; Ignore Verilog initial constructs ; Off ; Off ;
- ; Iteration limit for constant Verilog loops ; 5000 ; 5000 ;
- ; Iteration limit for non-constant Verilog loops ; 250 ; 250 ;
- ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
- ; Parallel Synthesis ; Off ; Off ;
- ; DSP Block Balancing ; Auto ; Auto ;
- ; NOT Gate Push-Back ; On ; On ;
- ; Power-Up Don't Care ; On ; On ;
- ; Remove Redundant Logic Cells ; Off ; Off ;
- ; Remove Duplicate Registers ; On ; On ;
- ; Ignore CARRY Buffers ; Off ; Off ;
- ; Ignore CASCADE Buffers ; Off ; Off ;
- ; Ignore GLOBAL Buffers ; Off ; Off ;
- ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
- ; Ignore LCELL Buffers ; Off ; Off ;
- ; Ignore SOFT Buffers ; On ; On ;
- ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
- ; Optimization Technique ; Balanced ; Balanced ;
- ; Carry Chain Length ; 70 ; 70 ;
- ; Auto Carry Chains ; On ; On ;
- ; Auto Open-Drain Pins ; On ; On ;
- ; Perform WYSIWYG Primitive Resynthesis ; Off ; Off ;
- ; Auto ROM Replacement ; On ; On ;
- ; Auto RAM Replacement ; On ; On ;
- ; Auto DSP Block Replacement ; On ; On ;
- ; Auto Shift Register Replacement ; Auto ; Auto ;
- ; Auto Clock Enable Replacement ; On ; On ;
- ; Strict RAM Replacement ; Off ; Off ;
- ; Allow Synchronous Control Signals ; On ; On ;
- ; Force Use of Synchronous Clear Signals ; Off ; Off ;
- ; Auto RAM Block Balancing ; On ; On ;
- ; Auto RAM to Logic Cell Conversion ; Off ; Off ;
- ; Auto Resource Sharing ; Off ; Off ;
- ; Allow Any RAM Size For Recognition ; Off ; Off ;
- ; Allow Any ROM Size For Recognition ; Off ; Off ;
- ; Allow Any Shift Register Size For Recognition ; Off ; Off ;
- ; Use LogicLock Constraints during Resource Balancing ; On ; On ;
- ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
- ; Timing-Driven Synthesis ; Off ; Off ;
- ; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
- ; Ignore Maximum Fan-Out Assignments ; Off ; Off ;
- ; Synchronization Register Chain Length ; 2 ; 2 ;
- ; PowerPlay Power Optimization ; Normal compilation ; Normal compilation ;
- ; HDL message level ; Level2 ; Level2 ;
- ; Suppress Register Optimization Related Messages ; Off ; Off ;
- ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
- ; Number of Inverted Registers Reported in Synthesis Report ; 100 ; 100 ;
- ; Clock MUX Protection ; On ; On ;
- ; Auto Gated Clock Conversion ; Off ; Off ;
- ; Block Design Naming ; Auto ; Auto ;
- ; SDC constraint protection ; Off ; Off ;
- ; Synthesis Effort ; Auto ; Auto ;
- ; Allows Asynchronous Clear Usage For Shift Register Replacement ; On ; On ;
- ; Analysis & Synthesis Message Level ; Medium ; Medium ;
- +----------------------------------------------------------------+--------------------+--------------------+
- +--------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Source Files Read ;
- +----------------------------------+-----------------+------------------------------+--------------------------------------------+
- ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
- +----------------------------------+-----------------+------------------------------+--------------------------------------------+
- ; cpu.v ; yes ; User Verilog HDL File ; F:/altera/90/quartus/115157712RISC8/cpu.v ;
- ; regs.v ; yes ; Auto-Found Verilog HDL File ; F:/altera/90/quartus/115157712RISC8/regs.v ;
- ; dram.v ; yes ; Auto-Found Verilog HDL File ; F:/altera/90/quartus/115157712RISC8/dram.v ;
- ; alu.v ; yes ; Auto-Found Verilog HDL File ; F:/altera/90/quartus/115157712RISC8/alu.v ;
- ; idec.v ; yes ; Auto-Found Verilog HDL File ; F:/altera/90/quartus/115157712RISC8/idec.v ;
- +----------------------------------+-----------------+------------------------------+--------------------------------------------+
- +-------------------------------------------------------+
- ; Analysis & Synthesis Resource Usage Summary ;
- +-----------------------------------------------+-------+
- ; Resource ; Usage ;
- +-----------------------------------------------+-------+
- ; Estimated ALUTs Used ; 589 ;
- ; Dedicated logic registers ; 660 ;
- ; ; ;
- ; Estimated ALUTs Unavailable ; 204 ;
- ; ; ;
- ; Total combinational functions ; 589 ;
- ; Combinational ALUT usage by number of inputs ; ;
- ; -- 7 input functions ; 130 ;
- ; -- 6 input functions ; 160 ;
- ; -- 5 input functions ; 78 ;
- ; -- 4 input functions ; 50 ;
- ; -- <=3 input functions ; 171 ;
- ; ; ;
- ; Combinational ALUTs by mode ; ;
- ; -- normal mode ; 413 ;
- ; -- extended LUT mode ; 130 ;
- ; -- arithmetic mode ; 46 ;
- ; -- shared arithmetic mode ; 0 ;
- ; ; ;
- ; Estimated ALUT/register pairs used ; 1200 ;
- ; ; ;
- ; Total registers ; 660 ;
- ; -- Dedicated logic registers ; 660 ;
- ; -- I/O registers ; 0 ;
- ; ; ;
- ; Estimated ALMs: partially or completely used ; 600 ;
- ; ; ;
- ; I/O pins ; 113 ;
- ; Maximum fan-out node ; clk ;
- ; Maximum fan-out ; 660 ;
- ; Total fan-out ; 4968 ;
- ; Average fan-out ; 3.65 ;
- +-----------------------------------------------+-------+
- +----------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Resource Utilization by Entity ;
- +----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+--------------------------+--------------+
- ; Compilation Hierarchy Node ; LC Combinationals ; LC Registers ; Block Memory Bits ; DSP Elements ; DSP 9x9 ; DSP 18x18 ; DSP 36x36 ; Pins ; Virtual Pins ; Full Hierarchy Name ; Library Name ;
- +----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+--------------------------+--------------+
- ; |cpu ; 589 (202) ; 660 (116) ; 0 ; 0 ; 0 ; 0 ; 0 ; 113 ; 0 ; |cpu ; work ;
- ; |alu:alu| ; 53 (53) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |cpu|alu:alu ; work ;
- ; |idec:idec| ; 45 (45) ; 0 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |cpu|idec:idec ; work ;
- ; |regs:regs| ; 289 (4) ; 544 (0) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |cpu|regs:regs ; work ;
- ; |dram:dram| ; 285 (285) ; 544 (544) ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; 0 ; |cpu|regs:regs|dram:dram ; work ;
- +----------------------------+-------------------+--------------+-------------------+--------------+---------+-----------+-----------+------+--------------+--------------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +-------------------------------------------------------------+
- ; Registers Removed During Synthesis ;
- +----------------------------------------+--------------------+
- ; Register name ; Reason for Removal ;
- +----------------------------------------+--------------------+
- ; regs:regs|dram:dram|mem~544 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~552 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~545 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~553 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~548 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~556 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~546 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~554 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~549 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~557 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~547 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~555 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~550 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~558 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~551 ; Lost fanout ;
- ; regs:regs|dram:dram|mem~559 ; Lost fanout ;
- ; Total Number of Removed Registers = 16 ; ;
- +----------------------------------------+--------------------+
- +------------------------------------------------------+
- ; General Register Statistics ;
- +----------------------------------------------+-------+
- ; Statistic ; Value ;
- +----------------------------------------------+-------+
- ; Total registers ; 660 ;
- ; Number of registers using Synchronous Clear ; 83 ;
- ; Number of registers using Synchronous Load ; 8 ;
- ; Number of registers using Asynchronous Clear ; 0 ;
- ; Number of registers using Asynchronous Load ; 0 ;
- ; Number of registers using Clock Enable ; 617 ;
- ; Number of registers using Preset ; 0 ;
- +----------------------------------------------+-------+
- +------------------------------------------------------------------------------------------------------------------------------------------+
- ; Multiplexer Restructuring Statistics (Restructuring Performed) ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
- ; Multiplexer Inputs ; Bus Width ; Baseline Area ; Area if Restructured ; Saving if Restructured ; Registered ; Example Multiplexer Output ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
- ; 3:1 ; 5 bits ; 10 ALUTs ; 5 ALUTs ; 5 ALUTs ; Yes ; |cpu|option[5] ;
- ; 3:1 ; 12 bits ; 24 ALUTs ; 0 ALUTs ; 24 ALUTs ; Yes ; |cpu|inst[9] ;
- ; 3:1 ; 2 bits ; 4 ALUTs ; 2 ALUTs ; 2 ALUTs ; Yes ; |cpu|status[3] ;
- ; 3:1 ; 4 bits ; 8 ALUTs ; 4 ALUTs ; 4 ALUTs ; Yes ; |cpu|status[5] ;
- ; 3:1 ; 8 bits ; 16 ALUTs ; 0 ALUTs ; 16 ALUTs ; Yes ; |cpu|fsr[7] ;
- ; 3:1 ; 8 bits ; 16 ALUTs ; 0 ALUTs ; 16 ALUTs ; Yes ; |cpu|portb[7] ;
- ; 3:1 ; 8 bits ; 16 ALUTs ; 0 ALUTs ; 16 ALUTs ; Yes ; |cpu|portc[4] ;
- ; 3:1 ; 8 bits ; 16 ALUTs ; 0 ALUTs ; 16 ALUTs ; Yes ; |cpu|w[1] ;
- ; 4:1 ; 11 bits ; 22 ALUTs ; 0 ALUTs ; 22 ALUTs ; Yes ; |cpu|stack1[2] ;
- ; 27:1 ; 8 bits ; 144 ALUTs ; 0 ALUTs ; 144 ALUTs ; Yes ; |cpu|tmr0[1] ;
- ; 4:1 ; 8 bits ; 16 ALUTs ; 16 ALUTs ; 0 ALUTs ; No ; |cpu|Mux19 ;
- ; 5:1 ; 8 bits ; 24 ALUTs ; 24 ALUTs ; 0 ALUTs ; No ; |cpu|Mux13 ;
- ; 5:1 ; 10 bits ; 30 ALUTs ; 30 ALUTs ; 0 ALUTs ; No ; |cpu|Selector10 ;
- ; 11:1 ; 8 bits ; 56 ALUTs ; 48 ALUTs ; 8 ALUTs ; No ; |cpu|sbus[0] ;
- ; 13:1 ; 7 bits ; 56 ALUTs ; 56 ALUTs ; 0 ALUTs ; No ; |cpu|alu:alu|Mux1 ;
- +--------------------+-----------+---------------+----------------------+------------------------+------------+----------------------------+
- +---------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: Top-level Entity: |cpu ;
- +--------------------+-------------+----------------------------------+
- ; Parameter Name ; Value ; Type ;
- +--------------------+-------------+----------------------------------+
- ; RESET_VECTOR ; 11111111111 ; Unsigned Binary ;
- ; INDF_ADDRESS ; 000 ; Unsigned Binary ;
- ; TMR0_ADDRESS ; 001 ; Unsigned Binary ;
- ; PCL_ADDRESS ; 010 ; Unsigned Binary ;
- ; STATUS_ADDRESS ; 011 ; Unsigned Binary ;
- ; FSR_ADDRESS ; 100 ; Unsigned Binary ;
- ; PORTA_ADDRESS ; 101 ; Unsigned Binary ;
- ; PORTB_ADDRESS ; 110 ; Unsigned Binary ;
- ; PORTC_ADDRESS ; 111 ; Unsigned Binary ;
- ; ALUASEL_W ; 00 ; Unsigned Binary ;
- ; ALUASEL_SBUS ; 01 ; Unsigned Binary ;
- ; ALUASEL_K ; 10 ; Unsigned Binary ;
- ; ALUASEL_BD ; 11 ; Unsigned Binary ;
- ; ALUBSEL_W ; 00 ; Unsigned Binary ;
- ; ALUBSEL_SBUS ; 01 ; Unsigned Binary ;
- ; ALUBSEL_K ; 10 ; Unsigned Binary ;
- ; ALUBSEL_1 ; 11 ; Unsigned Binary ;
- ; ALUOP_ADD ; 0000 ; Unsigned Binary ;
- ; ALUOP_SUB ; 1000 ; Unsigned Binary ;
- ; ALUOP_AND ; 0001 ; Unsigned Binary ;
- ; ALUOP_OR ; 0010 ; Unsigned Binary ;
- ; ALUOP_XOR ; 0011 ; Unsigned Binary ;
- ; ALUOP_COM ; 0100 ; Unsigned Binary ;
- ; ALUOP_ROR ; 0101 ; Unsigned Binary ;
- ; ALUOP_ROL ; 0110 ; Unsigned Binary ;
- ; ALUOP_SWAP ; 0111 ; Unsigned Binary ;
- ; STATUS_RESET_VALUE ; 00011000 ; Unsigned Binary ;
- ; OPTION_RESET_VALUE ; 00111111 ; Unsigned Binary ;
- +--------------------+-------------+----------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +------------------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: regs:regs|dram:dram ;
- +----------------+-------+-----------------------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+-----------------------------------------+
- ; word_depth ; 70 ; Signed Integer ;
- +----------------+-------+-----------------------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +------------------------------------------------------+
- ; Parameter Settings for User Entity Instance: alu:alu ;
- +----------------+-------+-----------------------------+
- ; Parameter Name ; Value ; Type ;
- +----------------+-------+-----------------------------+
- ; ALUOP_ADD ; 0000 ; Unsigned Binary ;
- ; ALUOP_SUB ; 1000 ; Unsigned Binary ;
- ; ALUOP_AND ; 0001 ; Unsigned Binary ;
- ; ALUOP_OR ; 0010 ; Unsigned Binary ;
- ; ALUOP_XOR ; 0011 ; Unsigned Binary ;
- ; ALUOP_COM ; 0100 ; Unsigned Binary ;
- ; ALUOP_ROR ; 0101 ; Unsigned Binary ;
- ; ALUOP_ROL ; 0110 ; Unsigned Binary ;
- ; ALUOP_SWAP ; 0111 ; Unsigned Binary ;
- +----------------+-------+-----------------------------+
- Note: In order to hide this table in the UI and the text report file, please set the "Show Parameter Settings Tables in Synthesis Report" option in "Analysis and Synthesis Settings -> More Settings" to "Off".
- +-------------------------------+
- ; Analysis & Synthesis Messages ;
- +-------------------------------+
- Info: *******************************************************************
- Info: Running Quartus II Analysis & Synthesis
- Info: Version 9.0 Build 132 02/25/2009 SJ Full Version
- Info: Processing started: Mon Mar 08 21:52:09 2010
- Info: Command: quartus_map --read_settings_files=on --write_settings_files=off cpu -c cpu
- Info: Found 1 design units, including 1 entities, in source file cpu.v
- Info: Found entity 1: cpu
- Info: Elaborating entity "cpu" for the top level hierarchy
- Warning (10036): Verilog HDL or VHDL warning at cpu.v(128): object "trisa" assigned a value but never read
- Warning (10036): Verilog HDL or VHDL warning at cpu.v(129): object "trisb" assigned a value but never read
- Warning (10036): Verilog HDL or VHDL warning at cpu.v(130): object "trisc" assigned a value but never read
- Warning (10036): Verilog HDL or VHDL warning at cpu.v(145): object "d" assigned a value but never read
- Warning (10766): Verilog HDL Synthesis Attribute warning at cpu.v(363): ignoring full_case attribute on case statement with explicit default case item
- Warning (10230): Verilog HDL assignment warning at cpu.v(621): truncated value with size 32 to match size of target (8)
- Warning (10230): Verilog HDL assignment warning at cpu.v(622): truncated value with size 32 to match size of target (8)
- Warning (10230): Verilog HDL assignment warning at cpu.v(623): truncated value with size 32 to match size of target (8)
- Warning (10230): Verilog HDL assignment warning at cpu.v(624): truncated value with size 32 to match size of target (8)
- Warning (10230): Verilog HDL assignment warning at cpu.v(625): truncated value with size 32 to match size of target (8)
- Warning (10230): Verilog HDL assignment warning at cpu.v(626): truncated value with size 32 to match size of target (8)
- Warning (10230): Verilog HDL assignment warning at cpu.v(627): truncated value with size 32 to match size of target (8)
- Warning (10230): Verilog HDL assignment warning at cpu.v(628): truncated value with size 32 to match size of target (8)
- Warning (10230): Verilog HDL assignment warning at cpu.v(629): truncated value with size 32 to match size of target (8)
- Warning (10230): Verilog HDL assignment warning at cpu.v(643): truncated value with size 32 to match size of target (8)
- Warning (10230): Verilog HDL assignment warning at cpu.v(827): truncated value with size 32 to match size of target (11)
- Warning (10175): Verilog HDL warning at cpu.v(857): ignoring unsupported system task
- Warning (10175): Verilog HDL warning at cpu.v(861): ignoring unsupported system task
- Warning: Using design file regs.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
- Info: Found entity 1: regs
- Info: Elaborating entity "regs" for hierarchy "regs:regs"
- Warning: Using design file dram.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
- Info: Found entity 1: dram
- Info: Elaborating entity "dram" for hierarchy "regs:regs|dram:dram"
- Warning: Using design file alu.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
- Info: Found entity 1: alu
- Info: Elaborating entity "alu" for hierarchy "alu:alu"
- Warning: Using design file idec.v, which is not specified as a design file for the current project, but contains definitions for 1 design units and 1 entities in project
- Info: Found entity 1: idec
- Info: Elaborating entity "idec" for hierarchy "idec:idec"
- Info: Found 1 instances of uninferred RAM logic
- Info: RAM logic "regs:regs|dram:dram|mem" is uninferred due to asynchronous read logic
- Info: 16 registers lost all their fanouts during netlist optimizations. The first 16 are displayed below.
- Info: Register "regs:regs|dram:dram|mem~544" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~552" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~545" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~553" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~548" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~556" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~546" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~554" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~549" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~557" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~547" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~555" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~550" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~558" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~551" lost all its fanouts during netlist optimizations.
- Info: Register "regs:regs|dram:dram|mem~559" lost all its fanouts during netlist optimizations.
- Info: Implemented 1322 device resources after synthesis - the final resource count might be different
- Info: Implemented 30 input pins
- Info: Implemented 83 output pins
- Info: Implemented 1209 logic cells
- Info: Quartus II Analysis & Synthesis was successful. 0 errors, 22 warnings
- Info: Peak virtual memory: 175 megabytes
- Info: Processing ended: Mon Mar 08 21:52:14 2010
- Info: Elapsed time: 00:00:05
- Info: Total CPU time (on all processors): 00:00:05
English
