cpu.qsf
上传用户:bltddc
上传日期:2020-07-09
资源大小:4428k
文件大小:2k
- # -------------------------------------------------------------------------- #
- #
- # Copyright (C) 1991-2009 Altera Corporation
- # Your use of Altera Corporation's design tools, logic functions
- # and other software and tools, and its AMPP partner logic
- # functions, and any output files from any of the foregoing
- # (including device programming or simulation files), and any
- # associated documentation or information are expressly subject
- # to the terms and conditions of the Altera Program License
- # Subscription Agreement, Altera MegaCore Function License
- # Agreement, or other applicable license agreement, including,
- # without limitation, that your use is for the sole purpose of
- # programming logic devices manufactured by Altera and sold by
- # Altera or its authorized distributors. Please refer to the
- # applicable agreement for further details.
- #
- # -------------------------------------------------------------------------- #
- #
- # Quartus II
- # Version 9.0 Build 132 02/25/2009 SJ Full Version
- # Date created = 21:52:06 March 08, 2010
- #
- # -------------------------------------------------------------------------- #
- #
- # Notes:
- #
- # 1) The default values for assignments are stored in the file:
- # cpu_assignment_defaults.qdf
- # If this file doesn't exist, see file:
- # assignment_defaults.qdf
- #
- # 2) Altera recommends that you do not modify this file. This
- # file is updated automatically by the Quartus II software
- # and any changes you make may be lost or overwritten.
- #
- # -------------------------------------------------------------------------- #
- set_global_assignment -name FAMILY "Stratix II"
- set_global_assignment -name DEVICE AUTO
- set_global_assignment -name TOP_LEVEL_ENTITY cpu
- set_global_assignment -name ORIGINAL_QUARTUS_VERSION 9.0
- set_global_assignment -name PROJECT_CREATION_TIME_DATE "21:52:06 MARCH 08, 2010"
- set_global_assignment -name LAST_QUARTUS_VERSION 9.0
- set_global_assignment -name USE_GENERATED_PHYSICAL_CONSTRAINTS OFF -section_id eda_blast_fpga
- set_global_assignment -name DEVICE_FILTER_SPEED_GRADE FASTEST
- set_global_assignment -name VERILOG_FILE cpu.v
- set_instance_assignment -name PARTITION_HIERARCHY root_partition -to | -section_id Top
- set_global_assignment -name PARTITION_NETLIST_TYPE SOURCE -section_id Top
- set_global_assignment -name PARTITION_COLOR 16764057 -section_id Top
- set_global_assignment -name LL_ROOT_REGION ON -section_id "Root Region"
- set_global_assignment -name LL_MEMBER_STATE LOCKED -section_id "Root Region"