扫描程序

开发平台：

VHDL

xh.vhd：源码内容

							LIBRARY IEEE;
USE IEEE.STD_LOGIC_1164.ALL;
USE IEEE.STD_LOGIC_UNSIGNED.ALL;
ENTITY xh IS
PORT(clk,fw,en:IN STD_LOGIC;
    BT:out std_logic_vector(3 downto 0);
	D1,D2,D3,D4:in STD_LOGIC_VECTOR(3 downto 0);
	DOUT:out std_logic_vector(6 downto 0));
END xh;
ARCHITECTURE  shuchu OF xh IS 
SIGNAL STATE:STD_LOGIC_VECTOR(1 DOWNTO 0);
SIGNAL data_out: STD_LOGIC_VECTOR(3 DOWNTO 0);
begin
PROCESS(CLK)is
      BEGIN
  IF  CLK'EVENT AND CLK='1'  THEN 
   IF STATE="11"  THEN
       STATE<="00";
         else 
            STATE<=STATE+'1';
   END IF;
END IF;
END PROCESS;
PROCESS(STATE)
BEGIN
   CASE STATE IS 
            WHEN "00"  =>BT <="0001"; data_out <= D1;
            WHEN "01"  =>BT <="0010"; data_out <= D2;
            WHEN "10"  =>BT <="0100"; data_out <= D3;
            WHEN "11"  =>BT <="1000"; data_out <= D4;
            WHEN OTHERS=>NULL;
          END CASE;
   
        CASE DATA_OUT IS
          WHEN "0000"=>DOUT<="0111111";
          WHEN "0001"=>DOUT<="0000110";
          WHEN "0010"=>DOUT<="1011011";
          WHEN "0011"=>DOUT<="1001111";
          WHEN "0100"=>DOUT<="1100110";
          WHEN "0101"=>DOUT<="1101101";
          WHEN "0110"=>DOUT<="1111101";
          WHEN "0111"=>DOUT<="0000111";
          WHEN "1000"=>DOUT<="1111111";
          WHEN "1001"=>DOUT<="1101111";
          WHEN OTHERS=>DOUT<="ZZZZZZZ";
        END CASE;
  END PROCESS ;
 END shuchu;
         

						