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examp1.map.rpt
资源名称：gtt2.rar [点击查看]
上传用户：jinxingdao
上传日期：2021-04-27
资源大小：415k
文件大小：22k
源码类别：
扫描程序
开发平台：
VHDL
- Analysis & Synthesis report for examp1
- Fri Jan 22 09:53:19 2010
- Quartus II Version 7.2 Build 151 09/26/2007 SJ Full Version
- ---------------------
- ; Table of Contents ;
- ---------------------
- 1. Legal Notice
- 2. Analysis & Synthesis Summary
- 3. Analysis & Synthesis Settings
- 4. Analysis & Synthesis Source Files Read
- 5. Analysis & Synthesis Resource Usage Summary
- 6. Analysis & Synthesis Resource Utilization by Entity
- 7. Registers Removed During Synthesis
- 8. General Register Statistics
- 9. Analysis & Synthesis Messages
- ----------------
- ; Legal Notice ;
- ----------------
- Copyright (C) 1991-2007 Altera Corporation
- Your use of Altera Corporation's design tools, logic functions
- and other software and tools, and its AMPP partner logic
- functions, and any output files from any of the foregoing
- (including device programming or simulation files), and any
- associated documentation or information are expressly subject
- to the terms and conditions of the Altera Program License
- Subscription Agreement, Altera MegaCore Function License
- Agreement, or other applicable license agreement, including,
- without limitation, that your use is for the sole purpose of
- programming logic devices manufactured by Altera and sold by
- Altera or its authorized distributors. Please refer to the
- applicable agreement for further details.
- +------------------------------------------------------------------------+
- ; Analysis & Synthesis Summary ;
- +-----------------------------+------------------------------------------+
- ; Analysis & Synthesis Status ; Successful - Fri Jan 22 09:53:19 2010 ;
- ; Quartus II Version ; 7.2 Build 151 09/26/2007 SJ Full Version ;
- ; Revision Name ; examp1 ;
- ; Top-level Entity Name ; examp1 ;
- ; Family ; FLEX10K ;
- ; Total logic elements ; 188 ;
- ; Total pins ; 124 ;
- ; Total memory bits ; 0 ;
- +-----------------------------+------------------------------------------+
- +--------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Settings ;
- +----------------------------------------------------------+-----------------+---------------+
- ; Option ; Setting ; Default Value ;
- +----------------------------------------------------------+-----------------+---------------+
- ; Device ; EPF10K10QI208-4 ; ;
- ; Top-level entity name ; examp1 ; examp1 ;
- ; Family name ; FLEX10K ; Stratix II ;
- ; Use smart compilation ; Off ; Off ;
- ; Create Debugging Nodes for IP Cores ; Off ; Off ;
- ; Preserve fewer node names ; On ; On ;
- ; Disable OpenCore Plus hardware evaluation ; Off ; Off ;
- ; Verilog Version ; Verilog_2001 ; Verilog_2001 ;
- ; VHDL Version ; VHDL93 ; VHDL93 ;
- ; State Machine Processing ; Auto ; Auto ;
- ; Safe State Machine ; Off ; Off ;
- ; Extract Verilog State Machines ; On ; On ;
- ; Extract VHDL State Machines ; On ; On ;
- ; Ignore Verilog initial constructs ; Off ; Off ;
- ; Add Pass-Through Logic to Inferred RAMs ; On ; On ;
- ; Parallel Synthesis ; Off ; Off ;
- ; NOT Gate Push-Back ; On ; On ;
- ; Power-Up Don't Care ; On ; On ;
- ; Remove Redundant Logic Cells ; Off ; Off ;
- ; Remove Duplicate Registers ; On ; On ;
- ; Ignore CARRY Buffers ; Off ; Off ;
- ; Ignore CASCADE Buffers ; Off ; Off ;
- ; Ignore GLOBAL Buffers ; Off ; Off ;
- ; Ignore ROW GLOBAL Buffers ; Off ; Off ;
- ; Ignore LCELL Buffers ; Off ; Off ;
- ; Ignore SOFT Buffers ; On ; On ;
- ; Limit AHDL Integers to 32 Bits ; Off ; Off ;
- ; Auto Implement in ROM ; Off ; Off ;
- ; Optimization Technique -- FLEX 10K/10KE/10KA/ACEX 1K ; Area ; Area ;
- ; Carry Chain Length -- FLEX 10K ; 32 ; 32 ;
- ; Cascade Chain Length ; 2 ; 2 ;
- ; Auto Carry Chains ; On ; On ;
- ; Auto Open-Drain Pins ; On ; On ;
- ; Auto ROM Replacement ; On ; On ;
- ; Auto RAM Replacement ; On ; On ;
- ; Auto Clock Enable Replacement ; On ; On ;
- ; Auto Resource Sharing ; Off ; Off ;
- ; Allow Any RAM Size For Recognition ; Off ; Off ;
- ; Allow Any ROM Size For Recognition ; Off ; Off ;
- ; Ignore translate_off and synthesis_off directives ; Off ; Off ;
- ; Show Parameter Settings Tables in Synthesis Report ; On ; On ;
- ; HDL message level ; Level2 ; Level2 ;
- ; Suppress Register Optimization Related Messages ; Off ; Off ;
- ; Number of Removed Registers Reported in Synthesis Report ; 100 ; 100 ;
- ; Block Design Naming ; Auto ; Auto ;
- +----------------------------------------------------------+-----------------+---------------+
- +--------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Source Files Read ;
- +----------------------------------+-----------------+------------------------------------+--------------------------------------------------------+
- ; File Name with User-Entered Path ; Used in Netlist ; File Type ; File Name with Absolute Path ;
- +----------------------------------+-----------------+------------------------------------+--------------------------------------------------------+
- ; examp1.bdf ; yes ; User Block Diagram/Schematic File ; F:/gtt2/examp1.bdf ;
- ; xh.vhd ; yes ; User VHDL File ; F:/gtt2/xh.vhd ;
- ; 74160.bdf ; yes ; Megafunction ; d:/quratus/quartus/libraries/others/maxplus2/74160.bdf ;
- ; 74273.bdf ; yes ; Megafunction ; d:/quratus/quartus/libraries/others/maxplus2/74273.bdf ;
- +----------------------------------+-----------------+------------------------------------+--------------------------------------------------------+
- +---------------------------------------------+
- ; Analysis & Synthesis Resource Usage Summary ;
- +--------------------------------+------------+
- ; Resource ; Usage ;
- +--------------------------------+------------+
- ; Total logic elements ; 188 ;
- ; Total combinational functions ; 140 ;
- ; -- Total 4-input functions ; 48 ;
- ; -- Total 3-input functions ; 13 ;
- ; -- Total 2-input functions ; 42 ;
- ; -- Total 1-input functions ; 37 ;
- ; -- Total 0-input functions ; 0 ;
- ; Total registers ; 98 ;
- ; I/O pins ; 124 ;
- ; Maximum fan-out node ; CLK ;
- ; Maximum fan-out ; 52 ;
- ; Total fan-out ; 760 ;
- ; Average fan-out ; 2.44 ;
- +--------------------------------+------------+
- +---------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
- ; Analysis & Synthesis Resource Utilization by Entity ;
- +----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------+--------------+
- ; Compilation Hierarchy Node ; Logic Cells ; LC Registers ; Memory Bits ; Pins ; LUT-Only LCs ; Register-Only LCs ; LUT/Register LCs ; Carry Chain LCs ; Packed LCs ; Full Hierarchy Name ; Library Name ;
- +----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------+--------------+
- ; |examp1 ; 188 (2) ; 98 ; 0 ; 124 ; 90 (2) ; 48 (0) ; 50 (0) ; 0 (0) ; 0 (0) ; |examp1 ; work ;
- ; |74160:inst10| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst10 ; work ;
- ; |74160:inst12| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst12 ; work ;
- ; |74160:inst13| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst13 ; work ;
- ; |74160:inst14| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst14 ; work ;
- ; |74160:inst15| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst15 ; work ;
- ; |74160:inst2| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst2 ; work ;
- ; |74160:inst3| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst3 ; work ;
- ; |74160:inst6| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst6 ; work ;
- ; |74160:inst7| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst7 ; work ;
- ; |74160:inst8| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst8 ; work ;
- ; |74160:inst9| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst9 ; work ;
- ; |74160:inst| ; 7 (7) ; 4 ; 0 ; 0 ; 3 (3) ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; |examp1|74160:inst ; work ;
- ; |74273:10| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:10 ; work ;
- ; |74273:11| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:11 ; work ;
- ; |74273:12| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:12 ; work ;
- ; |74273:14| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:14 ; work ;
- ; |74273:15| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:15 ; work ;
- ; |74273:16| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:16 ; work ;
- ; |74273:17| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:17 ; work ;
- ; |74273:18| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:18 ; work ;
- ; |74273:19| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:19 ; work ;
- ; |74273:6| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:6 ; work ;
- ; |74273:7| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:7 ; work ;
- ; |74273:8| ; 4 (4) ; 4 ; 0 ; 0 ; 0 (0) ; 4 (4) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|74273:8 ; work ;
- ; |xh:inst16| ; 22 (22) ; 2 ; 0 ; 0 ; 20 (20) ; 0 (0) ; 2 (2) ; 0 (0) ; 0 (0) ; |examp1|xh:inst16 ; work ;
- ; |xh:inst17| ; 16 (16) ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|xh:inst17 ; work ;
- ; |xh:inst18| ; 16 (16) ; 0 ; 0 ; 0 ; 16 (16) ; 0 (0) ; 0 (0) ; 0 (0) ; 0 (0) ; |examp1|xh:inst18 ; work ;
- +----------------------------+-------------+--------------+-------------+------+--------------+-------------------+------------------+-----------------+------------+----------------------+--------------+
- Note: For table entries with two numbers listed, the numbers in parentheses indicate the number of resources of the given type used by the specific entity alone. The numbers listed outside of parentheses indicate the total resources of the given type used by the specific entity and all of its sub-entities in the hierarchy.
- +------------------------------------------------------------------------+
- ; Registers Removed During Synthesis ;
- +---------------------------------------+--------------------------------+
- ; Register name ; Reason for Removal ;
- +---------------------------------------+--------------------------------+
- ; xh:inst18|STATE[0] ; Merged with xh:inst16|STATE[0] ;
- ; xh:inst17|STATE[0] ; Merged with xh:inst16|STATE[0] ;
- ; xh:inst17|STATE[1] ; Merged with xh:inst16|STATE[1] ;
- ; xh:inst18|STATE[1] ; Merged with xh:inst16|STATE[1] ;
- ; Total Number of Removed Registers = 4 ; ;
- +---------------------------------------+--------------------------------+
- +------------------------------------------------------+
- ; General Register Statistics ;
- +----------------------------------------------+-------+
- ; Statistic ; Value ;
- +----------------------------------------------+-------+
- ; Total registers ; 98 ;
- ; Number of registers using Synchronous Clear ; 0 ;
- ; Number of registers using Synchronous Load ; 0 ;
- ; Number of registers using Asynchronous Clear ; 96 ;
- ; Number of registers using Asynchronous Load ; 0 ;
- ; Number of registers using Clock Enable ; 24 ;
- ; Number of registers using Preset ; 0 ;
- +----------------------------------------------+-------+
- +-------------------------------+
- ; Analysis & Synthesis Messages ;
- +-------------------------------+
- Info: *******************************************************************
- Info: Running Quartus II Analysis & Synthesis
- Info: Version 7.2 Build 151 09/26/2007 SJ Full Version
- Info: Processing started: Fri Jan 22 09:53:17 2010
- Info: Command: quartus_map --read_settings_files=on --write_settings_files=off examp1 -c examp1
- Info: Found 1 design units, including 1 entities, in source file examp1.bdf
- Info: Found entity 1: examp1
- Info: Found 2 design units, including 1 entities, in source file xh.vhd
- Info: Found design unit 1: xh-shuchu
- Info: Found entity 1: xh
- Info: Elaborating entity "examp1" for the top level hierarchy
- Warning: Processing legacy GDF or BDF entity "examp1" with Max+Plus II bus and instance naming rules
- Warning: Block or symbol "74160" of instance "inst6" overlaps another block or symbol
- Warning: Block or symbol "74160" of instance "inst10" overlaps another block or symbol
- Warning: Block or symbol "74160" of instance "inst13" overlaps another block or symbol
- Info: Found 1 design units, including 1 entities, in source file d:/quratus/quartus/libraries/others/maxplus2/74160.bdf
- Info: Found entity 1: 74160
- Info: Elaborating entity "74160" for hierarchy "74160:inst"
- Warning: Processing legacy GDF or BDF entity "74160" with Max+Plus II bus and instance naming rules
- Info: Elaborated megafunction instantiation "74160:inst"
- Info: Elaborating entity "xh" for hierarchy "xh:inst16"
- Warning (10492): VHDL Process Statement warning at xh.vhd(30): signal "D1" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
- Warning (10492): VHDL Process Statement warning at xh.vhd(31): signal "D2" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
- Warning (10492): VHDL Process Statement warning at xh.vhd(32): signal "D3" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
- Warning (10492): VHDL Process Statement warning at xh.vhd(33): signal "D4" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
- Warning (10492): VHDL Process Statement warning at xh.vhd(37): signal "data_out" is read inside the Process Statement but isn't in the Process Statement's sensitivity list
- Info: Found 1 design units, including 1 entities, in source file d:/quratus/quartus/libraries/others/maxplus2/74273.bdf
- Info: Found entity 1: 74273
- Info: Elaborating entity "74273" for hierarchy "74273:6"
- Warning: Processing legacy GDF or BDF entity "74273" with Max+Plus II bus and instance naming rules
- Info: Elaborated megafunction instantiation "74273:6"
- Info: Duplicate registers merged to single register
- Info: Duplicate register "xh:inst18|STATE[0]" merged to single register "xh:inst16|STATE[0]"
- Info: Duplicate register "xh:inst17|STATE[0]" merged to single register "xh:inst16|STATE[0]"
- Info: Duplicate register "xh:inst17|STATE[1]" merged to single register "xh:inst16|STATE[1]"
- Info: Duplicate register "xh:inst18|STATE[1]" merged to single register "xh:inst16|STATE[1]"
- Info: Implemented 312 device resources after synthesis - the final resource count might be different
- Info: Implemented 3 input pins
- Info: Implemented 121 output pins
- Info: Implemented 188 logic cells
- Info: Quartus II Analysis & Synthesis was successful. 0 errors, 11 warnings
- Info: Allocated 158 megabytes of memory during processing
- Info: Processing ended: Fri Jan 22 09:53:19 2010
- Info: Elapsed time: 00:00:02
