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LPC2300.s
资源名称：ucosii2.52forlpc2366.rar　[点击查看]
上传用户：ssllxx2007
上传日期：2022-06-12
资源大小：784k
文件大小：36k
源码类别：

uCOS

开发平台：

C/C++

LPC2300.s：源码内容
  1. ;/*****************************************************************************/
  2. ;/* LPC2300.S: Startup file for Philips LPC2300 device series                 */
  3. ;/*****************************************************************************/
  4. ;/* <<< Use Configuration Wizard in Context Menu >>>                          */
  5. ;/*****************************************************************************/
  6. ;/* This file is part of the uVision/ARM development tools.                   */
  7. ;/* Copyright (c) 2007 Keil - An ARM Company. All rights reserved.            */
  8. ;/* This software may only be used under the terms of a valid, current,       */
  9. ;/* end user licence from KEIL for a compatible version of KEIL software      */
  10. ;/* development tools. Nothing else gives you the right to use this software. */
  11. ;/*****************************************************************************/
  14. ;/*
  15. ; *  The LPC2300.S code is executed after CPU Reset. This file may be 
  16. ; *  translated with the following SET symbols. In uVision these SET 
  17. ; *  symbols are entered under Options - ASM - Define.
  18. ; *
  19. ; *  NO_CLOCK_SETUP: when set the startup code will not initialize Clock 
  20. ; *  (used mostly when clock is already initialized from script .ini 
  21. ; *  file).
  22. ; *
  23. ; *  NO_EMC_SETUP: when set the startup code will not initializes External 
  24. ; *  Memory Controller (used mostly when external memory is already initialized 
  25. ; *  and loaded from script .ini file).
  26. ; *
  27. ; *  RAM_INTVEC: when set the startup code copies exception vectors 
  28. ; *  from on-chip Flash to on-chip RAM.
  29. ; *
  30. ; *  REMAP: when set the startup code initializes the register MEMMAP 
  31. ; *  which overwrites the settings of the CPU configuration pins. The 
  32. ; *  startup and interrupt vectors are remapped from:
  33. ; *     0x00000000  default setting (not remapped)
  34. ; *     0x40000000  when RAM_MODE is used
  35. ; *     0x80000000  when EXTMEM_MODE is used
  36. ; *
  37. ; *  EXTMEM_MODE: when set the device is configured for code execution
  38. ; *  from external memory starting at address 0x80000000.
  39. ; *
  40. ; *  RAM_MODE: when set the device is configured for code execution
  41. ; *  from on-chip RAM starting at address 0x40000000. 
  42. ; */
  45. ; Standard definitions of Mode bits and Interrupt (I & F) flags in PSRs
  47. Mode_USR        EQU     0x10
  48. Mode_FIQ        EQU     0x11
  49. Mode_IRQ        EQU     0x12
  50. Mode_SVC        EQU     0x13
  51. Mode_ABT        EQU     0x17
  52. Mode_UND        EQU     0x1B
  53. Mode_SYS        EQU     0x1F
  55. I_Bit           EQU     0x80            ; when I bit is set, IRQ is disabled
  56. F_Bit           EQU     0x40            ; when F bit is set, FIQ is disabled
  59. ;----------------------- Memory Definitions ------------------------------------
  61. ; Internal Memory Base Addresses
  62. FLASH_BASE      EQU     0x00000000   
  63. RAM_BASE        EQU     0x40000000
  64. EXTMEM_BASE     EQU     0x80000000
  66. ; External Memory Base Addresses
  67. STA_MEM0_BASE   EQU     0x80000000
  68. STA_MEM1_BASE   EQU     0x81000000
  71. ;----------------------- Stack and Heap Definitions ----------------------------
  73. ;// <h> Stack Configuration (Stack Sizes in Bytes)
  74. ;//   <o0> Undefined Mode      <0x0-0xFFFFFFFF:8>
  75. ;//   <o1> Supervisor Mode     <0x0-0xFFFFFFFF:8>
  76. ;//   <o2> Abort Mode          <0x0-0xFFFFFFFF:8>
  77. ;//   <o3> Fast Interrupt Mode <0x0-0xFFFFFFFF:8>
  78. ;//   <o4> Interrupt Mode      <0x0-0xFFFFFFFF:8>
  79. ;//   <o5> User/System Mode    <0x0-0xFFFFFFFF:8>
  80. ;// </h>
  82. UND_Stack_Size  EQU     0x00000000
  83. SVC_Stack_Size  EQU     0x00000008
  84. ABT_Stack_Size  EQU     0x00000000
  85. FIQ_Stack_Size  EQU     0x00000000
  86. IRQ_Stack_Size  EQU     0x00000100
  87. USR_Stack_Size  EQU     0x00000400
  89. ISR_Stack_Size  EQU     (UND_Stack_Size + SVC_Stack_Size + ABT_Stack_Size + 
  90.                          FIQ_Stack_Size + IRQ_Stack_Size)
  92.                 AREA    STACK, NOINIT, READWRITE, ALIGN=3
  94. Stack_Mem       SPACE   USR_Stack_Size
  95. __initial_sp    SPACE   ISR_Stack_Size
  97. Stack_Top
  100. ;// <h> Heap Configuration
  101. ;//   <o>  Heap Size (in Bytes) <0x0-0xFFFFFFFF>
  102. ;// </h>
  104. Heap_Size       EQU     0x00000000
  106.                 AREA    HEAP, NOINIT, READWRITE, ALIGN=3
  107. __heap_base
  108. Heap_Mem        SPACE   Heap_Size
  109. __heap_limit
  112. ;----------------------- System Control Block (SCB) Module Definitions ---------
  114. SCB_BASE        EQU     0xE01FC000      ; SCB Base Address
  115. PLLCON_OFS      EQU     0x80            ; PLL Control Offset
  116. PLLCFG_OFS      EQU     0x84            ; PLL Configuration Offset
  117. PLLSTAT_OFS     EQU     0x88            ; PLL Status Offset
  118. PLLFEED_OFS     EQU     0x8C            ; PLL Feed Offset
  119. CCLKCFG_OFS     EQU     0x104           ; CPU Clock Divider Reg Offset
  120. USBCLKCFG_OFS   EQU     0x108           ; USB Clock Divider Reg Offset
  121. CLKSRCSEL_OFS   EQU     0x10C           ; Clock Source Select Reg Offset
  122. SCS_OFS         EQU     0x1A0           ; System Control and Status Reg Offset
  123. PCLKSEL0_OFS    EQU     0x1A8           ; Peripheral Clock Select Reg 0 Offset
  124. PCLKSEL1_OFS    EQU     0x1AC           ; Peripheral Clock Select Reg 1 Offset
  126. PCON_OFS        EQU     0x0C0           ; Power Mode Control Reg Offset
  127. PCONP_OFS       EQU     0x0C4           ; Power Control for Periphs Reg Offset
  129. ; Constants
  130. OSCRANGE        EQU     (1<<4)          ; Oscillator Range Select
  131. OSCEN           EQU     (1<<5)          ; Main oscillator Enable
  132. OSCSTAT         EQU     (1<<6)          ; Main Oscillator Status
  133. PLLCON_PLLE     EQU     (1<<0)          ; PLL Enable
  134. PLLCON_PLLC     EQU     (1<<1)          ; PLL Connect
  135. PLLSTAT_M       EQU     (0x7FFF<<0)     ; PLL M Value
  136. PLLSTAT_N       EQU     (0xFF<<16)      ; PLL N Value
  137. PLLSTAT_PLOCK   EQU     (1<<26)         ; PLL Lock Status
  139. ;// <e> Clock Setup
  140. ;//   <h> System Controls and Status Register (SCS)
  141. ;//     <o1.4>    OSCRANGE: Main Oscillator Range Select
  142. ;//                     <0=>  1 MHz to 20 MHz
  143. ;//                     <1=> 15 MHz to 24 MHz
  144. ;//     <e1.5>       OSCEN: Main Oscillator Enable
  145. ;//     </e>
  146. ;//   </h>
  147. ;//
  148. ;//   <h> Clock Source Select Register (CLKSRCSEL)
  149. ;//     <o2.0..1>   CLKSRC: PLL Clock Source Selection
  150. ;//                     <0=> Internal RC oscillator
  151. ;//                     <1=> Main oscillator
  152. ;//                     <1=> RTC oscillator
  153. ;//   </h>
  154. ;//
  155. ;//   <h> PLL Configuration Register (PLLCFG)
  156. ;//                     <i> PLL_clk = (2* M * PLL_clk_src) / N
  157. ;//     <o3.0..14>    MSEL: PLL Multiplier Selection
  158. ;//                     <1-32768><#-1>
  159. ;//                     <i> M Value
  160. ;//     <o3.16..23>   NSEL: PLL Divider Selection
  161. ;//                     <1-256><#-1>
  162. ;//                     <i> N Value
  163. ;//   </h>
  164. ;//
  165. ;//   <h> CPU Clock Configuration Register (CCLKCFG)
  166. ;//     <o4.0..7>  CCLKSEL: Divide Value for CPU Clock from PLL
  167. ;//                     <1-256><#-1>
  168. ;//   </h>
  169. ;//
  170. ;//   <h> USB Clock Configuration Register (USBCLKCFG)
  171. ;//     <o5.0..3>   USBSEL: Divide Value for USB Clock from PLL
  172. ;//                     <1-16><#-1>
  173. ;//   </h>
  174. ;//
  175. ;//   <h> Peripheral Clock Selection Register 0 (PCLKSEL0)
  176. ;//     <o6.0..1>      PCLK_WDT: Peripheral Clock Selection for WDT
  177. ;//                     <0=> Pclk = Cclk / 4
  178. ;//                     <1=> Pclk = Cclk
  179. ;//                     <2=> Pclk = Cclk / 2
  180. ;//                     <3=> Pclk = Hclk / 8
  181. ;//     <o6.2..3>   PCLK_TIMER0: Peripheral Clock Selection for TIMER0
  182. ;//                     <0=> Pclk = Cclk / 4
  183. ;//                     <1=> Pclk = Cclk
  184. ;//                     <2=> Pclk = Cclk / 2
  185. ;//                     <3=> Pclk = Hclk / 8
  186. ;//     <o6.4..5>   PCLK_TIMER1: Peripheral Clock Selection for TIMER1
  187. ;//                     <0=> Pclk = Cclk / 4
  188. ;//                     <1=> Pclk = Cclk
  189. ;//                     <2=> Pclk = Cclk / 2
  190. ;//                     <3=> Pclk = Hclk / 8
  191. ;//     <o6.6..7>    PCLK_UART0: Peripheral Clock Selection for UART0
  192. ;//                     <0=> Pclk = Cclk / 4
  193. ;//                     <1=> Pclk = Cclk
  194. ;//                     <2=> Pclk = Cclk / 2
  195. ;//                     <3=> Pclk = Hclk / 8
  196. ;//     <o6.8..9>    PCLK_UART1: Peripheral Clock Selection for UART1
  197. ;//                     <0=> Pclk = Cclk / 4
  198. ;//                     <1=> Pclk = Cclk
  199. ;//                     <2=> Pclk = Cclk / 2
  200. ;//                     <3=> Pclk = Hclk / 8
  201. ;//     <o6.10..11>   PCLK_PWM0: Peripheral Clock Selection for PWM0
  202. ;//                     <0=> Pclk = Cclk / 4
  203. ;//                     <1=> Pclk = Cclk
  204. ;//                     <2=> Pclk = Cclk / 2
  205. ;//                     <3=> Pclk = Hclk / 8
  206. ;//     <o6.12..13>   PCLK_PWM1: Peripheral Clock Selection for PWM1
  207. ;//                     <0=> Pclk = Cclk / 4
  208. ;//                     <1=> Pclk = Cclk
  209. ;//                     <2=> Pclk = Cclk / 2
  210. ;//                     <3=> Pclk = Hclk / 8
  211. ;//     <o6.14..15>   PCLK_I2C0: Peripheral Clock Selection for I2C0
  212. ;//                     <0=> Pclk = Cclk / 4
  213. ;//                     <1=> Pclk = Cclk
  214. ;//                     <2=> Pclk = Cclk / 2
  215. ;//                     <3=> Pclk = Hclk / 8
  216. ;//     <o6.16..17>    PCLK_SPI: Peripheral Clock Selection for SPI
  217. ;//                     <0=> Pclk = Cclk / 4
  218. ;//                     <1=> Pclk = Cclk
  219. ;//                     <2=> Pclk = Cclk / 2
  220. ;//                     <3=> Pclk = Hclk / 8
  221. ;//     <o6.18..19>    PCLK_RTC: Peripheral Clock Selection for RTC
  222. ;//                     <0=> Pclk = Cclk / 4
  223. ;//                     <1=> Pclk = Cclk
  224. ;//                     <2=> Pclk = Cclk / 2
  225. ;//                     <3=> Pclk = Hclk / 8
  226. ;//     <o6.20..21>   PCLK_SSP1: Peripheral Clock Selection for SSP1
  227. ;//                     <0=> Pclk = Cclk / 4
  228. ;//                     <1=> Pclk = Cclk
  229. ;//                     <2=> Pclk = Cclk / 2
  230. ;//                     <3=> Pclk = Hclk / 8
  231. ;//     <o6.22..23>    PCLK_DAC: Peripheral Clock Selection for DAC
  232. ;//                     <0=> Pclk = Cclk / 4
  233. ;//                     <1=> Pclk = Cclk
  234. ;//                     <2=> Pclk = Cclk / 2
  235. ;//                     <3=> Pclk = Hclk / 8
  236. ;//     <o6.24..25>    PCLK_ADC: Peripheral Clock Selection for ADC
  237. ;//                     <0=> Pclk = Cclk / 4
  238. ;//                     <1=> Pclk = Cclk
  239. ;//                     <2=> Pclk = Cclk / 2
  240. ;//                     <3=> Pclk = Hclk / 8
  241. ;//     <o6.26..27>   PCLK_CAN1: Peripheral Clock Selection for CAN1
  242. ;//                     <0=> Pclk = Cclk / 4
  243. ;//                     <1=> Pclk = Cclk
  244. ;//                     <2=> Pclk = Cclk / 2
  245. ;//                     <3=> Pclk = Hclk / 6
  246. ;//     <o6.28..29>   PCLK_CAN2: Peripheral Clock Selection for CAN2
  247. ;//                     <0=> Pclk = Cclk / 4
  248. ;//                     <1=> Pclk = Cclk
  249. ;//                     <2=> Pclk = Cclk / 2
  250. ;//                     <3=> Pclk = Hclk / 6
  251. ;//     <o6.30..31>    PCLK_ACF: Peripheral Clock Selection for ACF
  252. ;//                     <0=> Pclk = Cclk / 4
  253. ;//                     <1=> Pclk = Cclk
  254. ;//                     <2=> Pclk = Cclk / 2
  255. ;//                     <3=> Pclk = Hclk / 6
  256. ;//   </h>
  257. ;//
  258. ;//   <h> Peripheral Clock Selection Register 1 (PCLKSEL1)
  259. ;//     <o7.0..1>  PCLK_BAT_RAM: Peripheral Clock Selection for the Battery Supported RAM
  260. ;//                     <0=> Pclk = Cclk / 4
  261. ;//                     <1=> Pclk = Cclk
  262. ;//                     <2=> Pclk = Cclk / 2
  263. ;//                     <3=> Pclk = Hclk / 8
  264. ;//     <o7.2..3>     PCLK_GPIO: Peripheral Clock Selection for GPIOs
  265. ;//                     <0=> Pclk = Cclk / 4
  266. ;//                     <1=> Pclk = Cclk
  267. ;//                     <2=> Pclk = Cclk / 2
  268. ;//                     <3=> Pclk = Hclk / 8
  269. ;//     <o7.4..5>      PCLK_PCB: Peripheral Clock Selection for Pin Connect Block
  270. ;//                     <0=> Pclk = Cclk / 4
  271. ;//                     <1=> Pclk = Cclk
  272. ;//                     <2=> Pclk = Cclk / 2
  273. ;//                     <3=> Pclk = Hclk / 8
  274. ;//     <o7.6..7>     PCLK_I2C1: Peripheral Clock Selection for I2C1
  275. ;//                     <0=> Pclk = Cclk / 4
  276. ;//                     <1=> Pclk = Cclk
  277. ;//                     <2=> Pclk = Cclk / 2
  278. ;//                     <3=> Pclk = Hclk / 8
  279. ;//     <o7.10..11>   PCLK_SSP0: Peripheral Clock Selection for SSP0
  280. ;//                     <0=> Pclk = Cclk / 4
  281. ;//                     <1=> Pclk = Cclk
  282. ;//                     <2=> Pclk = Cclk / 2
  283. ;//                     <3=> Pclk = Hclk / 8
  284. ;//     <o7.12..13> PCLK_TIMER2: Peripheral Clock Selection for TIMER2
  285. ;//                     <0=> Pclk = Cclk / 4
  286. ;//                     <1=> Pclk = Cclk
  287. ;//                     <2=> Pclk = Cclk / 2
  288. ;//                     <3=> Pclk = Hclk / 8
  289. ;//     <o7.14..15> PCLK_TIMER3: Peripheral Clock Selection for TIMER3
  290. ;//                     <0=> Pclk = Cclk / 4
  291. ;//                     <1=> Pclk = Cclk
  292. ;//                     <2=> Pclk = Cclk / 2
  293. ;//                     <3=> Pclk = Hclk / 8
  294. ;//     <o7.16..17>  PCLK_UART2: Peripheral Clock Selection for UART2
  295. ;//                     <0=> Pclk = Cclk / 4
  296. ;//                     <1=> Pclk = Cclk
  297. ;//                     <2=> Pclk = Cclk / 2
  298. ;//                     <3=> Pclk = Hclk / 8
  299. ;//     <o7.18..19>  PCLK_UART3: Peripheral Clock Selection for UART3
  300. ;//                     <0=> Pclk = Cclk / 4
  301. ;//                     <1=> Pclk = Cclk
  302. ;//                     <2=> Pclk = Cclk / 2
  303. ;//                     <3=> Pclk = Hclk / 8
  304. ;//     <o7.20..21>   PCLK_I2C2: Peripheral Clock Selection for I2C2
  305. ;//                     <0=> Pclk = Cclk / 4
  306. ;//                     <1=> Pclk = Cclk
  307. ;//                     <2=> Pclk = Cclk / 2
  308. ;//                     <3=> Pclk = Hclk / 8
  309. ;//     <o7.22..23>    PCLK_I2S: Peripheral Clock Selection for I2S
  310. ;//                     <0=> Pclk = Cclk / 4
  311. ;//                     <1=> Pclk = Cclk
  312. ;//                     <2=> Pclk = Cclk / 2
  313. ;//                     <3=> Pclk = Hclk / 8
  314. ;//     <o7.24..25>    PCLK_MCI: Peripheral Clock Selection for MCI
  315. ;//                     <0=> Pclk = Cclk / 4
  316. ;//                     <1=> Pclk = Cclk
  317. ;//                     <2=> Pclk = Cclk / 2
  318. ;//                     <3=> Pclk = Hclk / 8
  319. ;//     <o7.28..29> PCLK_SYSCON: Peripheral Clock Selection for System Control Block
  320. ;//                     <0=> Pclk = Cclk / 4
  321. ;//                     <1=> Pclk = Cclk
  322. ;//                     <2=> Pclk = Cclk / 2
  323. ;//                     <3=> Pclk = Hclk / 8
  324. ;//   </h>
  325. ;//   <h> Power Control for Peripherals Register (PCONP)
  326. ;//     <o8.31>     PCUSB: USB interface power/clock enable
  327. ;//     <o8.30>     PCENET: Ethernet block power/clock enable
  328. ;//     <o8.29>     PCGPDMA: GP DMA function power/clock enable
  329. ;//     <o8.28>     PCSDC: SD card interface power/clock enable
  330. ;//     <o8.27>     PCI2S: I2S interface power/clock enable
  331. ;//     <o8.26>     PCI2C2: I2C interface 2 power/clock enable
  332. ;//     <o8.25>     PCUART3: UART 3 power/clock enable
  333. ;//     <o8.24>     PCUART2: UART 2 power/clock enable
  334. ;//     <o8.23>     PCTIM3: Timer 3 power/clock enable
  335. ;//     <o8.22>     PCTIM2: Timer 2 power/clock enable
  336. ;//     <o8.21>     PCSSP0: SSP interface 0 power/clock enable
  337. ;//     <o8.19>     PCI2C1: I2C interface 1 power/clock enable
  338. ;//     <o8.14>     PCAN2: CAN controller 2 power/clock enable
  339. ;//     <o8.13>     PCAN1: CAN controller 1 power/clock enable
  340. ;//     <o8.12>     PCAD: A/D converter power/clock enable
  341. ;//     <o8.11>     PCEMC: External memory controller power/clock enable
  342. ;//     <o8.10>     PCSSP1: SSP interface 1 power/clock enable
  343. ;//     <o8.9>      PCRTC: RTC power/clock enable
  344. ;//     <o8.8>      PCSPI: SPI interface power/clock enable
  345. ;//     <o8.7>      PCI2C0: I2C interface 0 power/clock enable
  346. ;//     <o8.6>      PCPWM1: PWM 1 power/clock enable
  347. ;//     <o8.4>      PCUART1: UART 1 power/clock enable
  348. ;//     <o8.3>      PCUART0: UART 0 power/clock enable
  349. ;//     <o8.2>      PCTIM1: Timer/Counter 1 power/clock enable
  350. ;//     <o8.1>      PCTIM0: Timer/Counter 0 power/clock enable
  351. ;//   </h>
  352. ;// </e>
  353. CLOCK_SETUP     EQU     1
  354. SCS_Val         EQU     0x00000020
  355. CLKSRCSEL_Val   EQU     0x00000001
  356. PLLCFG_Val      EQU     0x0000000B
  357. CCLKCFG_Val     EQU     0x00000005
  358. USBCLKCFG_Val   EQU     0x00000005
  359. PCLKSEL0_Val    EQU     0x00000000
  360. PCLKSEL1_Val    EQU     0x00000000
  361. PCONP_Val       EQU     0x04280FDE
  363. ;----------------------- Memory Accelerator Module (MAM) Definitions -----------
  365. MAM_BASE        EQU     0xE01FC000      ; MAM Base Address
  366. MAMCR_OFS       EQU     0x00            ; MAM Control Offset
  367. MAMTIM_OFS      EQU     0x04            ; MAM Timing Offset
  369. ;// <e> MAM Setup
  370. ;//   <o1.0..1>   MAM Control
  371. ;//               <0=> Disabled
  372. ;//               <1=> Partially Enabled
  373. ;//               <2=> Fully Enabled
  374. ;//               <i> Mode
  375. ;//   <o2.0..2>   MAM Timing
  376. ;//               <0=> Reserved  <1=> 1   <2=> 2   <3=> 3
  377. ;//               <4=> 4         <5=> 5   <6=> 6   <7=> 7
  378. ;//               <i> Fetch Cycles
  379. ;// </e>
  380. MAM_SETUP       EQU     1
  381. MAMCR_Val       EQU     0x00000002
  382. MAMTIM_Val      EQU     0x00000004
  385. ;----------------------- Pin Connect Block Definitions -------------------------
  387. PCB_BASE            EQU 0xE002C000      ; PCB Base Address
  388. PINSEL0_OFS         EQU 0x00            ; PINSEL0  Address Offset
  389. PINSEL1_OFS         EQU 0x04            ; PINSEL1  Address Offset
  390. PINSEL2_OFS         EQU 0x08            ; PINSEL2  Address Offset
  391. PINSEL3_OFS         EQU 0x0C            ; PINSEL3  Address Offset
  392. PINSEL4_OFS         EQU 0x10            ; PINSEL4  Address Offset
  393. PINSEL5_OFS         EQU 0x14            ; PINSEL5  Address Offset
  394. PINSEL6_OFS         EQU 0x18            ; PINSEL6  Address Offset
  395. PINSEL7_OFS         EQU 0x1C            ; PINSEL7  Address Offset
  396. PINSEL8_OFS         EQU 0x20            ; PINSEL8  Address Offset
  397. PINSEL9_OFS         EQU 0x24            ; PINSEL9  Address Offset
  398. PINSEL10_OFS        EQU 0x28            ; PINSEL10 Address Offset
  401. ;----------------------- External Memory Controller (EMC) Definitons -----------
  403. EMC_BASE            EQU 0xFFE08000      ; EMC Base Address
  405. EMC_CTRL_OFS        EQU 0x000           ; EMCControl
  406. EMC_STAT_OFS        EQU 0x004           ; EMCStatus
  407. EMC_CONFIG_OFS      EQU 0x008           ; EMCConfig
  408. EMC_STA_CFG0_OFS    EQU 0x200           ; EMCStaticConfig0
  409. EMC_STA_WWEN0_OFS   EQU 0x204           ; EMCStaticWaitWen0
  410. EMC_STA_WOEN0_OFS   EQU 0x208           ; EMCStaticWaitOen0
  411. EMC_STA_WRD0_OFS    EQU 0x20C           ; EMCStaticWaitRd0
  412. EMC_STA_WPAGE0_OFS  EQU 0x210           ; EMCStaticWaitPage0
  413. EMC_STA_WWR0_OFS    EQU 0x214           ; EMCStaticWaitWr0
  414. EMC_STA_WTURN0_OFS  EQU 0x218           ; EMCStaticWaitTurn0
  415. EMC_STA_CFG1_OFS    EQU 0x220           ; EMCStaticConfig1
  416. EMC_STA_WWEN1_OFS   EQU 0x224           ; EMCStaticWaitWen1
  417. EMC_STA_WOEN1_OFS   EQU 0x228           ; EMCStaticWaitOen1
  418. EMC_STA_WRD1_OFS    EQU 0x22C           ; EMCStaticWaitRd1
  419. EMC_STA_WPAGE1_OFS  EQU 0x230           ; EMCStaticWaitPage1
  420. EMC_STA_WWR1_OFS    EQU 0x234           ; EMCStaticWaitWr1
  421. EMC_STA_WTURN1_OFS  EQU 0x238           ; EMCStaticWaitTurn1
  422. EMC_STA_EXT_W_OFS   EQU 0x880           ; EMCStaticExtendedWait
  424. BUFEN_Const         EQU (1 << 19)       ; Buffer enable bit
  425. EMC_PCONP_Const     EQU (1 << 11)       ; PCONP val to enable power for EMC
  427. ; External Memory Pins definitions
  428. ; pin functions for external memory interfacing
  429. EMC_PINSEL6_Val     EQU 0x00005555      ; D0 .. D7
  430. EMC_PINSEL8_Val     EQU 0x55555555      ; A0 .. A15
  431. EMC_PINSEL9_Val     EQU 0x50090000;     ; !OE, !WE (BLS0 because of errata), !CS0, !CS1
  433. ;//     External Memory Controller Setup (EMC) ---------------------------------
  434. ;// <e> External Memory Controller Setup (EMC)
  435. EMC_SETUP           EQU 1
  437. ;//   <h> EMC Control Register (EMCControl)
  438. ;//     <i> Controls operation of the memory controller
  439. ;//     <o0.2> L: Low-power mode enable
  440. ;//     <o0.1> M: Address mirror enable
  441. ;//     <o0.0> E: EMC enable
  442. ;//   </h>
  443. EMC_CTRL_Val        EQU 0x00000001
  445. ;//   <h> EMC Configuration Register (EMCConfig)
  446. ;//     <o0.0> Endian mode
  447. ;//       <0=> Little-endian
  448. ;//       <1=> Big-endian
  449. ;//   </h>
  450. EMC_CONFIG_Val      EQU 0x00000000
  452. ;//       Configure External Bus Behaviour for Static CS0 Area -----------------
  453. ;//   <e> Configure External Bus Behaviour for Static CS0 Area
  454. EMC_STACS0_SETUP    EQU 1
  456. ;//     <h> Static Memory Configuration Register (EMCStaticConfig0)
  457. ;//       <i> Defines the configuration information for the static memory CS0
  458. ;//       <o0.20> WP: Write protect
  459. ;//       <o0.19> B: Write buffer enable
  460. ;//       <o0.8> EW: Extended wait enable
  461. ;//       <o0.6> PC: Chip select polarity
  462. ;//         <0=> Active LOW chip select
  463. ;//         <1=> Active HIGH chip select
  464. ;//       <o0.3> PM: Async page mode enable
  465. ;//       <o0.0..1> MW: Memory width
  466. ;//         <0=> 8 bit
  467. ;//         <1=> 16 bit
  468. ;//         <2=> 32 bit
  469. ;//     </h>
  470. EMC_STA_CFG0_Val    EQU 0x00000000
  472. ;//     <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen0)
  473. ;//       <i> Selects the delay from CS0 to write enable
  474. ;//       <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
  475. ;//         <i> The delay is in CCLK cycles
  476. ;//     </h>
  477. EMC_STA_WWEN0_Val   EQU 0x00000002
  479. ;//     <h> Static Memory Output Enable Delay register (EMCStaticWaitOen0)
  480. ;//       <i> Selects the delay from CS0 or address change, whichever is later, to output enable
  481. ;//       <o.0..3> WAITOEN: Wait output enable <0-15>
  482. ;//         <i> The delay is in CCLK cycles
  483. ;//     </h>
  484. EMC_STA_WOEN0_Val   EQU 0x00000002
  485.                                       
  486. ;//     <h> Static Memory Read Delay Register (EMCStaticWaitRd0)
  487. ;//       <i> Selects the delay from CS0 to a read access
  488. ;//       <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
  489. ;//         <i> The delay is in CCLK cycles
  490. ;//     </h>
  491. EMC_STA_WRD0_Val    EQU 0x0000001F
  493. ;//     <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
  494. ;//       <i> Selects the delay for asynchronous page mode sequential accesses for CS0
  495. ;//       <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
  496. ;//         <i> The delay is in CCLK cycles
  497. ;//     </h>
  498. EMC_STA_WPAGE0_Val  EQU 0x0000001F
  500. ;//     <h> Static Memory Write Delay Register (EMCStaticWaitWr0)
  501. ;//       <i> Selects the delay from CS0 to a write access
  502. ;//       <o.0..4> WAITWR: Write wait states <2-33> <#-2>
  503. ;//         <i> The delay is in CCLK cycles
  504. ;//     </h>
  505. EMC_STA_WWR0_Val    EQU 0x0000001F
  507. ;//     <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn0)
  508. ;//       <i> Selects the number of bus turnaround cycles for CS0
  509. ;//       <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
  510. ;//         <i> The delay is in CCLK cycles
  511. ;//     </h>
  512. EMC_STA_WTURN0_Val  EQU 0x0000000F
  514. ;//   </e> End of Static Setup for Static CS0 Area
  516. ;//       Configure External Bus Behaviour for Static CS1 Area -----------------
  517. ;//   <e> Configure External Bus Behaviour for Static CS1 Area
  518. EMC_STACS1_SETUP    EQU 0
  520. ;//     <h> Static Memory Configuration Register (EMCStaticConfig1)
  521. ;//       <i> Defines the configuration information for the static memory CS1
  522. ;//       <o0.20> WP: Write protect
  523. ;//       <o0.19> B: Write buffer enable
  524. ;//       <o0.8> EW: Extended wait enable
  525. ;//       <o0.6> PC: Chip select polarity
  526. ;//         <0=> Active LOW chip select
  527. ;//         <1=> Active HIGH chip select
  528. ;//       <o0.3> PM: Async page mode enable
  529. ;//       <o0.0..1> MW: Memory width
  530. ;//         <0=> 8 bit
  531. ;//         <1=> 16 bit
  532. ;//         <2=> 32 bit
  533. ;//     </h>
  534. EMC_STA_CFG1_Val    EQU 0x00000000
  536. ;//     <h> Static Memory Write Enable Delay Register (EMCStaticWaitWen1)
  537. ;//       <i> Selects the delay from CS1 to write enable
  538. ;//       <o.0..3> WAITWEN: Wait write enable <1-16> <#-1>
  539. ;//         <i> The delay is in CCLK cycles
  540. ;//     </h>
  541. EMC_STA_WWEN1_Val   EQU 0x00000000
  543. ;//     <h> Static Memory Output Enable Delay register (EMCStaticWaitOen1)
  544. ;//       <i> Selects the delay from CS1 or address change, whichever is later, to output enable
  545. ;//       <o.0..3> WAITOEN: Wait output enable <0-15>
  546. ;//         <i> The delay is in CCLK cycles
  547. ;//     </h>
  548. EMC_STA_WOEN1_Val   EQU 0x00000000
  549.                                       
  550. ;//     <h> Static Memory Read Delay Register (EMCStaticWaitRd1)
  551. ;//       <i> Selects the delay from CS1 to a read access
  552. ;//       <o.0..4> WAITRD: Non-page mode read wait states or asynchronous page mode read first access wait states <1-32> <#-1>
  553. ;//         <i> The delay is in CCLK cycles
  554. ;//     </h>
  555. EMC_STA_WRD1_Val    EQU 0x0000001F
  557. ;//     <h> Static Memory Page Mode Read Delay Register (EMCStaticWaitPage0)
  558. ;//       <i> Selects the delay for asynchronous page mode sequential accesses for CS1
  559. ;//       <o.0..4> WAITPAGE: Asynchronous page mode read after the first read wait states <1-32> <#-1>
  560. ;//         <i> The delay is in CCLK cycles
  561. ;//     </h>
  562. EMC_STA_WPAGE1_Val  EQU 0x0000001F
  564. ;//     <h> Static Memory Write Delay Register (EMCStaticWaitWr1)
  565. ;//       <i> Selects the delay from CS1 to a write access
  566. ;//       <o.0..4> WAITWR: Write wait states <2-33> <#-2>
  567. ;//         <i> The delay is in CCLK cycles
  568. ;//     </h>
  569. EMC_STA_WWR1_Val    EQU  0x0000001F
  571. ;//     <h> Static Memory Turn Round Delay Register (EMCStaticWaitTurn1)
  572. ;//       <i> Selects the number of bus turnaround cycles for CS1
  573. ;//       <o.0..4> WAITTURN: Bus turnaround cycles <1-16> <#-1>
  574. ;//         <i> The delay is in CCLK cycles
  575. ;//     </h>
  576. EMC_STA_WTURN1_Val  EQU 0x0000000F
  578. ;//   </e> End of Static Setup for Static CS1 Area
  580. ;//   <h> Static Memory Extended Wait Register (EMCStaticExtendedWait)
  581. ;//     <i> Time long static memory read and write transfers
  582. ;//     <o.0..9> EXTENDEDWAIT: Extended wait time out <1-64><#-1>
  583. ;//       <i> The delay is in (16 * CCLK) cycles
  584. ;//   </h>
  585. EMC_STA_EXT_W_Val   EQU 0x00000000
  587. ;// </e> End of EMC Setup
  590. ; Area Definition and Entry Point
  591. ;  Startup Code must be linked first at Address at which it expects to run.
  593.                 AREA    RESET, CODE, READONLY
  594.                 ARM
  597. ; Exception Vectors
  598. ;  Mapped to Address 0.
  599. ;  Absolute addressing mode must be used.
  600. ;  Dummy Handlers are implemented as infinite loops which can be modified.
  602. Vectors         LDR     PC, Reset_Addr         
  603.                 LDR     PC, Undef_Addr
  604.                 LDR     PC, SWI_Addr
  605.                 LDR     PC, PAbt_Addr
  606.                 LDR     PC, DAbt_Addr
  607.                 NOP                            ; Reserved Vector 
  608. ;               LDR     PC, IRQ_Addr
  609.                 LDR     PC, [PC, #-0x0120]     ; Vector from VicVectAddr
  610.                 LDR     PC, FIQ_Addr
  612. Reset_Addr      DCD     Reset_Handler
  613. Undef_Addr      DCD     Undef_Handler
  614. SWI_Addr        DCD     SWI_Handler
  615. PAbt_Addr       DCD     PAbt_Handler
  616. DAbt_Addr       DCD     DAbt_Handler
  617.                 DCD     0                      ; Reserved Address 
  618. IRQ_Addr        DCD     IRQ_Handler
  619. FIQ_Addr        DCD     FIQ_Handler
  621. Undef_Handler   B       Undef_Handler
  622. SWI_Handler     B       SWI_Handler
  623. PAbt_Handler    B       PAbt_Handler
  624. DAbt_Handler    B       DAbt_Handler
  625. IRQ_Handler     B       IRQ_Handler
  626. FIQ_Handler     B       FIQ_Handler
  629. ; Reset Handler
  631.                 EXPORT  Reset_Handler
  632. Reset_Handler   
  636. ; Clock Setup ------------------------------------------------------------------
  638.                 IF      (:LNOT:(:DEF:NO_CLOCK_SETUP)):LAND:(CLOCK_SETUP != 0)
  639.                 LDR     R0, =SCB_BASE
  640.                 MOV     R1, #0xAA
  641.                 MOV     R2, #0x55
  643. ;  Configure and Enable PLL
  644.                 LDR     R3, =SCS_Val          ; Enable main oscillator
  645.                 STR     R3, [R0, #SCS_OFS] 
  647.                 IF      (SCS_Val:AND:OSCEN) != 0  
  648. OSC_Loop        LDR     R3, [R0, #SCS_OFS]    ; Wait for main osc stabilize
  649.                 ANDS    R3, R3, #OSCSTAT
  650.                 BEQ     OSC_Loop
  651.                 ENDIF
  653.                 LDR     R3, =CLKSRCSEL_Val    ; Select PLL source clock
  654.                 STR     R3, [R0, #CLKSRCSEL_OFS] 
  655.                 LDR     R3, =PLLCFG_Val
  656.                 STR     R3, [R0, #PLLCFG_OFS] 
  657.                 STR     R1, [R0, #PLLFEED_OFS]
  658.                 STR     R2, [R0, #PLLFEED_OFS]
  659.                 MOV     R3, #PLLCON_PLLE
  660.                 STR     R3, [R0, #PLLCON_OFS]
  661.                 STR     R1, [R0, #PLLFEED_OFS]
  662.                 STR     R2, [R0, #PLLFEED_OFS]
  664. ;  Wait until PLL Locked
  665. PLL_Loop        LDR     R3, [R0, #PLLSTAT_OFS]
  666.                 ANDS    R3, R3, #PLLSTAT_PLOCK
  667.                 BEQ     PLL_Loop
  669. M_N_Lock        LDR     R3, [R0, #PLLSTAT_OFS]
  670.                 LDR     R4, =(PLLSTAT_M:OR:PLLSTAT_N)
  671.                 AND     R3, R3, R4
  672.                 LDR     R4, =PLLCFG_Val
  673.                 EORS    R3, R3, R4
  674.                 BNE     M_N_Lock
  676. ;  Setup CPU clock divider
  677.                 MOV     R3, #CCLKCFG_Val
  678.                 STR     R3, [R0, #CCLKCFG_OFS]
  680. ;  Setup USB clock divider
  681.                 LDR     R3, =USBCLKCFG_Val
  682.                 STR     R3, [R0, #USBCLKCFG_OFS]
  684. ;  Setup Peripheral Clock
  685.                 LDR     R3, =PCLKSEL0_Val
  686.                 STR     R3, [R0, #PCLKSEL0_OFS]
  687.                 LDR     R3, =PCLKSEL1_Val
  688.                 STR     R3, [R0, #PCLKSEL1_OFS]
  690. ;  Switch to PLL Clock
  691.                 MOV     R3, #(PLLCON_PLLE:OR:PLLCON_PLLC)
  692.                 STR     R3, [R0, #PLLCON_OFS]
  693.                 STR     R1, [R0, #PLLFEED_OFS]
  694.                 STR     R2, [R0, #PLLFEED_OFS]
  696.                 LDR     R4, =PCONP_Val        ; Enable Peripheral Clocks
  697.                 STR     R4, [R0, #PCONP_OFS]
  698.                 ENDIF   ; CLOCK_SETUP
  701. ; Setup Memory Accelerator Module ----------------------------------------------
  703.                 IF      MAM_SETUP != 0
  704.                 LDR     R0, =MAM_BASE
  705.                 MOV     R1, #MAMTIM_Val
  706.                 STR     R1, [R0, #MAMTIM_OFS] 
  707.                 MOV     R1, #MAMCR_Val
  708.                 STR     R1, [R0, #MAMCR_OFS] 
  709.                 ENDIF   ; MAM_SETUP
  712. ; Setup External Memory Controller ---------------------------------------------
  714.                 IF      (:DEF:NO_EMC_SETUP):LOR:(EMC_SETUP != 0)
  715.                 LDR     R0, =EMC_BASE
  716.                 LDR     R1, =SCB_BASE
  717.                 LDR     R2, =PCB_BASE
  719.                 LDR     R4, [R1, #PCONP_OFS]
  720.                 ORR     R4, R4, #EMC_PCONP_Const  ; Enable EMC clock
  721.                 STR     R4, [R1, #PCONP_OFS]
  723.                 LDR     R4, =EMC_CTRL_Val
  724.                 STR     R4, [R0, #EMC_CTRL_OFS]
  725.                 LDR     R4, =EMC_CONFIG_Val
  726.                 STR     R4, [R0, #EMC_CONFIG_OFS]
  728. ;  Setup pin functions for External Bus functionality
  729.                 LDR     R4, =EMC_PINSEL6_Val
  730.                 STR     R4, [R2, #PINSEL6_OFS]
  731.                 LDR     R4, =EMC_PINSEL8_Val
  732.                 STR     R4, [R2, #PINSEL8_OFS]
  733.                 LDR     R4, =EMC_PINSEL9_Val
  734.                 STR     R4, [R2, #PINSEL9_OFS]
  736.                 LDR     R6, =1200000              ; Number of cycles to delay
  737. Wait_0          SUBS    R6, R6, #1                ; Delay ~100 ms @ proc clk 48 MHz
  738.                 BNE     Wait_0
  740.                 IF      (EMC_STACS0_SETUP != 0)
  741.                 LDR     R4, =EMC_STA_CFG0_Val
  742.                 STR     R4, [R0, #EMC_STA_CFG0_OFS]
  743.                 LDR     R4, =EMC_STA_WWEN0_Val
  744.                 STR     R4, [R0, #EMC_STA_WWEN0_OFS]
  745.                 LDR     R4, =EMC_STA_WOEN0_Val
  746.                 STR     R4, [R0, #EMC_STA_WOEN0_OFS]
  747.                 LDR     R4, =EMC_STA_WRD0_Val
  748.                 STR     R4, [R0, #EMC_STA_WRD0_OFS]
  749.                 LDR     R4, =EMC_STA_WPAGE0_Val
  750.                 STR     R4, [R0, #EMC_STA_WPAGE0_OFS]
  751.                 LDR     R4, =EMC_STA_WWR0_Val
  752.                 STR     R4, [R0, #EMC_STA_WWR0_OFS]
  753.                 LDR     R4, =EMC_STA_WTURN0_Val
  754.                 STR     R4, [R0, #EMC_STA_WTURN0_OFS]
  755.                 ENDIF
  757.                 IF      (EMC_STACS1_SETUP != 0)
  758.                 LDR     R4, =EMC_STA_CFG1_Val
  759.                 STR     R4, [R0, #EMC_STA_CFG1_OFS]
  760.                 LDR     R4, =EMC_STA_WWEN1_Val
  761.                 STR     R4, [R0, #EMC_STA_WWEN1_OFS]
  762.                 LDR     R4, =EMC_STA_WOEN1_Val
  763.                 STR     R4, [R0, #EMC_STA_WOEN1_OFS]
  764.                 LDR     R4, =EMC_STA_WRD1_Val
  765.                 STR     R4, [R0, #EMC_STA_WRD1_OFS]
  766.                 LDR     R4, =EMC_STA_WPAGE1_Val
  767.                 STR     R4, [R0, #EMC_STA_WPAGE1_OFS]
  768.                 LDR     R4, =EMC_STA_WWR1_Val
  769.                 STR     R4, [R0, #EMC_STA_WWR1_OFS]
  770.                 LDR     R4, =EMC_STA_WTURN1_Val
  771.                 STR     R4, [R0, #EMC_STA_WTURN1_OFS]
  772.                 ENDIF
  774.                 LDR     R6, =120000               ; Number of cycles to delay
  775. Wait_1          SUBS    R6, R6, #1                ; Delay ~10 ms @ proc clk 48 MHz
  776.                 BNE     Wait_1
  778.                 LDR     R4, =EMC_STA_EXT_W_Val
  779.                 LDR     R5, =EMC_STA_EXT_W_OFS
  780.                 ADD     R5, R5, R0
  781.                 STR     R4, [R5, #0]
  783.                 ENDIF   ; EMC_SETUP
  786. ; Copy Exception Vectors to Internal RAM ---------------------------------------
  788.                 IF      :DEF:RAM_INTVEC
  789.                 ADR     R8, Vectors         ; Source
  790.                 LDR     R9, =RAM_BASE       ; Destination
  791.                 LDMIA   R8!, {R0-R7}        ; Load Vectors 
  792.                 STMIA   R9!, {R0-R7}        ; Store Vectors 
  793.                 LDMIA   R8!, {R0-R7}        ; Load Handler Addresses 
  794.                 STMIA   R9!, {R0-R7}        ; Store Handler Addresses
  795.                 ENDIF
  798. ; Memory Mapping (when Interrupt Vectors are in RAM) ---------------------------
  800. MEMMAP          EQU     0xE01FC040          ; Memory Mapping Control
  801.                 IF      :DEF:REMAP
  802.                 LDR     R0, =MEMMAP
  803.                 IF      :DEF:EXTMEM_MODE
  804.                 MOV     R1, #3
  805.                 ELIF    :DEF:RAM_MODE
  806.                 MOV     R1, #2
  807.                 ELSE
  808.                 MOV     R1, #1
  809.                 ENDIF
  810.                 STR     R1, [R0]
  811.                 ENDIF
  814. ; Setup Stack for each mode ----------------------------------------------------
  816.                 LDR     R0, =Stack_Top
  818. ;  Enter Undefined Instruction Mode and set its Stack Pointer
  819.                 MSR     CPSR_c, #Mode_UND:OR:I_Bit:OR:F_Bit
  820.                 MOV     SP, R0
  821.                 SUB     R0, R0, #UND_Stack_Size
  823. ;  Enter Abort Mode and set its Stack Pointer
  824.                 MSR     CPSR_c, #Mode_ABT:OR:I_Bit:OR:F_Bit
  825.                 MOV     SP, R0
  826.                 SUB     R0, R0, #ABT_Stack_Size
  828. ;  Enter FIQ Mode and set its Stack Pointer
  829.                 MSR     CPSR_c, #Mode_FIQ:OR:I_Bit:OR:F_Bit
  830.                 MOV     SP, R0
  831.                 SUB     R0, R0, #FIQ_Stack_Size
  833. ;  Enter IRQ Mode and set its Stack Pointer
  834.                 MSR     CPSR_c, #Mode_IRQ:OR:I_Bit:OR:F_Bit
  835.                 MOV     SP, R0
  836.                 SUB     R0, R0, #IRQ_Stack_Size
  838. ;  Enter Supervisor Mode and set its Stack Pointer
  839.                 MSR     CPSR_c, #Mode_SVC:OR:I_Bit:OR:F_Bit
  840.                 MOV     SP, R0
  841.                 SUB     R0, R0, #SVC_Stack_Size
  843. ;  Enter User Mode and set its Stack Pointer
  844.                 MSR     CPSR_c, #Mode_USR
  845.                 IF      :DEF:__MICROLIB
  847.                 EXPORT __initial_sp
  849.                 ELSE
  851.                 MOV     SP, R0
  852.                 SUB     SL, SP, #USR_Stack_Size
  854.                 ENDIF
  857. ; Enter the C code -------------------------------------------------------------
  859.                 IMPORT  __main
  860.                 LDR     R0, =__main
  861.                 BX      R0
  864.                 IF      :DEF:__MICROLIB
  866.                 EXPORT  __heap_base
  867.                 EXPORT  __heap_limit
  869.                 ELSE
  870. ; User Initial Stack & Heap
  871.                 AREA    |.text|, CODE, READONLY
  873.                 IMPORT  __use_two_region_memory
  874.                 EXPORT  __user_initial_stackheap
  875. __user_initial_stackheap
  877.                 LDR     R0, =  Heap_Mem
  878.                 LDR     R1, =(Stack_Mem + USR_Stack_Size)
  879.                 LDR     R2, = (Heap_Mem +      Heap_Size)
  880.                 LDR     R3, = Stack_Mem
  881.                 BX      LR
  882.                 ENDIF
  885.                 END