idt32438End.h
资源名称:idt438.rar [点击查看]
上传用户:yingyi0918
上传日期:2022-06-26
资源大小:214k
文件大小:32k
源码类别:
VxWorks
开发平台:
C/C++
- /* idt32438End.h - Ethernet END Driver header for IDT RC32438*/
- /* Copyright 1984-2002 Wind River Systems, Inc. */
- #include "copyright_wrs.h"
- /*
- * This file has been developed or significantly modified by the
- * MIPS Center of Excellence Dedicated Engineering Staff.
- * This notice is as per the MIPS Center of Excellence Master Partner
- * Agreement, do not remove this notice without checking first with
- * WR/Platforms MIPS Center of Excellence engineering management.
- */
- /*
- modification history
- --------------------
- 01b,25jul02,slk SPR 80131 and also general code clean up
- 01b,11jul02,pgh Significant re-write and clean up.
- 01a,19Jun02,d_c Code from IDT modified to approach C of E standards.
- */
- /*
- DESCRIPTION
- This file is contains definitions for the Ethernet enhanced network driver
- for the IDT RC32438.
- */
- #ifndef __INCidt32438Endh
- #define __INCidt32438Endh
- #ifdef __cplusplus
- extern "C" {
- #endif
- /* ethernet frame and MAC size */
- #define EH_SIZE 14
- #define ETH_CRC_LEN 4
- #define ETH_MAX_FRAME_SIZE (ETHERMTU + EH_SIZE + ETH_CRC_LEN)
- #define ENET_SIZE 6 /* Ethernet address size */
- #define IDT438_DEV_NAME "IDT" /* name of the device */
- #define IDT438_DEV_NAME_LEN 4 /* length of the name string */
- #define IDT_UNIT0 0 /* device unit number */
- #define IDT_UNIT1 1
- #ifndef N_MCAST
- #define N_MCAST 64 /* max multicast addresses for this driver */
- #endif
- #define IDT_BUFSIZ 2048 /* cluster buffer size */
- /* General Macros */
- #define MAX(A,B) (((A) > (B)) ? (A) : (B))
- #define MIN(A,B) (((A) < (B)) ? (A) : (B))
- /* BASE ETHERNET ADDRESS */
- #define ETH0_BASE_ADDR 0xB8058000
- #define ETH1_BASE_ADDR 0xB8060000
- #define DMA0_BASE_ADDR 0xB8040028
- #define DMA1_BASE_ADDR 0xB8040050
- /* long read and write MACROs handling volatile registers */
- #ifndef IDT_LONG_WR
- #define IDT_LONG_WR(addr, value)
- {
- *((volatile UINT32 *)(addr)) = (UINT32)(value);
- }
- #endif/* IDT_LONG_WR */
- #ifndef IDT_LONG_RD
- #define IDT_LONG_RD(addr) *((volatile UINT32 *)(addr))
- #endif/* IDT_LONG_RD */
- /* RC32438 Register Base Offsets from Reg Base Addr */
- #define IDT_INTC_REG_OFFSET 0x00038000
- #define IDT_DMA0_REG_OFFSET 0x00040028
- #define IDT_ETH0_REG_OFFSET 0x00058000
- #define IDT_DMA1_REG_OFFSET 0x00040050
- #define IDT_ETH1_REG_OFFSET 0x00060000
- /* DMA, Interrupt Controller and Ethernet register access macros */
- #define IDT_DMA_REGS(pDrvCtrl,reg)
- ((volatile UINT32 *)((UINT32)(pDrvCtrl->dmaRegBase)+(reg)))
- #define IDT_INT_REGS(pDrvCtrl,reg)
- ((volatile UINT32 *)((UINT32)(pDrvCtrl->intRegBase)+(reg)))
- #define IDT_ETH_REGS(pDrvCtrl,reg)
- ((volatile UINT32 *)((UINT32)(pDrvCtrl->ethRegBase)+(reg)))
- /* Ethernet Interrupt Registers
- * Notes: During the vxWorks bringup all the IMASK
- * registers should be written with all F's. Once
- * this is done, any subsequent interrupt enable
- * operation would do corresponding mask bit reset.
- * This would ensure non-occurrence of any spurious
- * interrupt.
- */
- #define DMA_CHAN2_INT 0x00000004
- #define DMA_CHAN3_INT 0x00000008
- #define DMA_CHAN4_INT 0x00000010
- #define DMA_CHAN5_INT 0x00000020
- /* DMA Rx and Tx Interrupt Numbers */
- #define DMA_ETHERNET0_RX_INT_NUM 2
- #define DMA_ETHERNET0_TX_INT_NUM 3
- #define DMA_ETHERNET1_RX_INT_NUM 4
- #define DMA_ETHERNET1_TX_INT_NUM 5
- /* Interrupt Controller IMASK3 register used to enable and disable
- * interrupts for DMA channels 9 and 10 (ethernet tx and rx)
- */
- #define IDT_IMASK3_CONTROL(pDrvCtrl) IDT_INT_REGS(pDrvCtrl,0x14)
- /* Interrupt Controller Mask 3, Enable and Disable Ethernet Tx and Rx */
- #define DMA_INT_ENABLE(pDrvCtrl)
- {
- volatile UINT32 temp ;
- temp = INTERRUPT.i3.imask;
- if(pDrvCtrl->unit == 0)
- temp = (temp & (~(DMA_CHAN2_INT | DMA_CHAN3_INT)));
- else
- temp = (temp & (~(DMA_CHAN4_INT | DMA_CHAN5_INT )));
- INTERRUPT.i3.imask = temp ;
- temp = INTERRUPT.i3.imask ;
- }
- #define DMA_INT_DISABLE(pDrvCtrl)
- {
- volatile UINT32 temp ;
- temp = INTERRUPT.i3.imask;
- if(pDrvCtrl->unit == 0)
- temp = (temp | ((DMA_CHAN2_INT | DMA_CHAN3_INT )));
- else
- temp = (temp | ((DMA_CHAN4_INT | DMA_CHAN5_INT )));
- INTERRUPT.i3.imask = temp ;
- temp = INTERRUPT.i3.imask ;
- }
- /* Interrupt Controller IMask5 Register. Controls enable/disable
- * of ethernet input overflow and output underflow interrupts.
- */
- #define IDT_IMASK5_CONTROL(pDrvCtrl) IDT_INT_REGS(pDrvCtrl,0x2c)
- /* output underflow and input overflow interrupt IMASK5 bits */
- #define ETH0FIFOS_INPUT_OVERFLOW 0x00001000
- #define ETH0FIFOS_OUTPUT_UNDERFLOW 0x00002000
- #define ETH1FIFOS_INPUT_OVERFLOW 0x00008000
- #define ETH1FIFOS_OUTPUT_UNDERFLOW 0x00010000
- /* Ethernet Receive DMA defines : DMA Channel 9
- * Notes: The DMA_RX_CONTROL should be written with
- * a value of 0x0000 0009 at the initialization, which
- * selects the transfer request mode, resets the DONE
- * MASK, and has no effect on the RUN bit.The DMA Status
- * Status Mask register need to be zeroed during
- * initialization. Subsequently, set the DMA Status Mask
- * to receive all the interrupts ( To help Debug ) though
- * only DONE would be important in Receive and FINISH in
- * the case of Transmit. Also, during initialization,
- * write all zero's to DPTR and NDPTR.
- */
- #define DMA_RX_CONTROL(pDrvCtrl) IDT_DMA_REGS(pDrvCtrl,0x00)
- /* DMA 2/4 control register */
- #define DMA_RX_CNT_MODE 0x00000008
- #define DMA_RX_CNT_RUN 0x00000001
- #define DMA_RX_CNT_VAL 0x00000009
- #define DMA_RX_CONTROL_RD(pDrvCtrl)
- (*((volatile UINT32 *)DMA_RX_CONTROL(pDrvCtrl)))
- #define DMA_RX_CONTROL_WR(pDrvCtrl,val)
- (*((volatile UINT32 *)DMA_RX_CONTROL(pDrvCtrl)) = (val | 0x8))
- #define DMA_TXRX_RUN 0x1
- #define DMA_RX_STATUS(pDrvCtrl)
- IDT_DMA_REGS(pDrvCtrl,0x04) /* DMA2/4 status register */
- #define DMA_RX_FINISHED 0x00000001
- #define DMA_RX_DONE 0x00000002
- #define DMA_RX_CHAIN 0x00000004
- #define DMA_RX_ERROR 0x00000008
- #define DMA_RX_HALT 0x00000010
- #define DMA_RX_STATUS_RD(pDrvCtrl)
- (*((volatile UINT32 *)DMA_RX_STATUS(pDrvCtrl)))
- #define DMA_RX_STATUS_WR(pDrvCtrl,val)
- (*((volatile UINT32 *)DMA_RX_STATUS(pDrvCtrl)) = (val))
- #define DMA_RX_STATUS_MASK(pDrvCtrl)
- IDT_DMA_REGS(pDrvCtrl,0x08) /* DMA 2/4 status mask register */
- #define DMA_RX_SMASK_VAL
- (DMA_RX_ERROR | DMA_RX_FINISHED | DMA_RX_DONE | DMA_RX_HALT)
- #define ETH_DMA_RX_INT_ENABLE(pDrvCtrl)
- {
- volatile UINT32 temp ;
- temp = (UINT32)(~( DMA_RX_SMASK_VAL) );
- *((volatile UINT32 *)DMA_RX_STATUS_MASK(pDrvCtrl))&=temp;
- temp= *((volatile UINT32 *)DMA_RX_STATUS_MASK(pDrvCtrl)) ;
- }
- #define ETH_DMA_RX_INT_DISABLE(pDrvCtrl)
- {
- volatile UINT32 temp ;
- temp = (UINT32)(DMA_RX_SMASK_VAL);
- *((volatile UINT32 *)DMA_RX_STATUS_MASK(pDrvCtrl))|=temp;
- temp=*((volatile UINT32 *)DMA_RX_STATUS_MASK(pDrvCtrl)) ;
- }
- #define DMA_RX_DPTR(pDrvCtrl)
- IDT_DMA_REGS(pDrvCtrl,0x0c) /* DMA 2/4 descriptor ptr reg */
- #define DMA_RX_NDPTR(pDrvCtrl)
- IDT_DMA_REGS(pDrvCtrl,0x10) /* DMA 2/4 next descriptor ptr reg */
- #ifndef DMA_RX_DPTR_WR
- #define DMA_RX_DPTR_WR(pDrvCtrl,val)
- {
- *((volatile UINT32 *)DMA_RX_DPTR(pDrvCtrl)) = K1_TO_PHYS((UINT32)(val));
- }
- #endif
- #ifndef DMA_RX_DPTR_RD
- #define DMA_RX_DPTR_RD(pDrvCtrl)
- (PHYS_TO_K1(*((volatile UINT32 *)DMA_RX_DPTR(pDrvCtrl))))
- #endif /* DMA_RX_DPTR_RD */
- #ifndef DMA_RX_NDPTR_RD
- #define DMA_RX_NDPTR_RD(pDrvCtrl)
- (PHYS_TO_K1(*((volatile UINT32 *)DMA_RX_NDPTR(pDrvCtrl))))
- #endif /* DMA_RX_NDPTR_RD */
- #ifndef DMA_RX_NDPTR_WR
- #define DMA_RX_NDPTR_WR(pDrvCtrl,val)
- {
- *((volatile UINT32 *)DMA_RX_NDPTR(pDrvCtrl)) = K1_TO_PHYS((UINT32)(val));
- }
- #endif /* DMA_RX_NDPTR_WR */
- /* Ethernet Transmit DMA defines : DMA Channel 10 */
- #define DMA_TX_CONTROL(pDrvCtrl)
- IDT_DMA_REGS(pDrvCtrl,0x14) /* DMA 3/5 control register */
- #define DMA_TX_CNT_MODE 0x00000008
- #define DMA_TX_CNT_RUN 0x00000001
- #define DMA_TX_CNT_VAL 0x00000009
- #define DMA_TX_CONTROL_RD(pDrvCtrl)
- (*((volatile UINT32 *)DMA_TX_CONTROL(pDrvCtrl)))
- #define DMA_TX_CONTROL_WR(pDrvCtrl,val)
- (*((volatile UINT32 *)DMA_TX_CONTROL(pDrvCtrl)) = (val| 0x8))
- #define DMA_TX_STATUS(pDrvCtrl)
- IDT_DMA_REGS(pDrvCtrl,0x18) /* DMA 3/5 status register */
- #define DMA_TX_FINISHED 0x00000001
- #define DMA_TX_DONE 0x00000002
- #define DMA_TX_CHAIN 0x00000004
- #define DMA_TX_ERROR 0x00000008
- #define DMA_TX_HALT 0x00000010
- #define DMA_TX_STATUS_RD(pDrvCtrl)
- (*((volatile UINT32 *)DMA_TX_STATUS(pDrvCtrl)))
- #define DMA_TX_STATUS_WR(pDrvCtrl,val)
- (*((volatile UINT32 *)DMA_TX_STATUS(pDrvCtrl)) = (val))
- #define DMA_TX_STATUS_MASK(pDrvCtrl)
- IDT_DMA_REGS(pDrvCtrl,0x1c)/* DMA 3/5 status mask register */
- #define DMA_TX_SMASK_VAL
- (DMA_TX_ERROR | DMA_TX_FINISHED | DMA_TX_DONE | DMA_TX_HALT)
- #define DMA_TX_SMASK_RD(pDrvCtrl)
- (*((volatile UINT32 *)DMA_TX_STATUS_MASK(pDrvCtrl)))
- #define DMA_TX_SMASK_WR(pDrvCtrl,val)
- (*((volatile UINT32 *)DMA_TX_STATUS_MASK(pDrvCtrl)) = (val))
- /* enable and disable ethernet DMA TX interrupts */
- #define ETH_DMA_TX_INT_ENABLE(pDrvCtrl)
- {
- volatile UINT32 temp ;
- temp = (UINT32)(~( DMA_TX_SMASK_VAL) );
- *((volatile UINT32 *)DMA_TX_STATUS_MASK(pDrvCtrl))&=temp;
- temp= *((volatile UINT32 *)DMA_TX_STATUS_MASK(pDrvCtrl)) ;
- }
- #define ETH_DMA_TX_INT_DISABLE(pDrvCtrl)
- {
- volatile UINT32 temp ;
- temp = (UINT32)(DMA_TX_SMASK_VAL);
- *((volatile UINT32 *)DMA_TX_STATUS_MASK(pDrvCtrl))|=temp;
- temp=*((volatile UINT32 *)DMA_TX_STATUS_MASK(pDrvCtrl)) ;
- }
- #define DMA_TX_DPTR(pDrvCtrl)
- IDT_DMA_REGS(pDrvCtrl,0x20) /* DMA 3/5 descriptor pointer reg */
- #ifndef DMA_TX_DPTR_RD
- #define DMA_TX_DPTR_RD(pDrvCtrl)
- (PHYS_TO_K1(*((volatile UINT32 *)DMA_TX_DPTR(pDrvCtrl))))
- #endif /* DMA_TX_DPTR_RD */
- /* DMA_TX_DPTR_WR starts the send of of TDR packet */
- #ifndef DMA_TX_DPTR_WR
- #define DMA_TX_DPTR_WR(pDrvCtrl,val)
- {
- *((volatile UINT32 *)DMA_TX_DPTR(pDrvCtrl)) = K1_TO_PHYS((UINT32)(val));
- }
- #endif /* DMA_TX_DPTR_WR */
- #define DMA_TX_NDPTR(pDrvCtrl) IDT_DMA_REGS(pDrvCtrl,0x24)
- /* DMA 3/5 next descriptor ptr reg */
- #ifndef DMA_TX_NDPTR_RD
- #define DMA_TX_NDPTR_RD(pDrvCtrl)
- (PHYS_TO_K1(*((volatile UINT32 *)DMA_TX_NDPTR(pDrvCtrl))))
- #endif /* DMA_TX_NDPTR_RD */
- #ifndef DMA_TX_NDPTR_WR
- #define DMA_TX_NDPTR_WR(pDrvCtrl,val)
- {
- *((volatile UINT32 *)DMA_TX_NDPTR(pDrvCtrl)) = K1_TO_PHYS((UINT32)(val));
- }
- #endif /* DMA_TX_NDPTR_WR */
- /* Ethernet Interface Control Register */
- #define IDT_ETHINTFC_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x00)
- #define IDT_ETHINTFC_EN 0x00000001
- #define IDT_ETHINTFC_DIS 0x00000000
- #define IDT_ETHINTFC_RIP 0x00000004
- /* Ethernet Multicast Hash Registers */
- #define IDT_ETHHASH0_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0c)
- #define IDT_ETHHASH1_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x10)
- /* Ethernet MAC Address Registers */
- #define IDT_ETHSAL0_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0100)
- #define IDT_ETHSAH0_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0104)
- #define IDT_ETHSAL1_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0108)
- #define IDT_ETHSAH1_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x010c)
- #define IDT_ETHSAL2_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0110)
- #define IDT_ETHSAH2_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0114)
- #define IDT_ETHSAL3_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0118)
- #define IDT_ETHSAH3_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x011c)
- #define IDT_ETHSAL_WRITE(pDrvCtrl,value)
- {
- *((volatile UINT32 *)IDT_ETHSAL0_REG(pDrvCtrl)) = (value);
- *((volatile UINT32 *)IDT_ETHSAL1_REG(pDrvCtrl)) = (value);
- *((volatile UINT32 *)IDT_ETHSAL2_REG(pDrvCtrl)) = (value);
- *((volatile UINT32 *)IDT_ETHSAL3_REG(pDrvCtrl)) = (value);
- }
- #define IDT_ETHSAH_WRITE(pDrvCtrl,value)
- {
- *((volatile UINT32 *)IDT_ETHSAH0_REG(pDrvCtrl)) = (value);
- *((volatile UINT32 *)IDT_ETHSAH1_REG(pDrvCtrl)) = (value);
- *((volatile UINT32 *)IDT_ETHSAH2_REG(pDrvCtrl)) = (value);
- *((volatile UINT32 *)IDT_ETHSAH3_REG(pDrvCtrl)) = (value);
- }
- #define ETH_DMA_OVRRUN(pDrvCtrl)
- if( ETH0.eth0intfc & ETHERINTFC_OVR )
- {
- ETH0.eth0intfc = ( ETH0.eth0intfc & (~(UINT32)(ETHERINTFC_OVR)) );
- }
- else if( ETH1.eth1intfc & ETHERINTFC_OVR )
- {
- ETH1.eth1intfc = ( ETH1.eth1intfc & (~(UINT32)(ETHERINTFC_OVR)) );
- }
- /* Ethernet Address recognition control register */
- #define IDT_ETHARC_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x08)
- #define IDT_ETHARC_PRO 0x00000001
- #define IDT_ETHARC_AM 0x00000002
- #define IDT_ETHARC_AFM 0x00000004
- #define IDT_ETHARC_AB 0x00000008
- #define IDT_SET_PROMISC(pDrvCtrl)
- {
- *((volatile UINT32 *)IDT_ETHARC_REG(pDrvCtrl)) |= IDT_ETHARC_PRO;
- }
- #define IDT_CLR_PROMISC(pDrvCtrl)
- {
- *((volatile UINT32 *)IDT_ETHARC_REG(pDrvCtrl)) &= ~IDT_ETHARC_PRO;
- }
- #define IDT_SET_MCAST(pDrvCtrl)
- {
- *((volatile UINT32 *)IDT_ETHARC_REG(pDrvCtrl)) |= IDT_ETHARC_AM;
- }
- #define IDT_SET_MCASTALL(pDrvCtrl)
- {
- *((volatile UINT32 *)IDT_ETHARC_REG(pDrvCtrl)) |= IDT_ETHARC_AFM;
- }
- #define IDT_ETHFIFOTT_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x04)
- #define IDT_ETHFIFOTT_VAL 0x40 /* Assuming COLWIN to be 0x37 */
- /* Ethernet MAC Controller Registers and bit definitions */
- #define IDT_ETHMAC1_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0200)
- #define IDT_ETHMAC1_RE 0x1
- #define IDT_ETHMAC1_PAF 0x2
- #define IDT_ETHMAC1_RFC 0x4
- #define IDT_ETHMAC1_TFC 0x8
- #define IDT_ETHMAC1_LB 0x10
- #define IDT_ETHMAC1_MR 0x8000
- #define IDT_ETHMAC2_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0204)
- #define IDT_ETHMAC2_FD 0x1
- #define IDT_ETHMAC2_FLC 0x2
- #define IDT_ETHMAC2_HFE 0x4
- #define IDT_ETHMAC2_DC 0x8
- #define IDT_ETHMAC2_CEN 0x10
- #define IDT_ETHMAC2_PE 0x20
- #define IDT_ETHMAC2_VPE 0x40
- #define IDT_ETHMAC2_APE 0x80
- #define IDT_ETHMAC2_PPE 0x100
- #define IDT_ETHMAC2_LPE 0x200
- #define IDT_ETHMAC2_NB 0x1000
- #define IDT_ETHMAC2_BP 0x2000
- #define IDT_ETHMAC2_ED 0x4000
- #define IDT_ETHIPGT_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0208)
- #define IDT_ETHIPGT_HDX 0x12
- #define IDT_ETHIPGT_FDX 0x15
- #define IDT_ETHIPGR_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x020c)
- #define IDT_ETHIPGR_HDX 0x1212
- #define IDT_ETHIPGR_FDX 0x1515
- #define IDT_ETHCLRT_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0210)
- #define IDT_ETHCLRT_VAL 0x370F
- #define IDT_ETHMAXF_REG(pDrvCtrl) IDT_ETH_REGS(pDrvCtrl,0x0214)
- #define IDT_ETHMAXF_VAL 0x0600
- /* MII Management Interface Registers and bit values */
- #define IDT_ETH_REG_BASE 0xB8058000
- #define IDT_MIIMCFG_REG IDT_ETH_REG_BASE + 0x0220
- #define IDT_MIIMCMD_REG IDT_ETH_REG_BASE + 0x0224
- #define IDT_MIIMADDR_REG IDT_ETH_REG_BASE + 0x0228
- #define IDT_MIIMWTD_REG IDT_ETH_REG_BASE + 0x022c
- #define IDT_MIIMRDD_REG IDT_ETH_REG_BASE + 0x0230
- #define IDT_MIIMIND_REG IDT_ETH_REG_BASE + 0x0234
- #define IDT_ETHMCP_REG IDT_ETH_REG_BASE + 0x0028
- #define IDT_ETHMCP_VAL 0
- #define MIICFG_RESET_VAL 0x00008000
- #define MIICMD_SET_SCAN()
- {
- *((volatile UINT32 *)IDT_MIIMCMD_REG) = MIIMCMD_SCN;
- }
- #define MIICMD_RESET_SCAN()
- {
- *((volatile UINT32 *)IDT_MIIMCMD_REG) &= ~MIIMCMD_SCN;
- }
- #define MIIM_RESET()
- {
- *((volatile UINT32 *)IDT_MIIMCMD_REG) = MIICFG_RESET_VAL;
- }
- /* PHY Device used on the board : LXT972
- * Register Definitions
- */
- #define PHY_ADDR_0 0x0
- #define PHY_ADDR_1 0x1
- #define PHY_10MBS 0
- #define PHY_100MBS 1
- #define PHY_AUTO_SPEED 2
- #define PHY_HALF_DPX 0
- #define PHY_FULL_DPX 1
- #define PHY_AUTO_DPX 2
- #define PHY_CONTROL_REG 0x0
- #define PHY_RESET_VAL 0x8000
- #define PHY_LOOP_EN 0x4000
- #define PHY_SPEED_SEL 0x2000
- #define PHY_AUTONEG_EN 0x1000
- #define PHY_PWR_DOWN 0x0800
- #define PHY_ISOLATE 0x0400
- #define PHY_RESTART_AN 0x0200
- #define PHY_DPLX_MODE 0x0100
- #define PHY_COL_TEST 0x0080
- #define PHY_SPD_SELECT 0x0040
- #define PHY_NEGOTIATE (PHY_AUTONEG_EN | PHY_RESTART_AN)
- #define PHY_STATUS1_REG 0x1
- #define PHY_10BASE_T4 0x8000
- #define PHY_100BASEX_FULL 0x4000
- #define PHY_100BASEX_HALF 0x2000
- #define PHY_10BASE_FULL 0x1000
- #define PHY_10BASE_HALF 0x0800
- #define PHY_10BASET2_HALF 0x0400
- #define PHY_10BASET2_FULL 0x0200
- #define PHY_EXT_STATUS 0x0100
- #define PHY_MF_PREAM_SUPPRESS 0x0040
- #define PHY_AUTONEG_DONE 0x0020
- #define PHY_REMOTE_FAULT 0x0010
- #define PHY_AUTONEG_ABLE 0x0008
- #define PHY_LINK_STATUS 0x0004
- #define PHY_JABBER_DETECT 0x0002
- #define PHY_EXTEND_ABLE 0x0001
- #define PHY_PHY_ID_1_REG 0x2
- #define PHY_PHY_ID_2_REG 0x3
- #define PHY_AUTONEG_ADV_REG 0x4
- #define PHY_MULTIPAGE_ABLE 0x8000
- #define PHY_ASYM_PAUSE 0x0800
- #define PHY_PAUSE_EN 0x0400
- #define PHY_100BASETX_FULL 0x0100
- #define PHY_100BASETX_ABLE 0x0080
- #define PHY_10BASET_FULL 0x0040
- #define PHY_10BASET_ABLE 0x0020
- #define PHY_IEEE802_3_VAL 0x0001
- #define PHY_AUTO_NEG_DEFAULT
- (
- PHY_100BASETX_FULL |
- PHY_100BASETX_ABLE |
- PHY_10BASET_FULL |
- PHY_10BASET_ABLE |
- PHY_IEEE802_3_VAL
- )
- #define PHY_AUTONEG_LNK_ABILITY_REG 0x5
- #define PHY_AUTONEG_EXPANSION_REG 0x6
- #define PHY_BASE_PAGE 0x0020
- #define PHY_PAR_DETECT_FAULT 0x0010
- #define PHY_LNK_PARTNER 0x0008
- #define PHY_NXT_PAG_ABLE 0x0004
- #define PHY_PAGE_RCVD 0x0002
- #define PHY_LNK_PARTNER_ANABLE 0x0001
- #define PHY_AUTONEG_LNK_PAGE_XMT_REG 0x7
- #define PHY_AUTONEG_LNK_NXT_PAGE_REG 0x8
- #define PHY_NEXT_PAGE 0x8000
- #define PHY_MESSAGE_PAGE 0x2000
- #define PHY_ACK2 0x1000
- #define PHY_TOGGLE 0x0800
- #define PHY_PORT_CONFIG_REG 0x10
- #define PHY_FORCE_LNK_PASS 0x4000
- #define PHY_XMT_DISABLE 0x2000
- #define PHY_BYPASS_SCRAMBLER 0x1000
- #define PHY_JABBER 0x0400
- #define PHY_SQE 0x0200
- #define PHY_TP_LOOPBACK 0x0100
- #define PHY_CRS_SELECT 0x0080
- #define PHY_PRE_EN 0x0020
- #define PHY_ALT_NXT_PAGE 0x0002
- #define PHY_STATUS2_REG 0x11
- #define PHY_STAT2_100 0x4000
- #define PHY_STAT2_LINK 0x0400
- #define PHY_STAT2_FULL_DPLX 0x0200
- #define PHY_STAT2_AN_ABLE 0x0100
- #define PHY_STAT2_AN_CMPLT 0x0080
- #define PHY_INTRPT_ENABLE_REG 0x12
- #define PHY_INTRPT_STATUS_REG 0x13
- #define PHY_LED_CONFIG_REG 0x14
- #define PHY_LED_VAL 0x1232
- #define PHY_LED_VAL2 0x1242
- #define PHY_XMT_CONTROL_REG 0x1E
- #define PHY_SPEED_10 10000000
- #define PHY_SPEED_100 100000000
- #undef DRV_DEBUG
- #define DRV_DEBUG
- #ifdef DRV_DEBUG
- /* define the various levels of debugging if the DRV_DEBUG is defined */
- #define DRV_DEBUG_OFF 0x00000000
- #define DRV_DEBUG_RX 0x00000001
- #define DRV_DEBUG_TX 0x00000002
- #define DRV_DEBUG_INT 0x00000004
- #define DRV_DEBUG_POLL_RX 0x00000008
- #define DRV_DEBUG_POLL_TX 0x00000010
- #define DRV_DEBUG_POLL (DRV_DEBUG_POLL_RX | DRV_DEBUG_POLL_TX)
- #define DRV_DEBUG_LOAD 0x00000020
- #define DRV_DEBUG_LOAD2 0x00000040
- #define DRV_DEBUG_IOCTL 0x00000080
- #define DRV_DEBUG_RESET 0x00000100
- #define DRV_DEBUG_MCAST 0x00000200
- #define DRV_DEBUG_CSR 0x00000400
- #define DRV_DEBUG_RX_PKT 0x00000800
- #define DRV_DEBUG_TX_PKT 0x00001000
- #define DRV_DEBUG_MEM 0x00002000
- #define DRV_DEBUG_POLL_REDIR 0x00004000
- #define DRV_DEBUG_LOG_NVRAM 0x00008000
- #define DRV_DEBUG_ENTRY 0x00010000
- #define DRV_DEBUG_INFO 0x00100000
- #define DRV_DEBUG_WARNING 0x00200000
- #define DRV_DEBUG_ERROR 0x00400000
- #define DRV_DEBUG_FATAL 0x00800000
- #define DRV_DEBUG_PANIC 0x01000000
- #define DRV_DEBUG_ALL 0xffffffff
- #define DRV_DEBUG_OVR 0x04000000
- #define DRV_LOG(FLG, X0, X1, X2, X3, X4, X5, X6)
- if (idt32438DebugFlags & FLG)
- (void)logMsg(X0, X1, X2, X3, X4, X5, X6);
- #else /*DRV_DEBUG*/
- #define DRV_LOG(DBG_SW, X0, X1, X2, X3, X4, X5, X6)
- #endif /*DRV_DEBUG*/
- /* minimum number of transmit and receive descriptors */
- #define MIN_NUM_TDRS 0x500 /* Number of TX descriptors */
- #define MIN_NUM_RDRS 0x500 /* Number of RX descriptors */
- /*
- * The Ethernet DMA Descriptor Register data structure.
- * This structure is used for both Transmit DMA Descriptor
- * Registers (TDR), and Receive DMA Descriptor Registers (RDR).
- */
- typedef struct dma_dr
- {
- UINT32 control; /* DMA control and status */
- UINT32 ca; /* DMA buffer current address */
- UINT32 devcs; /* device control and status */
- UINT32 link; /* address of the next DMA descriptor */
- volatile struct dma_dr * next; /* points to next RDR/TDR */
- volatile struct dma_dr * prev; /* points to previous RDR/TDR */
- char * pClust; /* points to cluster buffer */
- M_BLK * pMblk; /* M_BLK to be freed */
- UINT32 flags; /* flags */
- UINT32 pad[7];
- } DMA_DR;
- /* DMA Descriptor Register control field bit definitions */
- #define DMA_DR_CONTROL_F 0x80000000 /* Finished */
- #define DMA_DR_CONTROL_D 0x40000000 /* Done */
- #define DMA_DR_CONTROL_T 0x20000000 /* Terminated */
- #define DMA_DR_CONTROL_IOD 0x10000000 /* Interrupt On Done */
- #define DMA_DR_CONTROL_IOF 0x08000000 /* Interrupt On Finished */
- #define DMA_DR_CONTROL_COF 0x02000000 /* chain on finished */
- #define DMA_DR_CONTROL_COUNT 0x3FFFF /* byte count */
- /* value loaded into receive DMA buffer descriptor control word */
- #define RX_DMA_COUNT 0x600
- #define RDR_CONTROL_VAL
- (DMA_DR_CONTROL_IOD | DMA_DR_CONTROL_IOF | RX_DMA_COUNT )
- /*
- * Ethernet Receive Descriptor Device Control and Status field bit definitions.
- */
- #define RDR_DEVCS_FD 0x00000001 /* first descriptor */
- #define RDR_DEVCS_LD 0x00000002 /* last descriptor */
- #define RDR_DEVCS_ROK 0x00000004 /* receive OK */
- #define RDR_DEVCS_FM 0x00000008 /* filter match */
- #define RDR_DEVCS_MP 0x00000010 /* multicast packet */
- #define RDR_DEVCS_BP 0x00000020 /* broadcast packet */
- #define RDR_DEVCS_VLT 0x00000040 /* VLAN tag detected */
- #define RDR_DEVCS_CF 0x00000080 /* control frame */
- #define RDR_DEVCS_OVR 0x00000100 /* receive FIFO overflow */
- #define RDR_DEVCS_CRC 0x00000200 /* CRC error */
- #define RDR_DEVCS_CV 0x00000400 /* code violation */
- #define RDR_DEVCS_DB 0x00000800 /* dribble bits detected */
- #define RDR_DEVCS_LE 0x00001000 /* length error */
- #define RDR_DEVCS_LOR 0x00002000 /* length out of range */
- #define RDR_DEVCS_CES 0x00004000 /* carrier event seen */
- /*
- * Ethernet Transmit Descriptor Device Control and Status field bit definitions.
- */
- #define TDR_DEVCS_FD 0x00000001 /* first descriptor */
- #define TDR_DEVCS_LD 0x00000002 /* last descriptor */
- #define TDR_DEVCS_OEN 0x00000004 /* override enable */
- #define TDR_DEVCS_PEN 0x00000008 /* packet padding enable */
- #define TDR_DEVCS_CEN 0x00000010 /* packet CRC enable */
- #define TDR_DEVCS_HEN 0x00000020 /* huge packet enable */
- #define TDR_DEVCS_TOK 0x00000040 /* transmit OK */
- #define TDR_DEVCS_MP 0x00000080 /* multicast packet */
- #define TDR_DEVCS_BP 0x00000100 /* broadcast packet */
- #define TDR_DEVCS_UND 0x00000200 /* transmit FIFO underflow */
- #define TDR_DEVCS_OF 0x00000400 /* oversized frame */
- #define TDR_DEVCS_ED 0x00000800 /* excessive deferral */
- #define TDR_DEVCS_EC 0x00001000 /* excessive collisions */
- #define TDR_DEVCS_LC 0x00002000 /* late collision */
- #define TDR_DEVCS_TD 0x00004000 /* transmit deferred */
- #define TDR_DEVCS_CRC 0x00008000 /* CRC error */
- #define TDR_DEVCS_LE 0x00010000 /* length error */
- /* TDR/RDR Flags : Bit Definition */
- #define TDR_IN_USE 0x01
- #define TDR_LAST 0x02
- #define TDR_FIRST 0x04
- /* physical interface specific infomation */
- typedef struct phy_info
- {
- int phyAddr; /* PHY device address: 0-32 */
- int phySpeed; /* PHY speed: PHY_10MBS PHY_100MBS */
- int phyDpx; /* PHY duplex: PHY_HALF_DPX PHY_FULL_DPX */
- char enetAddr[ENET_SIZE]; /* ethernet address */
- } PHY_INFO;
- typedef struct drv_ctrl
- {
- END_OBJ endObj; /* base class */
- END_ERR lastError; /* Last error passed to muxError */
- int unit; /* unit number */
- char * pMemArea; /* cluster block pointer */
- int nTDRs; /* how many TDRs to create */
- char * pTDRmem; /* TX Descriptor Register memory base */
- volatile DMA_DR * pTDRHead; /* next tx descriptor to complete TX */
- volatile DMA_DR * pTDRTail; /* next transmit descriptor to sent */
- volatile DMA_DR * pTDRQStart; /* start of queue of transmit descriptor */
- int cntTDRused; /* count of TDRs in use */
- int nRDRs; /* how many RDRs to create */
- char * pRDRmem; /* RX Descriptor Register memory base */
- volatile DMA_DR * pRDR; /* receive descriptor pointer */
- volatile UINT32 flags; /* driver state */
- BOOL attached; /* interface has been attached */
- BOOL txBlocked; /* TX send blocked. No TDRs available. */
- PHY_INFO board; /* physical interface info */
- CL_POOL_ID pClPoolId; /* cluster pool identifier */
- char * clBaseAddr; /* cluster buffer pool base addr */
- UINT32 dmaRegBase; /* base address of DMA registers */
- UINT32 ethRegBase; /* base address of ethernet registers */
- UINT32 intRegBase; /* base addr of interrupt ctrl registers */
- int ivec; /* input overflow vector number */
- } DRV_CTRL;
- /* DRV_CTRL flags element bit definitions */
- #define IDT_POLLING 0x00000001 /* polling mode */
- #define IDT_PROMISC 0x00000002 /* promiscuous mode */
- #define IDT_MCAST 0x00000004 /* multicast addressing mode */
- #define IDT_MCASTALL 0x00000008 /* all multicast addressing mode */
- #define IDT_RX_NETADD 0x00000010 /* Rx netAdd() requested */
- #define IDT_TX_NETADD 0x00000020 /* Tx netAdd() requested */
- #define IDT_ETHER_RESET 0x00000040 /* Ethernet reset */
- /* Ethernet Transmit Descriptors Read Macros */
- #ifdef INCLUDE_RFC_1213
- #define IDT_HADDR(pEnd) ((pEnd)->mib2Tbl.ifPhysAddress.phyAddress)
- #define IDT_HADDR_LEN(pEnd) ((pEnd)->mib2Tbl.ifPhysAddress.addrLength)
- #else
- #define IDT_HADDR(pEnd)
- ((pEnd)->pMib2Tbl->m2Data.mibIfTbl.ifPhysAddress.phyAddress)
- #define IDT_HADDR_LEN(pEnd)
- ((pEnd)->pMib2Tbl->m2Data.mibIfTbl.ifPhysAddress.addrLength)
- #endif
- /*
- * Buffer Management Macros
- */
- #define NET_BUF_ALLOC()
- netClusterGet (pDrvCtrl->endObj.pNetPool, pDrvCtrl->clPoolId)
- #define NET_BUF_FREE(pBuf)
- netClFree (pDrvCtrl->endObj.pNetPool, pBuf)
- #define NET_MBLK_ALLOC()
- mBlkGet (pDrvCtrl->endObj.pNetPool, M_DONTWAIT, MT_DATA)
- #define NET_MBLK_FREE(pMblk)
- netMblkFree (pDrvCtrl->endObj.pNetPool, (M_BLK_ID)pMblk)
- #define NET_CL_BLK_ALLOC()
- clBlkGet (pDrvCtrl->endObj.pNetPool, M_DONTWAIT)
- #define NET_CL_BLK_FREE(pClblk)
- clBlkFree (pDrvCtrl->endObj.pNetPool, (CL_BLK_ID)pClBlk)
- #define NET_MBLK_BUF_FREE(pMblk)
- netMblkClFree ((M_BLK_ID)pMblk)
- #define NET_MBLK_CHAIN_FREE(pMblk)
- {
- M_BLK *pNext;
- pNext=pMblk;
- while (pNext)
- pNext=NET_MBLK_BUF_FREE (pNext);
- }
- #define NET_MBLK_CL_JOIN(pMblk, pClBlk)
- netMblkClJoin ((pMblk), (pClBlk))
- #define NET_CL_BLK_JOIN(pClBlk, pBuf, len)
- netClBlkJoin ((pClBlk), (pBuf), (len), NULL, 0, 0, 0)
- #ifdef __cplusplus
- }
- #endif
- #endif /* __INCidt32438Endh */