sysALib.s
资源名称:idt438.rar [点击查看]
上传用户:yingyi0918
上传日期:2022-06-26
资源大小:214k
文件大小:10k
源码类别:
VxWorks
开发平台:
C/C++
- /* sysALib.s - IDT79PMC438 system-dependent assembly routines */
- /* Copyright 1984-2002 Wind River Systems, Inc. */
- #include "copyright_wrs.h"
- /*
- * This file has been developed or significantly modified by the
- * MIPS Center of Excellence Dedicated Engineering Staff.
- * This notice is as per the MIPS Center of Excellence Master Partner
- * Agreement, do not remove this notice without checking first with
- * WR/Platforms MIPS Center of Excellence engineering management.
- */
- .data
- .globl copyright_wind_river
- /*
- modification history
- --------------------
- 01a,28may02,krao written
- */
- /*
- DESCRIPTION
- This module contains system-dependent routines written in assembly
- language.
- This module must be the first specified in the command used to
- build the system. The sysInit() routine is the system start-up code.
- */
- /* includes */
- #define _ASMLANGUAGE
- #include "vxWorks.h"
- #include "arch/mips/ivMips.h"
- #include "arch/mips/asmMips.h"
- #include "arch/mips/esfMips.h"
- #include "sysLib.h"
- #include "config.h"
- #include "asm.h"
- #include "esf.h"
- /* defines */
- #define CHAR_DISPLAY_DELAY (CPU_CLOCK_RATE/2)
- #ifndef RC32438_N_TLB_ENTRIES
- #define RC32438_N_TLB_ENTRIES 16
- #define MIPS_N_TLB_ENTRIES RC32438_N_TLB_ENTRIES
- #endif
- #define P_ENTRY_SHIFT 12 /* shift to convert VM page# to virt address */
- #define KSEG1(addr) (((addr) & 0x1fffffff) | K1BASE)
- /* externals */
- .globl usrInit /* system initialization routine */
- /* internals */
- .globl sysWait /* wait for keyboard ready */
- .globl sysInit /* start of system code */
- .globl sysGpInit /* initialize global pointer */
- .globl sysClearTlbEntry /* clear entry in tlb */
- .globl sysWbFlush /* flush write buffers */
- .globl sysFpaAck /* flush write buffers */
- .globl sysCompareSet
- .globl sysCompareGet
- .globl sysCountSet
- .globl sysCountGet
- .globl sysTimerIntClr
- .globl sysConfigGet
- .globl sysConfig1Get
- .globl sysSetPageSize
- .globl sysSetTlbEntry
- .text
- /*******************************************************************************
- *
- * sysInit - start after boot
- *
- * This routine is the system start-up entry point for VxWorks in RAM, the
- * first code executed after booting. It disables interrupts, sets up the
- * stack, and jumps to the C routine usrInit() in usrConfig.c.
- *
- * The initial stack is set to grow down from the address of sysInit(). This
- * stack is used only by usrInit() and is never used again. Memory for the
- * stack must be accounted for when determining the system load address.
- *
- * NOTE: This routine should not be called by the user.
- *
- * RETURNS: N/A
- *
- * sysInit (void) /@ THIS IS NOT A CALLABLE ROUTINE @/
- *
- */
- .set reorder
- .ent sysInit
- sysInit:
- /* disable all interrupts */
- li t0, SR_CU0
- mtc0 t0, C0_SR
- mtc0 zero, C0_CAUSE /* clear software interrupts */
- /* give us as long as possible before a clock interrupt */
- li v0,1
- mtc0 v0,C0_COUNT
- mtc0 zero,C0_COMPARE
- /* set stack to grow down from code, leave room for four parameters */
- la sp, sysInit-(4*_RTypeSize)
- la gp,_gp /* set global ptr from cmplr */
- li a0, BOOT_WARM_AUTOBOOT /* push start type arg = WARM_BOOT */
- jal usrInit /* never returns - starts up kernel */
- nop
- nop
- li ra, R_VEC /* load prom reset address */
- j ra /* just in case */
- .end sysInit
- /*******************************************************************************
- *
- * sysClearTlbEntry - clear translation lookaside buffer entry
- *
- * This routine clears a specified translation lookaside buffer (TLB)
- * entry by writing a zero to the virtual page number and valid bit.
- *
- * RETURNS: N/A
- *
- * void sysClearTlbEntry
- * (
- * int entry
- * )
- *
- */
- .ent sysClearTlbEntry
- sysClearTlbEntry:
- subu t0, a0, MIPS_N_TLB_ENTRIES - 1
- bgtz t0, invalidEntry /* is my index bad ? */
- move t1, a0 /* generate unique tlbhi value */
- sll t1, P_ENTRY_SHIFT+1 /* leave Valid bit set to zero */
- /* +1 because VPN2 field maps 2 pages */
- mtc0 t1,C0_TLBHI /* set tlbhi entry */
- mtc0 zero,C0_TLBLO0 /* set valid bit to zero */
- mtc0 zero,C0_TLBLO1 /* set valid bit to zero */
- mtc0 zero,C0_PAGEMASK /* 4k pages */
- mtc0 a0,C0_INX /* set up index for write */
- HAZARD_CP_WRITE
- c0 C0_WRITEI /* write entry */
- HAZARD_CP_WRITE
- invalidEntry:
- j ra
- .end sysClearTlbEntry
- /***************************************************
- *
- * sysSetTlbEntry - sets one MMU entry
- *
- * RETURNS: N/A
- *
- * void sysSetTlbEntry
- * (
- * UINT32 tlbInx /@ C0_INX reg value @/
- * UINT32 tlbHi, /@ C0_TLBHI reg value @/
- * UINT32 tlbLo0, /@ C0_TLBLO0 reg value @/
- * UINT32 tlbLo1 /@ C0_TLBLO1 reg value @/
- * )
- */
- .ent sysSetTlbEntry
- sysSetTlbEntry:
- .set noreorder
- HAZARD_CP_WRITE
- mtc0 a0,C0_INX
- mtc0 a1,C0_TLBHI
- mtc0 a2,C0_TLBLO0
- mtc0 a3,C0_TLBLO1
- HAZARD_CP_WRITE
- tlbwi
- HAZARD_TLB
- .set reorder
- j ra
- nop
- .end sysSetTlbEntry
- /*******************************************************************************
- *
- * sysCompareSet - set the timer compare register
- *
- * Care is taken to make sure that no interrupts are missed.
- *
- * RETURNS: N/A
- *
- * int sysCompareSet (void)
- *
- */
- .lcomm softCompare, 4
- .ent sysCompareSet
- sysCompareSet:
- li v1,CNTR_TMR0_COUNTREG
- sw a0,CNTR_TMR0_COMPREG
- nop
- nop
- 1:
- j ra
- .end sysCompareSet
- /*******************************************************************************
- *
- * sysCompareGet - get the timer compare register
- *
- * Care is taken to make sure that no interrupts are missed.
- *
- * RETURNS: N/A
- *
- * int sysCompareGet (void)
- *
- */
- .ent sysCompareGet
- sysCompareGet:
- li t0,CNTR_TMR0_COMPREG
- lw v0,0x0(t0)
- nop
- j ra
- .end sysCompareGet
- /*******************************************************************************
- *
- * sysWbFlush - flush the write buffer
- *
- * This routine flushes the write buffers, making certain all subsequent
- * memory writes have occurred. It is used during critical periods only, e.g.,
- * after memory-mapped I/O register access.
- *
- * RETURNS: N/A
- *
- * sysWbFlush (void)
- *
- */
- .ent sysWbFlush
- sysWbFlush:
- sync
- j ra
- .end sysWbFlush
- /*******************************************************************************
- *
- * sysFpaAck - acknowledge a floating point unit interrupt
- *
- * This routine writes the floating point unit (FPU) status register to
- * acknowledge the appropriate FPU interrupt. It returns an index to the vector
- * table.
- *
- * RETURNS: An interrupt vector.
- * int sysFpaAck (void)
- */
- .ent sysFpaAck
- sysFpaAck:
- j ra /* return to caller */
- .end sysFpaAck
- /******************************************************************************
- *
- * sysPciBusErrEnable - Enable PCI bus errors
- *
- * This routine sets the Bus Error Control Register bit 7
- * to enable PCI bus error generation.
- *
- * RETURNS: N/A
- *
- * void sysPciBusErrEnable (void)
- *
- */
- .globl sysPciBusErrEnable
- .ent sysPciBusErrEnable
- sysPciBusErrEnable:
- .set noreorder
- li t0, PCI_BASE
- lw t1, 0x0(t0)
- ori t1, PCIC_IEN
- sw t1, 0x0(t0)
- j ra
- nop
- .set reorder
- .end sysPciBusErrEnable
- /******************************************************************************
- *
- * sysPciBusErrDisable - Disable PCI bus errors
- *
- * This routine resets the Bus Error Control Register bit 7
- * to disable PCI bus error generation.
- *
- * RETURNS: N/A
- *
- * void sysPciBusErrDisable (void)
- *
- */
- .globl sysPciBusErrDisable
- .ent sysPciBusErrDisable
- sysPciBusErrDisable:
- .set noreorder
- li t0, PCI_BASE
- lw t1, 0(t0)
- li t2, ~PCIC_IEN
- and t1, t2
- sw t1, 0x0(t0)
- j ra
- nop
- .set reorder
- .end sysPciBusErrDisable
- /******************************************************************************
- *
- * sysTimerIntClr - clear the intyerrupt generated by the CPU internal timer
- *
- * This routine clears the interrupt pending bit ,IP7, of the CAUSE register
- * using a side effect of writing to the COMPARE register
- *
- * This routine is loaded into the static interrupt priority table.
- * It is called by jumping to the address in this table, not by
- * user calls.
- *
- * SEE ALSO: sysSetCompare()
- *
- * int sysTimerIntClr ()
- */
- .ent sysTimerIntClr
- sysTimerIntClr:
- /* give us as long as possible before a clock interrupt */
- li t0, 1
- mtc0 t0, C0_COUNT
- mtc0 zero, C0_COMPARE
- nop
- j ra /* return */
- .end sysTimerIntClr
- /*******************************************************************************
- *
- * sysWait - wait until the input buffer become empty
- *
- * wait until the input buffer become empty
- *
- * RETURNS: N/A
- * void sysWait (void)
- */
- .ent sysWait
- sysWait:
- j ra /* dummy routine for now */
- .end sysWait
- /*******************************************************************************
- *
- * sysSetPageSize - Set the MMU page size
- *
- * RETURNS: N/A
- *
- * void sysSetPageSize
- * (
- * UINT32 PageSize /@ The page size @/
- * )
- */
- .ent sysSetPageSize
- sysSetPageSize:
- .set noreorder
- HAZARD_CP_WRITE
- mtc0 a0,C0_PAGEMASK
- HAZARD_CP_WRITE
- .set reorder
- j ra
- nop
- .end sysSetPageSize
- /*******************************************************************************
- *
- * sysConfig1Get - get the processor Config1 register
- *
- * RETURNS: N/A
- * int sysConfig1Get (void)
- */
- .ent sysConfig1Get
- sysConfig1Get:
- .word 0x40028001
- j ra
- .end sysConfig1Get
- /* Include Generic MIPS Support */
- #define SYS_COMPARE_SET /* The BSP implements specialized */
- #define SYS_COMPARE_GET /* versions of these routines */
- #include "sysMipsALib.s"
- #ifdef BROADCOM_BSP
- .globl vxSpGet
- .ent vxSpGet
- vxSpGet:
- .set noreorder
- j ra
- or v0,sp,sp
- .set reorder
- .end vxSpGet
- .globl vxPcGet
- .ent vxPcGet
- vxPcGet:
- .set noreorder
- or v0,ra,ra
- j ra
- nop
- .set reorder
- .end vxPcGet
- #endif /*!BROADCOM_BSP */