汇编语言

开发平台：
Windows_Unix

regkeys：源码内容
							NUM_PROPERTIES
591
s
prop_100_name
PROP_XPowerOptVerboseRpt
s
prop_100_val
"false"
s
prop_101_name
PROP_XPowerOptLoadXMLFile
s
prop_101_val
"Default"
s
prop_102_name
PROP_XPowerOptOutputFile
s
prop_102_val
"Default"
s
prop_103_name
PROP_XPowerOptLoadVCDFile
s
prop_103_val
"Default"
s
prop_104_name
PROP_XPowerOptLoadPCFFile
s
prop_104_val
"Default"
s
prop_105_name
PROP_XPowerOptInputTclScript
s
prop_105_val
""
s
prop_106_name
PROP_XPowerOtherXPowerOpts
s
prop_106_val
""
s
prop_107_name
PROP_XplorerMode
s
prop_107_val
"Off"
s
prop_108_name
PROP_UserEditorPreference
s
prop_108_val
"ISE Text Editor"
s
prop_109_name
PROP_UserEditorCustomSetting
s
prop_109_val
""
s
prop_10_name
PROP_BehavioralSimTop
s
prop_10_val
"Architecture|switch_to_led7|Behavioral"
s
prop_110_name
PROP_UserConstraintEditorPreference
s
prop_110_val
"Constraints Editor"
s
prop_111_name
PROP_FlowDebugLevel
s
prop_111_val
"0"
s
prop_112_name
PROP_FitterReportFormat
s
prop_112_val
"HTML"
s
prop_113_name
PROP_ToolPathModelSim
s
prop_113_val
""
s
prop_114_name
PROP_ToolPathSynplify
s
prop_114_val
""
s
prop_115_name
PROP_ToolPathSynplifyPro
s
prop_115_val
""
s
prop_116_name
PROP_ToolPathPrecision
s
prop_116_val
""
s
prop_117_name
PROP_ToolPathChipscope
s
prop_117_val
""
s
prop_118_name
PROP_Enable_Message_Capture
s
prop_118_val
"true"
s
prop_119_name
PROP_Enable_Message_Filtering
s
prop_119_val
"false"
s
prop_11_name
PROP_PostXlateSimTop
s
prop_11_val
"Architecture|switch_to_led7|Behavioral"
s
prop_120_name
PROP_Enable_Incremental_Messaging
s
prop_120_val
"false"
s
prop_121_name
PROP_lockPinsUcfFile
s
prop_121_val
""
s
prop_122_name
PROP_PrecInputSdcFile
s
prop_122_val
""
s
prop_123_name
PROP_PrecResourceSharing
s
prop_123_val
"true"
s
prop_124_name
PROP_PrecAdvFsmOptimization
s
prop_124_val
"true"
s
prop_125_name
PROP_PrecUseSafeFsm
s
prop_125_val
"false"
s
prop_126_name
PROP_PrecFsmEncoding
s
prop_126_val
"Auto"
s
prop_127_name
PROP_PrecVhdlSyntax
s
prop_127_val
"VHDL 93"
s
prop_128_name
PROP_PrecFullCase
s
prop_128_val
"false"
s
prop_129_name
PROP_PrecParallelCase
s
prop_129_val
"false"
s
prop_12_name
PROP_PostMapSimTop
s
prop_12_val
"Architecture|switch_to_led7|Behavioral"
s
prop_130_name
PROP_PrecArrayBoundsCheck
s
prop_130_val
"false"
s
prop_131_name
PROP_PrecAddIOPads
s
prop_131_val
"true"
s
prop_132_name
PROP_PrecTranSetResetToLatches
s
prop_132_val
"true"
s
prop_133_name
PROP_PrecRunRetiming
s
prop_133_val
"false"
s
prop_134_name
PROP_PrecRptclockFreq
s
prop_134_val
"true"
s
prop_135_name
PROP_PrecRptTimingSummary
s
prop_135_val
"true"
s
prop_136_name
PROP_PrecRptCriticalPaths
s
prop_136_val
"true"
s
prop_137_name
PROP_PrecRptTimingViolations
s
prop_137_val
"true"
s
prop_138_name
PROP_PrecShowNetFanOut
s
prop_138_val
"true"
s
prop_139_name
PROP_PrecShowClockDomainCrossing
s
prop_139_val
"false"
s
prop_13_name
PROP_PostParSimTop
s
prop_13_val
"Architecture|switch_to_led7|Behavioral"
s
prop_140_name
PROP_PrecRptMissingConstraints
s
prop_140_val
"false"
s
prop_141_name
PROP_PrecOutputFileBase
s
prop_141_val
""
s
prop_142_name
PROP_PrecCreateUcfFromRtlConstraints
s
prop_142_val
"false"
s
prop_143_name
PROP_PrecEdif
s
prop_143_val
"true"
s
prop_144_name
PROP_PrecVerilog
s
prop_144_val
"false"
s
prop_145_name
PROP_PrecVhdl
s
prop_145_val
"false"
s
prop_146_name
PROP_ToolPathLeonardoSpectrum
s
prop_146_val
""
s
prop_147_name
PROP_Parse_Edif_Module
s
prop_147_val
"false"
s
prop_148_name
PROP_SynthUseFsmExplorerData
s
prop_148_val
"false"
s
prop_149_name
PROP_SynthSymbolicFsm
s
prop_149_val
"true"
s
prop_14_name
PROP_PostFitSimTop
s
prop_14_val
""
s
prop_150_name
PROP_SynthResourceSharing
s
prop_150_val
"true"
s
prop_151_name
PROP_SynthNumCriticalPaths
s
prop_151_val
"0"
s
prop_152_name
PROP_SynthNumStartEndPoints
s
prop_152_val
"0"
s
prop_153_name
PROP_WriteVerilogNetlist
s
prop_153_val
"false"
s
prop_154_name
PROP_WriteVHDLNetlist
s
prop_154_val
"false"
s
prop_155_name
PROP_WriteVendorConstFile
s
prop_155_val
"true"
s
prop_156_name
PROP_SynthDisableIOInsertion
s
prop_156_val
"false"
s
prop_157_name
PROP_SynthFanout
s
prop_157_val
"100"
s
prop_158_name
PROP_ConstFileName
s
prop_158_val
""
s
prop_159_name
PROP_ConstFileAddOption
s
prop_159_val
"true"
s
prop_15_name
PROP_PostSynthSimTop
s
prop_15_val
"Architecture|switch_to_led7|Behavioral"
s
prop_160_name
PROP_SynthProcBound
s
prop_160_val
"true"
s
prop_161_name
PROP_SynthEnumEncoding
s
prop_161_val
"default"
s
prop_162_name
PROP_Verilog2001
s
prop_162_val
"true"
s
prop_163_name
PROP_SynthModular
s
prop_163_val
"false"
s
prop_164_name
PROP_SynthRetiming
s
prop_164_val
"false"
s
prop_165_name
PROP_SynthPipelining
s
prop_165_val
"true"
s
prop_166_name
PROP_EnableWYSIWYG
s
prop_166_val
"None"
s
prop_167_name
PROP_xcpldUseLocConst
s
prop_167_val
"Always"
s
prop_168_name
PROP_xcpldFitDesInit
s
prop_168_val
"Low"
s
prop_169_name
PROP_xcpldFitDesTimingCst
s
prop_169_val
"true"
s
prop_16_name
PROP_UseSmartGuide
s
prop_16_val
"false"
s
prop_170_name
PROP_CPLDFitkeepio
s
prop_170_val
"false"
s
prop_171_name
PROP_cpldBestFit
s
prop_171_val
"false"
s
prop_172_name
PROP_xcpldFitDesMultiLogicOpt
s
prop_172_val
"true"
s
prop_173_name
PROP_cpldfit_otherCmdLineOptions
s
prop_173_val
""
s
prop_174_name
PROP_fitGenSimModel
s
prop_174_val
"false"
s
prop_175_name
PROP_cpldfitHDLeqStyle
s
prop_175_val
"Source"
s
prop_176_name
PROP_xcpldFitDesSlew
s
prop_176_val
"Fast"
s
prop_177_name
PROP_xcpldUseGlobalClocks
s
prop_177_val
"true"
s
prop_178_name
PROP_xcpldUseGlobalOutputEnables
s
prop_178_val
"true"
s
prop_179_name
PROP_xcpldUseGlobalSetReset
s
prop_179_val
"true"
s
prop_17_name
PROP_PartitionCreateDelete
s
prop_17_val
""
s
prop_180_name
PROP_hprep6_autosig
s
prop_180_val
"false"
s
prop_181_name
PROP_hprep6_otherCmdLineOptions
s
prop_181_val
""
s
prop_182_name
PROP_xcpldFittimRptOption
s
prop_182_val
"Summary"
s
prop_183_name
PROP_taengine_otherCmdLineOptions
s
prop_183_val
""
s
prop_184_name
PROP_xilxSynthMacroPreserve
s
prop_184_val
"true"
s
prop_185_name
PROP_xilxSynthXORPreserve
s
prop_185_val
"true"
s
prop_186_name
PROP_xilxSynthKeepHierarchy_CPLD
s
prop_186_val
"Yes"
s
prop_187_name
PROP_PlsClockEnable
s
prop_187_val
"true"
s
prop_188_name
PROP_CompxlibAbelLib
s
prop_188_val
"true"
s
prop_189_name
PROP_CompxlibCPLDDetLib
s
prop_189_val
"true"
s
prop_18_name
PROP_PartitionForceSynth
s
prop_18_val
""
s
prop_190_name
PROP_xcpldFitDesTriMode
s
prop_190_val
"Keeper"
s
prop_191_name
PROP_xcpldFitTemplate_xpla3
s
prop_191_val
"Optimize Density"
s
prop_192_name
PROP_FunctionBlockInputLimit
s
prop_192_val
"38"
s
prop_193_name
PROP_xcpldFitDesInputLmt_xbr
s
prop_193_val
"32"
s
prop_194_name
PROP_xcpldFitDesUnused
s
prop_194_val
"Keeper"
s
prop_195_name
PROP_xcpldFitDesVolt
s
prop_195_val
"LVCMOS18"
s
prop_196_name
PROP_UseDataGate
s
prop_196_val
"true"
s
prop_197_name
PROP_xilxBitgCfg_GenOpt_IEEE1532File_xbr
s
prop_197_val
"false"
s
prop_198_name
PROP_mapIgnoreTimingConstraints
s
prop_198_val
"false"
s
prop_199_name
PROP_mapTimingAnalyzerLoadDesign
s
prop_199_val
"true"
s
prop_19_name
PROP_PartitionForceTranslate
s
prop_19_val
""
s
prop_1_name
PROP_SteCreatedBy
s
prop_1_val
""
s
prop_200_name
PROP_parTimingAnalyzerLoadDesign
s
prop_200_val
"true"
s
prop_201_name
PROP_ngdbuildUseLOCConstraints
s
prop_201_val
"true"
s
prop_202_name
PROP_xilxNgdbldNTType
s
prop_202_val
"Timestamp"
s
prop_203_name
PROP_xilxNgdbldIOPads
s
prop_203_val
"false"
s
prop_204_name
PROP_xilxNgdbldUnexpBlks
s
prop_204_val
"false"
s
prop_205_name
PROP_xilxNgdbldUR
s
prop_205_val
""
s
prop_206_name
PROP_xilxMapTrimUnconnSig
s
prop_206_val
"true"
s
prop_207_name
PROP_xilxMapReplicateLogic
s
prop_207_val
"true"
s
prop_208_name
PROP_xilxMapAllowLogicOpt
s
prop_208_val
"false"
s
prop_209_name
PROP_xilxMapCoverMode
s
prop_209_val
"Area"
s
prop_20_name
PROP_PartitionForcePlacement
s
prop_20_val
""
s
prop_210_name
PROP_xilxMapReportDetail
s
prop_210_val
"false"
s
prop_211_name
PROP_mapUseRLOCConstraints
s
prop_211_val
"true"
s
prop_212_name
PROP_xilxMapPackRegInto
s
prop_212_val
"Off"
s
prop_213_name
PROP_xilxMapDisableRegOrdering
s
prop_213_val
"false"
s
prop_214_name
PROP_xilxTriStateBuffTXMode
s
prop_214_val
"Off"
s
prop_215_name
PROP_xilxMapSliceLogicInUnusedBRAMs
s
prop_215_val
"false"
s
prop_216_name
PROP_MapGlobalOptimization
s
prop_216_val
"false"
s
prop_217_name
PROP_map_otherCmdLineOptions
s
prop_217_val
""
s
prop_218_name
PROP_xilxPARplacerEffortLevel
s
prop_218_val
"None"
s
prop_219_name
PROP_xilxPARrouterEffortLevel
s
prop_219_val
"None"
s
prop_21_name
PROP_DesignName
s
prop_21_val
"switch_to_led7"
s
prop_220_name
PROP_xilxPARplacerCostTable
s
prop_220_val
"1"
s
prop_221_name
PROP_xilxPARstrat
s
prop_221_val
"Normal Place and Route"
s
prop_222_name
PROP_parUseTimingConstraints
s
prop_222_val
"true"
s
prop_223_name
PROP_parIgnoreTimingConstraints
s
prop_223_val
"false"
s
prop_224_name
PROP_xilxPARuseBondedIO
s
prop_224_val
"false"
s
prop_225_name
PROP_par_otherCmdLineOptions
s
prop_225_val
""
s
prop_226_name
PROP_mpprViewParRptsForAllRslt
s
prop_226_val
"true"
s
prop_227_name
PROP_mpprViewPadRptsForAllRslt
s
prop_227_val
"true"
s
prop_228_name
PROP_mpprRsltToCopy
s
prop_228_val
""
s
prop_229_name
PROP_xilxBitgCfg_GenOpt_DRC
s
prop_229_val
"true"
s
prop_22_name
PROP_Dummy
s
prop_22_val
"dum1"
s
prop_230_name
PROP_xilxBitgCfg_GenOpt_BitFile
s
prop_230_val
"true"
s
prop_231_name
PROP_xilxBitgCfg_GenOpt_BinaryFile
s
prop_231_val
"false"
s
prop_232_name
PROP_xilxBitgCfg_GenOpt_ASCIIFile
s
prop_232_val
"false"
s
prop_233_name
PROP_xilxBitgCfg_GenOpt_Compress
s
prop_233_val
"false"
s
prop_234_name
PROP_xilxBitgCfg_GenOpt_GClkDel0
s
prop_234_val
"11111"
s
prop_235_name
PROP_xilxBitgCfg_GenOpt_GClkDel1
s
prop_235_val
"11111"
s
prop_236_name
PROP_xilxBitgCfg_GenOpt_GClkDel2
s
prop_236_val
"11111"
s
prop_237_name
PROP_xilxBitgCfg_GenOpt_GClkDel3
s
prop_237_val
"11111"
s
prop_238_name
PROP_bitgen_otherCmdLineOptions
s
prop_238_val
""
s
prop_239_name
PROP_xilxBitgCfg_Clk
s
prop_239_val
"Pull Up"
s
prop_23_name
PROP_LastAppliedGoal
s
prop_23_val
"Balanced"
s
prop_240_name
PROP_xilxBitgCfg_M0
s
prop_240_val
"Pull Up"
s
prop_241_name
PROP_xilxBitgCfg_M1
s
prop_241_val
"Pull Up"
s
prop_242_name
PROP_xilxBitgCfg_M2
s
prop_242_val
"Pull Up"
s
prop_243_name
PROP_xilxBitgCfg_Pgm
s
prop_243_val
"Pull Up"
s
prop_244_name
PROP_xilxBitgCfg_Done
s
prop_244_val
"Pull Up"
s
prop_245_name
PROP_xilxBitgCfg_TCK
s
prop_245_val
"Pull Up"
s
prop_246_name
PROP_xilxBitgCfg_TDI
s
prop_246_val
"Pull Up"
s
prop_247_name
PROP_xilxBitgCfg_TDO
s
prop_247_val
"Pull Up"
s
prop_248_name
PROP_xilxBitgCfg_TMS
s
prop_248_val
"Pull Up"
s
prop_249_name
PROP_xilxBitgCfg_Unused
s
prop_249_val
"Pull Down"
s
prop_24_name
PROP_LastAppliedStrategy
s
prop_24_val
"Xilinx Default (unlocked)"
s
prop_250_name
PROP_xilxBitgCfg_Code
s
prop_250_val
"0xFFFFFFFF"
s
prop_251_name
PROP_xilxBitgStart_Clk
s
prop_251_val
"CCLK"
s
prop_252_name
PROP_xilxBitgStart_IntDone
s
prop_252_val
"false"
s
prop_253_name
PROP_xilxBitgStart_Clk_Done
s
prop_253_val
"Default (4)"
s
prop_254_name
PROP_xilxBitgStart_Clk_EnOut
s
prop_254_val
"Default (5)"
s
prop_255_name
PROP_xilxBitgStart_Clk_RelSet
s
prop_255_val
"Default (6)"
s
prop_256_name
PROP_xilxBitgStart_Clk_WrtEn
s
prop_256_val
"Default (6)"
s
prop_257_name
PROP_xilxBitgStart_Clk_RelDLL
s
prop_257_val
"Default (NoWait)"
s
prop_258_name
PROP_xilxBitgStart_Clk_DriveDone
s
prop_258_val
"false"
s
prop_259_name
PROP_xilxBitgReadBk_Sec
s
prop_259_val
"Enable Readback and Reconfiguration"
s
prop_25_name
PROP_LastUnlockStatus
s
prop_25_val
"false"
s
prop_260_name
PROP_xilxBitgCfg_GenOpt_ReadBack
s
prop_260_val
"false"
s
prop_261_name
PROP_CurrentFloorplanFile
s
prop_261_val
""
s
prop_262_name
PROP_xilxPreTrceRpt
s
prop_262_val
"Verbose Report"
s
prop_263_name
PROP_xilxPreTrceRptLimit
s
prop_263_val
"3"
s
prop_264_name
PROP_xilxPreTrceAdvAna
s
prop_264_val
"false"
s
prop_265_name
PROP_xilxPreTrceUncovPath
s
prop_265_val
""
s
prop_266_name
PROP_xilxPreTrceEndpointPath
s
prop_266_val
""
s
prop_267_name
PROP_PreTrceFastPath
s
prop_267_val
"false"
s
prop_268_name
PROP_xilxPostTrceRpt
s
prop_268_val
"Verbose Report"
s
prop_269_name
PROP_xilxPostTrceRptLimit
s
prop_269_val
"3"
s
prop_26_name
PROP_UserBrowsedStrategyFiles
s
prop_26_val
""
s
prop_270_name
PROP_xilxPostTrceAdvAna
s
prop_270_val
"false"
s
prop_271_name
PROP_xilxPostTrceUncovPath
s
prop_271_val
""
s
prop_272_name
PROP_xilxPostTrceEndpointPath
s
prop_272_val
""
s
prop_273_name
PROP_PostTrceFastPath
s
prop_273_val
"false"
s
prop_274_name
PROP_xilxPostTrceStamp
s
prop_274_val
""
s
prop_275_name
PROP_PreTrceGenTimegroups
s
prop_275_val
"false"
s
prop_276_name
PROP_PreTrceGenDatasheet
s
prop_276_val
"true"
s
prop_277_name
PROP_PostTrceGenTimegroups
s
prop_277_val
"false"
s
prop_278_name
PROP_PostTrceGenDatasheet
s
prop_278_val
"true"
s
prop_279_name
PROP_xilxPostTrceTSIFile
s
prop_279_val
""
s
prop_27_name
PROP_SimUseCustom_launchMSim
s
prop_27_val
"false"
s
prop_280_name
PROP_PreTrceTSIFile
s
prop_280_val
""
s
prop_281_name
PROP_LoadPostTrceTSIFile
s
prop_281_val
"false"
s
prop_282_name
PROP_primetimeBlockRamData
s
prop_282_val
""
s
prop_283_name
PROP_primeFlatternOutputNetlist
s
prop_283_val
"false"
s
prop_284_name
PROP_primeCorrelateOutput
s
prop_284_val
"false"
s
prop_285_name
PROP_primeTopLevelModule
s
prop_285_val
""
s
prop_286_name
PROP_AutoGenFile
s
prop_286_val
"false"
s
prop_287_name
PROP_CompxlibXlnxCoreLib
s
prop_287_val
"true"
s
prop_288_name
PROP_xilxSynthGlobOpt
s
prop_288_val
"AllClockNets"
s
prop_289_name
PROP_xstAutoBRAMPacking
s
prop_289_val
"false"
s
prop_28_name
PROP_SimUserCompileList_launchMSim
s
prop_28_val
""
s
prop_290_name
PROP_xstBRAMUtilRatio
s
prop_290_val
"100"
s
prop_291_name
PROP_xstAsynToSync
s
prop_291_val
"false"
s
prop_292_name
PROP_xstReadCores
s
prop_292_val
"true"
s
prop_293_name
PROP_xstCoresSearchDir
s
prop_293_val
""
s
prop_294_name
PROP_xstWriteTimingConstraints
s
prop_294_val
"false"
s
prop_295_name
PROP_xstSliceUtilRatio
s
prop_295_val
"100"
s
prop_296_name
PROP_xstCrossClockAnalysis
s
prop_296_val
"false"
s
prop_297_name
PROP_xstFsmStyle
s
prop_297_val
"LUT"
s
prop_298_name
PROP_SynthExtractRAM
s
prop_298_val
"true"
s
prop_299_name
PROP_SynthExtractROM
s
prop_299_val
"true"
s
prop_29_name
PROP_SimUseCustom_behav
s
prop_29_val
"false"
s
prop_2_name
PROP_SimUseCustom_postXlate
s
prop_2_val
"false"
s
prop_300_name
PROP_SynthDecoderExtract
s
prop_300_val
"true"
s
prop_301_name
PROP_SynthEncoderExtract
s
prop_301_val
"Yes"
s
prop_302_name
PROP_SynthShiftRegExtract
s
prop_302_val
"true"
s
prop_303_name
PROP_SynthLogicalShifterExtract
s
prop_303_val
"true"
s
prop_304_name
PROP_xilxSynthRegBalancing
s
prop_304_val
"No"
s
prop_305_name
PROP_xstPackIORegister
s
prop_305_val
"Auto"
s
prop_306_name
PROP_xstSlicePacking
s
prop_306_val
"true"
s
prop_307_name
PROP_xstTristate2Logic
s
prop_307_val
"Yes"
s
prop_308_name
PROP_xstOptimizeInsPrimtives
s
prop_308_val
"false"
s
prop_309_name
PROP_xilxSynthRegDuplication
s
prop_309_val
"true"
s
prop_30_name
PROP_SimDo
s
prop_30_val
"true"
s
prop_310_name
PROP_xstUseClockEnable
s
prop_310_val
"Yes"
s
prop_311_name
PROP_xstUseSyncSet
s
prop_311_val
"Yes"
s
prop_312_name
PROP_xstUseSyncReset
s
prop_312_val
"Yes"
s
prop_313_name
PROP_VirtexSynthAutoConstrain
s
prop_313_val
"true"
s
prop_314_name
PROP_ibiswriterGeneratePackageParasitics
s
prop_314_val
"false"
s
prop_315_name
PROP_xilxMapTimingDrivenPacking
s
prop_315_val
"false"
s
prop_316_name
PROP_xilxBitgCfg_GenOpt_IEEE1532File
s
prop_316_val
"false"
s
prop_317_name
PROP_xilxBitgCfg_GenOpt_EnableCRC
s
prop_317_val
"true"
s
prop_318_name
PROP_xilxBitgCfg_PwrDown
s
prop_318_val
"Pull Up"
s
prop_319_name
PROP_xilxBitgCfg_DCMShutdown
s
prop_319_val
"false"
s
prop_31_name
PROP_SimUseCustom_postMap
s
prop_31_val
"false"
s
prop_320_name
PROP_xilxBitgCfg_DCMBandgap
s
prop_320_val
"false"
s
prop_321_name
PROP_xilxBitgStart_Clk_MatchCycle
s
prop_321_val
"Auto"
s
prop_322_name
PROP_bitgen_Encrypt_keySeq0
s
prop_322_val
"None"
s
prop_323_name
PROP_bitgen_Encrypt_keySeq1
s
prop_323_val
"None"
s
prop_324_name
PROP_bitgen_Encrypt_keySeq2
s
prop_324_val
"None"
s
prop_325_name
PROP_bitgen_Encrypt_keySeq3
s
prop_325_val
"None"
s
prop_326_name
PROP_bitgen_Encrypt_keySeq4
s
prop_326_val
"None"
s
prop_327_name
PROP_bitgen_Encrypt_keySeq5
s
prop_327_val
"None"
s
prop_328_name
PROP_bitgen_Encrypt_startKey
s
prop_328_val
"None"
s
prop_329_name
PROP_bitgen_Encrypt_startCBC
s
prop_329_val
""
s
prop_32_name
PROP_SimUseCustom_postPar
s
prop_32_val
"false"
s
prop_330_name
PROPEXT_xilxMapGenInputK_virtex2
s
prop_330_val
"4"
s
prop_331_name
PROPEXT_SynthMultStyle_virtex2
s
prop_331_val
"Auto"
s
prop_332_name
PROPEXT_xilxSynthMaxFanout_virtex2
s
prop_332_val
"500"
s
prop_333_name
PROP_usedsp48
s
prop_333_val
"Auto"
s
prop_334_name
PROP_xstDSPUtilRatio
s
prop_334_val
"100"
s
prop_335_name
PROPEXT_xilxBitgCfg_DCIUpdateMode_spartan3
s
prop_335_val
"As Required"
s
prop_336_name
PROPEXT_xilxSynthAddBufg_spartan3e
s
prop_336_val
"24"
s
prop_337_name
PROPEXT_xilxBitgCfg_Rate_spartan3e
s
prop_337_val
"Default (1)"
s
prop_338_name
PROP_TopDesignUnit
s
prop_338_val
""
s
prop_339_name
PROP_TopDesignUnit
s
prop_339_val
""
s
prop_33_name
PROP_ModelSimUseConfigName
s
prop_33_val
"false"
s
prop_340_name
PROP_TopDesignUnit
s
prop_340_val
""
s
prop_341_name
PROP_TopDesignUnit
s
prop_341_val
""
s
prop_342_name
PROP_TopDesignUnit
s
prop_342_val
""
s
prop_343_name
PROP_TopDesignUnit
s
prop_343_val
""
s
prop_344_name
PROP_TopDesignUnit
s
prop_344_val
""
s
prop_345_name
PROP_TopDesignUnit
s
prop_345_val
""
s
prop_346_name
PROP_TopDesignUnit
s
prop_346_val
""
s
prop_347_name
PROP_TopDesignUnit
s
prop_347_val
""
s
prop_348_name
PROP_TopDesignUnit
s
prop_348_val
""
s
prop_349_name
PROP_TopDesignUnit
s
prop_349_val
""
s
prop_34_name
PROP_MSimSDFTimingToBeRead
s
prop_34_val
"Setup Time"
s
prop_350_name
PROP_TopDesignUnit
s
prop_350_val
""
s
prop_351_name
PROP_TopDesignUnit
s
prop_351_val
""
s
prop_352_name
PROP_TopDesignUnit
s
prop_352_val
""
s
prop_353_name
PROP_TopDesignUnit
s
prop_353_val
""
s
prop_354_name
PROP_TopDesignUnit
s
prop_354_val
""
s
prop_355_name
PROP_ISimIncreCompilation
s
prop_355_val
"true"
s
prop_356_name
PROP_ISimIncreCompilation
s
prop_356_val
"true"
s
prop_357_name
PROP_ISimIncreCompilation
s
prop_357_val
"true"
s
prop_358_name
PROP_ISimIncreCompilation
s
prop_358_val
"true"
s
prop_359_name
PROP_ISimIncreCompilation
s
prop_359_val
"true"
s
prop_35_name
PROP_OverwriteSym
s
prop_35_val
"false"
s
prop_360_name
PROP_ISimIncreCompilation
s
prop_360_val
"true"
s
prop_361_name
PROP_ISimIncreCompilation
s
prop_361_val
"true"
s
prop_362_name
PROP_ISimIncreCompilation
s
prop_362_val
"true"
s
prop_363_name
PROP_ISimIncreCompilation
s
prop_363_val
"true"
s
prop_364_name
PROP_ISimIncreCompilation
s
prop_364_val
"true"
s
prop_365_name
PROP_ISimIncreCompilation
s
prop_365_val
"true"
s
prop_366_name
PROP_ISimCompileForHdlDebug
s
prop_366_val
"true"
s
prop_367_name
PROP_ISimCompileForHdlDebug
s
prop_367_val
"true"
s
prop_368_name
PROP_ISimCompileForHdlDebug
s
prop_368_val
"true"
s
prop_369_name
PROP_ISimCompileForHdlDebug
s
prop_369_val
"true"
s
prop_36_name
PROP_CompxlibOutputDir
s
prop_36_val
"$XILINX/<language>/<simulator>"
s
prop_370_name
PROP_ISimCompileForHdlDebug
s
prop_370_val
"true"
s
prop_371_name
PROP_ISimCompileForHdlDebug
s
prop_371_val
"true"
s
prop_372_name
PROP_ISimCompileForHdlDebug
s
prop_372_val
"true"
s
prop_373_name
PROP_ISimCompileForHdlDebug
s
prop_373_val
"true"
s
prop_374_name
PROP_ISimCompileForHdlDebug
s
prop_374_val
"true"
s
prop_375_name
PROP_ISimValueRangeCheck
s
prop_375_val
"false"
s
prop_376_name
PROP_ISimValueRangeCheck
s
prop_376_val
"false"
s
prop_377_name
PROP_ISimValueRangeCheck
s
prop_377_val
"false"
s
prop_378_name
PROP_ISimValueRangeCheck
s
prop_378_val
"false"
s
prop_379_name
PROP_ISimValueRangeCheck
s
prop_379_val
"false"
s
prop_37_name
PROP_CompxlibOverwriteLib
s
prop_37_val
"Overwrite"
s
prop_380_name
PROP_ISimValueRangeCheck
s
prop_380_val
"false"
s
prop_381_name
PROP_ISimValueRangeCheck
s
prop_381_val
"false"
s
prop_382_name
PROP_ISimValueRangeCheck
s
prop_382_val
"false"
s
prop_383_name
PROP_ISimValueRangeCheck
s
prop_383_val
"false"
s
prop_384_name
PROP_ISimValueRangeCheck
s
prop_384_val
"false"
s
prop_385_name
PROP_ISimValueRangeCheck
s
prop_385_val
"false"
s
prop_386_name
PROP_ISimSpecifySearchDirectory
s
prop_386_val
""
s
prop_387_name
PROP_ISimSpecifySearchDirectory
s
prop_387_val
""
s
prop_388_name
PROP_ISimSpecifySearchDirectory
s
prop_388_val
""
s
prop_389_name
PROP_ISimSpecifySearchDirectory
s
prop_389_val
""
s
prop_38_name
PROP_CompxlibOtherCompxlibOpts
s
prop_38_val
""
s
prop_390_name
PROP_ISimSpecifySearchDirectory
s
prop_390_val
""
s
prop_391_name
PROP_ISimSpecifySearchDirectory
s
prop_391_val
""
s
prop_392_name
PROP_ISimSpecifySearchDirectory
s
prop_392_val
""
s
prop_393_name
PROP_ISimSpecifySearchDirectory
s
prop_393_val
""
s
prop_394_name
PROP_ISimSpecifySearchDirectory
s
prop_394_val
""
s
prop_395_name
PROP_ISimSpecifySearchDirectory
s
prop_395_val
""
s
prop_396_name
PROP_ISimSpecifySearchDirectory
s
prop_396_val
""
s
prop_397_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_397_val
""
s
prop_398_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_398_val
""
s
prop_399_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_399_val
""
s
prop_39_name
PROP_CompxlibSimPrimatives
s
prop_39_val
"true"
s
prop_3_name
PROP_StartImpView
s
prop_3_val
""
s
prop_400_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_400_val
""
s
prop_401_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_401_val
""
s
prop_402_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_402_val
""
s
prop_403_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_403_val
""
s
prop_404_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_404_val
""
s
prop_405_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_405_val
""
s
prop_406_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_406_val
""
s
prop_407_name
PROP_ISimSpecifyDefMacroAndValue
s
prop_407_val
""
s
prop_408_name
PROP_xstVeriIncludeDir
s
prop_408_val
""
s
prop_409_name
PROP_xstVeriIncludeDir
s
prop_409_val
""
s
prop_40_name
PROP_XPORTInpFileName
s
prop_40_val
""
s
prop_410_name
PROP_ISimSpecifySearchDir
s
prop_410_val
""
s
prop_411_name
PROP_ISimSpecifySearchDir
s
prop_411_val
""
s
prop_412_name
PROP_DevFamily
s
prop_412_val
"Spartan3E"
s
prop_413_name
PROP_Simulator
s
prop_413_val
"ISE Simulator (VHDL/Verilog)"
s
prop_414_name
PROP_SmartGuideFileName
s
prop_414_val
"switch_to_led7_guide.ncd"
s
prop_415_name
PROP_vsim_otherCmdLineOptions
s
prop_415_val
""
s
prop_416_name
PROP_vlog_otherCmdLineOptions
s
prop_416_val
""
s
prop_417_name
PROP_vcom_otherCmdLineOptions
s
prop_417_val
""
s
prop_418_name
PROP_ModelSimSignalWin
s
prop_418_val
"true"
s
prop_419_name
PROP_ModelSimWaveWin
s
prop_419_val
"true"
s
prop_41_name
PROP_XPORTInpFileType
s
prop_41_val
"ABEL"
s
prop_420_name
PROP_ModelSimStructWin
s
prop_420_val
"true"
s
prop_421_name
PROP_ModelSimSourceWin
s
prop_421_val
"false"
s
prop_422_name
PROP_ModelSimListWin
s
prop_422_val
"false"
s
prop_423_name
PROP_ModelSimVarsWin
s
prop_423_val
"false"
s
prop_424_name
PROP_ModelSimProcWin
s
prop_424_val
"false"
s
prop_425_name
PROP_ModelSimDataWin
s
prop_425_val
"false"
s
prop_426_name
PROP_ModelSimSimRes
s
prop_426_val
"Default (1 ps)"
s
prop_427_name
PROP_SimSyntax
s
prop_427_val
"93"
s
prop_428_name
PROP_SimUseExpDeclOnly
s
prop_428_val
"true"
s
prop_429_name
PROP_ModelSimSimRunTime_tb
s
prop_429_val
"1000ns"
s
prop_42_name
PROP_XPORTOutFileType
s
prop_42_val
"VHDL"
s
prop_430_name
PROP_ModelSimUutInstName_postMap
s
prop_430_val
"UUT"
s
prop_431_name
PROP_ModelSimUutInstName_postPar
s
prop_431_val
"UUT"
s
prop_432_name
PROP_SimGenVcdFile
s
prop_432_val
"false"
s
prop_433_name
PROP_SimCustom_launchMSim
s
prop_433_val
""
s
prop_434_name
PROP_SimCustom_behav
s
prop_434_val
""
s
prop_435_name
PROP_SimUserCompileList_behav
s
prop_435_val
""
s
prop_436_name
PROP_SimCustom_postXlate
s
prop_436_val
""
s
prop_437_name
PROP_SimCustom_postMap
s
prop_437_val
""
s
prop_438_name
PROP_SimCustom_postPar
s
prop_438_val
""
s
prop_439_name
PROP_ModelSimSimRunTime_tbw
s
prop_439_val
"1000ns"
s
prop_43_name
PROP_XPORTlistInpFiles
s
prop_43_val
"false"
s
prop_440_name
PROP_ModelSimConfigName
s
prop_440_val
"Default"
s
prop_441_name
PROP_SimModelRenTopLevInstTo
s
prop_441_val
"UUT"
s
prop_442_name
PROP_SynthConstraintsFile
s
prop_442_val
""
s
prop_443_name
PROP_ISimCustomSimCmdFileName_par_tb
s
prop_443_val
""
s
prop_444_name
PROP_ISimCustomSimCmdFileName_par_tbw
s
prop_444_val
""
s
prop_445_name
PROP_ISimCustomSimCmdFileName_behav_tb
s
prop_445_val
""
s
prop_446_name
PROP_ISimCustomSimCmdFileName_behav_tbw
s
prop_446_val
""
s
prop_447_name
PROP_ISimCustomSimCmdFileName_gen_tbw
s
prop_447_val
""
s
prop_448_name
PROP_ISimCustomSimCmdFileName_launch
s
prop_448_val
""
s
prop_449_name
PROP_ISimSimulationRun_par_tb
s
prop_449_val
"true"
s
prop_44_name
PROP_SimModelGenerateTestbenchFile
s
prop_44_val
"false"
s
prop_450_name
PROP_ISimSimulationRun_par_tbw
s
prop_450_val
"true"
s
prop_451_name
PROP_ISimSimulationRun_behav_tb
s
prop_451_val
"true"
s
prop_452_name
PROP_ISimSimulationRun_behav_tbw
s
prop_452_val
"true"
s
prop_453_name
PROP_ISimStoreAllSignalTransitions_par_tb
s
prop_453_val
"false"
s
prop_454_name
PROP_ISimStoreAllSignalTransitions_par_tbw
s
prop_454_val
"false"
s
prop_455_name
PROP_ISimStoreAllSignalTransitions_behav_tb
s
prop_455_val
"false"
s
prop_456_name
PROP_ISimStoreAllSignalTransitions_behav_tbw
s
prop_456_val
"false"
s
prop_457_name
PROP_ISimGenVCDFile_par_tb
s
prop_457_val
"false"
s
prop_458_name
PROP_ISimGenVCDFile_par_tbw
s
prop_458_val
"false"
s
prop_459_name
PROP_ISimCustomCompilationOrderFile
s
prop_459_val
""
s
prop_45_name
PROP_SimModelInsertBuffersPulseSwallow
s
prop_45_val
"false"
s
prop_460_name
PROP_impactBaud
s
prop_460_val
"None"
s
prop_461_name
PROP_impactConfigMode
s
prop_461_val
"None"
s
prop_462_name
PROP_impactPort
s
prop_462_val
"Auto - default"
s
prop_463_name
PROP_XPowerOptAdvancedVerboseRpt
s
prop_463_val
"false"
s
prop_464_name
PROP_XPowerOptMaxNumberLines
s
prop_464_val
"1000"
s
prop_465_name
PROP_xstSafeImplement
s
prop_465_val
"No"
s
prop_466_name
PROP_XplorerRunType
s
prop_466_val
"Yes"
s
prop_467_name
PROP_XplorerNumIterations
s
prop_467_val
"7"
s
prop_468_name
PROP_XplorerEnableRetiming
s
prop_468_val
"true"
s
prop_469_name
PROP_XplorerWarnToBackup
s
prop_469_val
"true"
s
prop_46_name
PROP_SimModelOtherNetgenOpts
s
prop_46_val
""
s
prop_470_name
PROP_XplorerOtherCmdLineOptions
s
prop_470_val
""
s
prop_471_name
PROP_PrecNumOfSumPaths
s
prop_471_val
"10"
s
prop_472_name
PROP_PrecNumOfCriticalPaths
s
prop_472_val
"1"
s
prop_473_name
PROP_FitterOptimization_xpla3
s
prop_473_val
"Density"
s
prop_474_name
PROP_xcpldFitDesPtermLmt_xbr
s
prop_474_val
"28"
s
prop_475_name
PROP_xcpldFitDesInReg_xbr
s
prop_475_val
"true"
s
prop_476_name
PROP_mapTimingMode
s
prop_476_val
"Non Timing Driven"
s
prop_477_name
PROP_xilxMapPackfactor
s
prop_477_val
"100"
s
prop_478_name
PROP_MapRetiming
s
prop_478_val
"false"
s
prop_479_name
PROP_MapEquivalentRegisterRemoval
s
prop_479_val
"true"
s
prop_47_name
PROP_SimModelRetainHierarchy
s
prop_47_val
"true"
s
prop_480_name
PROP_xilxPAReffortLevel
s
prop_480_val
"Standard"
s
prop_481_name
PROP_parTimingMode
s
prop_481_val
"Performance Evaluation"
s
prop_482_name
PROP_parGenAsyDlyRpt
s
prop_482_val
"false"
s
prop_483_name
PROP_parGenClkRegionRpt
s
prop_483_val
"false"
s
prop_484_name
PROP_parGenTimingRpt
s
prop_484_val
"true"
s
prop_485_name
PROP_parGenSimModel
s
prop_485_val
"false"
s
prop_486_name
PROP_parPowerReduction
s
prop_486_val
"false"
s
prop_487_name
PROP_mpprViewParRptForSelRslt
s
prop_487_val
""
s
prop_488_name
PROP_mpprViewPadRptForSelRslt
s
prop_488_val
""
s
prop_489_name
PROP_parMpprParIterations
s
prop_489_val
"3"
s
prop_48_name
PROP_CorgenRegenCore
s
prop_48_val
"Under Current Project Setting"
s
prop_490_name
PROP_parMpprResultsToSave
s
prop_490_val
""
s
prop_491_name
PROP_parMpprResultsDirectory
s
prop_491_val
""
s
prop_492_name
PROP_parMpprNodelistFile
s
prop_492_val
""
s
prop_493_name
PROP_xilxBitgCfg_GenOpt_DbgBitStr
s
prop_493_val
"false"
s
prop_494_name
PROP_xilxBitgReadBk_GenBitStr
s
prop_494_val
"false"
s
prop_495_name
PROP_xilxBitgCfg_GenOpt_LogicAllocFile
s
prop_495_val
"false"
s
prop_496_name
PROP_xilxBitgCfg_GenOpt_MaskFile
s
prop_496_val
"false"
s
prop_497_name
PROP_AceActiveName
s
prop_497_val
""
s
prop_498_name
PROP_impactConfigFileName
s
prop_498_val
""
s
prop_499_name
PROP_SynthRAMStyle
s
prop_499_val
"Auto"
s
prop_49_name
PROP_SynthOpt
s
prop_49_val
"Speed"
s
prop_4_name
PROP_StopImpView
s
prop_4_val
"AbstractSynthesis"
s
prop_500_name
PROP_xstROMStyle
s
prop_500_val
"Auto"
s
prop_501_name
PROP_SynthMuxStyle
s
prop_501_val
"Auto"
s
prop_502_name
PROP_xstMoveFirstFfStage
s
prop_502_val
"true"
s
prop_503_name
PROP_xstMoveLastFfStage
s
prop_503_val
"true"
s
prop_504_name
PROP_MapPowerReduction
s
prop_504_val
"false"
s
prop_505_name
PROPEXT_SynthFrequencySyn_virtex
s
prop_505_val
"0.0"
s
prop_506_name
PROP_MapEffortLevel
s
prop_506_val
"Medium"
s
prop_507_name
PROP_bitgen_Encrypt_Encrypt
s
prop_507_val
"false"
s
prop_508_name
PROP_MapPlacerCostTable
s
prop_508_val
"1"
s
prop_509_name
PROP_MapLogicOptimization
s
prop_509_val
"false"
s
prop_50_name
PROP_SynthOptEffort
s
prop_50_val
"Normal"
s
prop_510_name
PROP_MapRegDuplication
s
prop_510_val
"false"
s
prop_511_name
PROP_MapSmartGuideFileName
s
prop_511_val
"switch_to_led7_guide.ncd"
s
prop_512_name
PROP_ParSmartGuideFileName
s
prop_512_val
"switch_to_led7_guide.ncd"
s
prop_513_name
PROP_DevFamilyPMName
s
prop_513_val
"spartan3e"
s
prop_514_name
PROP_DevDevice
s
prop_514_val
"xc3s500e"
s
prop_515_name
PROP_CompxlibSimPath
s
prop_515_val
"Search in Path"
s
prop_516_name
PROP_CompxlibLang
s
prop_516_val
"VHDL"
s
prop_517_name
PROP_SimModelGenMultiHierFile
s
prop_517_val
"false"
s
prop_518_name
PROP_ISimSimulationRunTime_par_tb
s
prop_518_val
"1000 ns"
s
prop_519_name
PROP_ISimSimulationRunTime_par_tbw
s
prop_519_val
"1000 ns"
s
prop_51_name
PROP_xstUseSynthConstFile
s
prop_51_val
"true"
s
prop_520_name
PROP_ISimSimulationRunTime_behav_tb
s
prop_520_val
"1000 ns"
s
prop_521_name
PROP_ISimSimulationRunTime_behav_tbw
s
prop_521_val
"1000 ns"
s
prop_522_name
PROP_ISimVCDFileName_par_tb
s
prop_522_val
"xpower.vcd"
s
prop_523_name
PROP_ISimVCDFileName_par_tbw
s
prop_523_val
"xpower.vcd"
s
prop_524_name
PROP_xilxPARextraEffortLevel
s
prop_524_val
"None"
s
prop_525_name
PROP_parPowerActivityFile
s
prop_525_val
""
s
prop_526_name
PROP_CompxlibSmartModels
s
prop_526_val
"false"
s
prop_527_name
PROP_CompxlibUpdateIniForSmartModel
s
prop_527_val
"false"
s
prop_528_name
PROP_MapPowerActivityFile
s
prop_528_val
""
s
prop_529_name
PROP_bitgen_Encrypt_key0
s
prop_529_val
""
s
prop_52_name
PROP_xstLibSearchOrder
s
prop_52_val
""
s
prop_530_name
PROP_bitgen_Encrypt_key1
s
prop_530_val
""
s
prop_531_name
PROP_bitgen_Encrypt_key2
s
prop_531_val
""
s
prop_532_name
PROP_bitgen_Encrypt_key3
s
prop_532_val
""
s
prop_533_name
PROP_bitgen_Encrypt_key4
s
prop_533_val
""
s
prop_534_name
PROP_bitgen_Encrypt_key5
s
prop_534_val
""
s
prop_535_name
PROP_bitgen_Encrypt_keyFile
s
prop_535_val
""
s
prop_536_name
PROP_MapExtraEffort
s
prop_536_val
"None"
s
prop_537_name
PROP_xilxBitgCfg_GenOpt_ReadBack_virtex2
s
prop_537_val
"false"
s
prop_538_name
PROP_DevPackage
s
prop_538_val
"pq208"
s
prop_539_name
PROP_Synthesis_Tool
s
prop_539_val
"XST (VHDL/Verilog)"
s
prop_53_name
PROP_xstCase
s
prop_53_val
"Maintain"
s
prop_540_name
PROP_CompxlibUniSimLib
s
prop_540_val
"true"
s
prop_541_name
PROP_CompxlibUni9000Lib
s
prop_541_val
"true"
s
prop_542_name
PROP_xilxBitgReadBk_GenBitStr_virtex2
s
prop_542_val
"false"
s
prop_543_name
PROP_xilxBitgCfg_GenOpt_LogicAllocFile_virtex2
s
prop_543_val
"false"
s
prop_544_name
PROP_xilxBitgCfg_GenOpt_MaskFile_virtex2
s
prop_544_val
"false"
s
prop_545_name
PROP_DevSpeed
s
prop_545_val
"-4"
s
prop_546_name
PROP_PreferredLanguage
s
prop_546_val
"VHDL"
s
prop_547_name
PROP_HdlTemplateLang
s
prop_547_val
"VHDL"
s
prop_548_name
PROP_schFuncModelTargetLang
s
prop_548_val
"VHDL"
s
prop_549_name
PROP_schInstTempTargetLang
s
prop_549_val
"VHDL"
s
prop_54_name
PROP_xstWorkDir
s
prop_54_val
"./xst"
s
prop_550_name
PROP_hdlInstTempTargetLang
s
prop_550_val
"VHDL"
s
prop_551_name
PROP_ChangeDevSpeed
s
prop_551_val
"-4"
s
prop_552_name
PROP_SimModelTarget
s
prop_552_val
"VHDL"
s
prop_553_name
PROP_xawHdlSourceTargetLang
s
prop_553_val
"VHDL"
s
prop_554_name
PROP_tbwTestbenchTargetLang
s
prop_554_val
"VHDL"
s
prop_555_name
PROP_coregenFuncModelTargetLang
s
prop_555_val
"VHDL"
s
prop_556_name
PROP_xmpInstTempTargetLang
s
prop_556_val
"VHDL"
s
prop_557_name
PROP_sysgenInstTempTargetLang
s
prop_557_val
"VHDL"
s
prop_558_name
PROP_xilxPreTrceSpeed
s
prop_558_val
"-4"
s
prop_559_name
PROP_xilxPostTrceSpeed
s
prop_559_val
"-4"
s
prop_55_name
PROP_xstIniFile
s
prop_55_val
""
s
prop_560_name
PROP_HdlTemplateName
s
prop_560_val
"switch_to_led7.vhd"
s
prop_561_name
PROP_SimModelRenTopLevArchTo
s
prop_561_val
"Structure"
s
prop_562_name
PROP_SimModelGenArchOnly
s
prop_562_val
"false"
s
prop_563_name
PROP_SimModelOutputExtIdent
s
prop_563_val
"false"
s
prop_564_name
PROP_SimModelRenTopLevMod
s
prop_564_val
""
s
prop_565_name
PROP_SimModelIncUselibDirInVerilogFile
s
prop_565_val
"false"
s
prop_566_name
PROP_SimModelIncSdfAnnInVerilogFile
s
prop_566_val
"true"
s
prop_567_name
PROP_SimModelNoEscapeSignal
s
prop_567_val
"false"
s
prop_568_name
PROP_netgenPostXlateSimModelName
s
prop_568_val
"switch_to_led7_translate.vhd"
s
prop_569_name
PROP_netgenPostMapSimModelName
s
prop_569_val
"switch_to_led7_map.vhd"
s
prop_56_name
PROP_xstVerilog2001
s
prop_56_val
"true"
s
prop_570_name
PROP_netgenPostParSimModelName
s
prop_570_val
"switch_to_led7_timesim.vhd"
s
prop_571_name
PROP_bencherPostXlateTestbenchName
s
prop_571_val
"switch_to_led7.translate_vhw"
s
prop_572_name
PROP_bencherPostMapTestbenchName
s
prop_572_val
"switch_to_led7.map_vhw"
s
prop_573_name
PROP_bencherPostParTestbenchName
s
prop_573_val
"switch_to_led7.timesim_vhw"
s
prop_574_name
PROP_SimModelIncSimprimInVerilogFile
s
prop_574_val
"false"
s
prop_575_name
PROP_SimModelIncUnisimInVerilogFile
s
prop_575_val
"false"
s
prop_576_name
PROP_netgenPostSynthesisSimModelName
s
prop_576_val
"switch_to_led7_synthesis.vhd"
s
prop_577_name
PROP_SimModelAutoInsertGlblModuleInNetlist
s
prop_577_val
"true"
s
prop_578_name
PROP_PostXlateSimModelName
s
prop_578_val
"switch_to_led7_translate.vhd"
s
prop_579_name
PROP_PostMapSimModelName
s
prop_579_val
"switch_to_led7_map.vhd"
s
prop_57_name
PROP_xstVeriIncludeDir_Global
s
prop_57_val
""
s
prop_580_name
PROP_PostParSimModelName
s
prop_580_val
"switch_to_led7_timesim.vhd"
s
prop_581_name
PROP_PostParSimModelName
s
prop_581_val
"switch_to_led7_timesim.vhd"
s
prop_582_name
PROP_PostParSimModelName
s
prop_582_val
"switch_to_led7_timesim.vhd"
s
prop_583_name
PROP_tbwPostXlateTestbenchName
s
prop_583_val
"switch_to_led7.translate_vhw"
s
prop_584_name
PROP_tbwPostMapTestbenchName
s
prop_584_val
"switch_to_led7.map_vhw"
s
prop_585_name
PROP_tbwPostParTestbenchName
s
prop_585_val
"switch_to_led7.timesim_vhw"
s
prop_586_name
PROP_tbwPostParTestbenchName
s
prop_586_val
"switch_to_led7.timesim_vhw"
s
prop_587_name
PROP_PostSynthesisSimModelName
s
prop_587_val
"switch_to_led7_synthesis.vhd"
s
prop_588_name
PROP_SimModelBringOutGtsNetAsAPort
s
prop_588_val
"false"
s
prop_589_name
PROP_SimModelBringOutGsrNetAsAPort
s
prop_589_val
"false"
s
prop_58_name
PROP_xstUserCompileList
s
prop_58_val
""
s
prop_590_name
PROP_netgenRenameTopLevEntTo
s
prop_590_val
"switch_to_led7"
s
prop_591_name
PROP_SimModelPathUsedInSdfAnn
s
prop_591_val
"Default"
s
prop_59_name
PROP_xstGenericsParameters
s
prop_59_val
""
s
prop_5_name
PROP_HierarchicalProjectType
s
prop_5_val
"N/A"
s
prop_60_name
PROP_xstVerilogMacros
s
prop_60_val
""
s
prop_61_name
PROP_xst_otherCmdLineOptions
s
prop_61_val
""
s
prop_62_name
PROP_xstGenerateRTLNetlist
s
prop_62_val
"Yes"
s
prop_63_name
PROP_xstHierarchySeparator
s
prop_63_val
"/"
s
prop_64_name
PROP_xstBusDelimiter
s
prop_64_val
"<>"
s
prop_65_name
PROP_SynthFsmEncode
s
prop_65_val
"Auto"
s
prop_66_name
PROP_SynthCaseImplStyle
s
prop_66_val
"None"
s
prop_67_name
PROP_SynthResSharing
s
prop_67_val
"true"
s
prop_68_name
PROP_SynthExtractMux
s
prop_68_val
"Yes"
s
prop_69_name
PROP_xilxSynthAddIObuf
s
prop_69_val
"true"
s
prop_6_name
PROP_ProjectGeneratorType
s
prop_6_val
"ProjNav"
s
prop_70_name
PROP_xstEquivRegRemoval
s
prop_70_val
"true"
s
prop_71_name
PROP_ISimUutInstName
s
prop_71_val
"UUT"
s
prop_72_name
PROP_ISimUseCustomSimCmdFile_par_tb
s
prop_72_val
"false"
s
prop_73_name
PROP_ISimUseCustomSimCmdFile_par_tbw
s
prop_73_val
"false"
s
prop_74_name
PROP_ISimUseCustomSimCmdFile_behav_tb
s
prop_74_val
"false"
s
prop_75_name
PROP_ISimUseCustomSimCmdFile_behav_tbw
s
prop_75_val
"false"
s
prop_76_name
PROP_ISimUseCustomSimCmdFile_gen_tbw
s
prop_76_val
"false"
s
prop_77_name
PROP_ISimUseCustomSimCmdFile_launch
s
prop_77_val
"false"
s
prop_78_name
PROP_isimIncreCompilation
s
prop_78_val
"true"
s
prop_79_name
PROP_isimCompileForHdlDebug
s
prop_79_val
"true"
s
prop_7_name
PROP_Parse_Target
s
prop_7_val
"synthesis"
s
prop_80_name
PROP_ISimSDFTimingToBeRead
s
prop_80_val
"Setup Time"
s
prop_81_name
PROP_isimValueRangeCheck
s
prop_81_val
"false"
s
prop_82_name
PROP_isimSpecifySearchDirectory
s
prop_82_val
""
s
prop_83_name
PROP_ISimSpecifySearchDirectoryChkSyntax
s
prop_83_val
""
s
prop_84_name
PROP_isimSpecifyDefMacroAndValue
s
prop_84_val
""
s
prop_85_name
PROP_ISimSpecifyDefMacroAndValueChkSyntax
s
prop_85_val
""
s
prop_86_name
PROP_ISimLibSearchOrderFile
s
prop_86_val
""
s
prop_87_name
PROP_ISimUseCustomCompilationOrder
s
prop_87_val
"false"
s
prop_88_name
PROP_ISimOtherCompilerOptions_behav
s
prop_88_val
""
s
prop_89_name
PROP_ISimOtherCompilerOptions_par
s
prop_89_val
""
s
prop_8_name
PROP_Top_Level_Module_Type
s
prop_8_val
"HDL"
s
prop_90_name
PROP_ISimOtherCompilerOptions_fit
s
prop_90_val
""
s
prop_91_name
PROP_DefaultTBName
s
prop_91_val
"Default"
s
prop_92_name
PROP_ibiswriterShowAllModels
s
prop_92_val
"false"
s
prop_93_name
PROP_ImpactProjectFile
s
prop_93_val
"Default"
s
prop_94_name
PROP_ngdbuild_otherCmdLineOptions
s
prop_94_val
""
s
prop_95_name
PROP_SynthXORCollapse
s
prop_95_val
"true"
s
prop_96_name
PROP_xilxNgdbld_AUL
s
prop_96_val
"false"
s
prop_97_name
PROP_xilxNgdbldMacro
s
prop_97_val
""
s
prop_98_name
PROP_xilxSynthKeepHierarchy
s
prop_98_val
"No"
s
prop_99_name
PROP_xstNetlistHierarchy
s
prop_99_val
"As Optimized"
s
prop_9_name
PROP_SynthTop
s
prop_9_val
"Architecture|switch_to_led7|Behavioral"
s

						