switch_to_led7.par
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上传日期：2022-07-03
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文件大小：7k
- Release 10.1.03 par K.39 (nt)
Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
THTFCOMPUTER:: Wed May 05 21:43:37 2010
par -w -intstyle ise -ol std -t 1 switch_to_led7_map.ncd switch_to_led7.ncd
- switch_to_led7.pcf
Constraints file: switch_to_led7.pcf.
Loading device for application Rf_Device from file '3s500e.nph' in environment D:Xilinx10.1ISE.
"switch_to_led7" is an NCD, version 3.2, device xc3s500e, package pq208, speed -4
Initializing temperature to 85.000 Celsius. (default - Range: -40.000 to 100.000 Celsius)
Initializing voltage to 1.140 Volts. (default - Range: 1.140 to 1.320 Volts)
INFO:Par:282 - No user timing constraints were detected or you have set the option to ignore timing constraints ("par
- -x"). Place and Route will run in "Performance Evaluation Mode" to automatically improve the performance of all
- internal clocks in this design. The PAR timing summary will list the performance achieved for each clock. Note: For
- the fastest runtime, set the effort level to "std". For best performance, set the effort level to "high". For a
- balance between the fastest runtime and best performance, set the effort level to "med".
Device speed data version: "PRODUCTION 1.27 2008-01-09".
Design Summary Report:
Number of External IOBs 21 out of 158 13%
Number of External Input IOBs 9
Number of External Input IBUFs 9
Number of LOCed External Input IBUFs 9 out of 9 100%
Number of External Output IOBs 12
Number of External Output IOBs 12
Number of LOCed External Output IOBs 12 out of 12 100%
Number of External Bidir IOBs 0
Number of BUFGMUXs 2 out of 24 8%
Number of RAMB16s 1 out of 20 5%
Number of Slices 154 out of 4656 3%
Number of SLICEMs 34 out of 2328 1%
Overall effort level (-ol): Standard
Placer effort level (-pl): High
Placer cost table entry (-t): 1
Router effort level (-rl): Standard
Starting Placer
Phase 1.1
Phase 1.1 (Checksum:6158) REAL time: 2 secs
Phase 2.7
Phase 2.7 (Checksum:6158) REAL time: 2 secs
Phase 3.31
Phase 3.31 (Checksum:6158) REAL time: 2 secs
Phase 4.2
.
Phase 4.2 (Checksum:8196) REAL time: 2 secs
Phase 5.30
Phase 5.30 (Checksum:8196) REAL time: 2 secs
Phase 6.8
............
............
.......
...........................
...............................
...............................................
Phase 6.8 (Checksum:45652) REAL time: 7 secs
Phase 7.5
Phase 7.5 (Checksum:45652) REAL time: 7 secs
Phase 8.18
Phase 8.18 (Checksum:42770) REAL time: 8 secs
Phase 9.5
Phase 9.5 (Checksum:42770) REAL time: 8 secs
REAL time consumed by placer: 8 secs
CPU time consumed by placer: 8 secs
Writing design to file switch_to_led7.ncd
Total REAL time to Placer completion: 8 secs
Total CPU time to Placer completion: 8 secs
Starting Router
Phase 1: 1213 unrouted; REAL time: 11 secs
Phase 2: 1105 unrouted; REAL time: 11 secs
Phase 3: 222 unrouted; REAL time: 11 secs
Phase 4: 222 unrouted; (51749) REAL time: 11 secs
Phase 5: 221 unrouted; (0) REAL time: 11 secs
Phase 6: 0 unrouted; (0) REAL time: 12 secs
Phase 7: 0 unrouted; (0) REAL time: 12 secs
Phase 8: 0 unrouted; (0) REAL time: 12 secs
Phase 9: 0 unrouted; (0) REAL time: 12 secs
Phase 10: 0 unrouted; (0) REAL time: 12 secs
Total REAL time to Router completion: 12 secs
Total CPU time to Router completion: 12 secs
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Generating "PAR" statistics.
**************************
Generating Clock Report
**************************
+---------------------+--------------+------+------+------------+-------------+
| Clock Net | Resource |Locked|Fanout|Net Skew(ns)|Max Delay(ns)|
+---------------------+--------------+------+------+------------+-------------+
| clk_in_BUFGP | BUFGMUX_X2Y1| No | 78 | 0.062 | 0.181 |
+---------------------+--------------+------+------+------------+-------------+
| write_strobe | BUFGMUX_X2Y0| No | 16 | 0.040 | 0.188 |
+---------------------+--------------+------+------+------------+-------------+
|Inst_divid_200/clk_t | | | | | |
| mp | Local| | 3 | 0.000 | 1.763 |
+---------------------+--------------+------+------+------------+-------------+
* Net Skew is the difference between the minimum and maximum routing
only delays for the net. Note this is different from Clock Skew which
is reported in TRCE timing report. Clock Skew is the difference between
the minimum and maximum path delays which includes logic delays.
Timing Score: 0
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the constraint does not cover any paths or that it has no
- requested value.
Asterisk (*) preceding a constraint indicates it was not met.
This may be due to a setup or hold violation.
------------------------------------------------------------------------------------------------------
Constraint | Check | Worst Case | Best Case | Timing | Timing
| | Slack | Achievable | Errors | Score
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net clk | SETUP | N/A| 13.912ns| N/A| 0
_in_BUFGP | HOLD | 0.773ns| | 0| 0
------------------------------------------------------------------------------------------------------
Autotimespec constraint for clock net Ins | SETUP | N/A| 2.282ns| N/A| 0
t_divid_200/clk_tmp | HOLD | 1.192ns| | 0| 0
------------------------------------------------------------------------------------------------------
All constraints were met.
INFO:Timing:2761 - N/A entries in the Constraints list may indicate that the
constraint does not cover any paths or that it has no requested value.
Generating Pad Report.
All signals are completely routed.
Total REAL time to PAR completion: 13 secs
Total CPU time to PAR completion: 13 secs
Peak Memory Usage: 142 MB
Placement: Completed - No errors found.
Routing: Completed - No errors found.
Number of error messages: 0
Number of warning messages: 0
Number of info messages: 2
Writing design to file switch_to_led7.ncd
PAR done!
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