switch_to_led7.twr
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上传日期：2022-07-03
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文件大小：3k
- --------------------------------------------------------------------------------
- Release 10.1.03 Trace (nt)
- Copyright (c) 1995-2008 Xilinx, Inc. All rights reserved.
- D:Xilinx10.1ISEbinntunwrappedtrce.exe -ise
- F:/lilihua/switch_to_led7/switch_to_led7.ise -intstyle ise -v 3 -s 4 -xml
- switch_to_led7 switch_to_led7.ncd -o switch_to_led7.twr switch_to_led7.pcf -ucf
- switch_to_led7.ucf
- Design file: switch_to_led7.ncd
- Physical constraint file: switch_to_led7.pcf
- Device,package,speed: xc3s500e,pq208,-4 (PRODUCTION 1.27 2008-01-09)
- Report level: verbose report
- Environment Variable Effect
- -------------------- ------
- NONE No environment variables were set
- --------------------------------------------------------------------------------
- INFO:Timing:2698 - No timing constraints found, doing default enumeration.
- INFO:Timing:2752 - To get complete path coverage, use the unconstrained paths
- option. All paths that are not constrained will be reported in the
- unconstrained paths section(s) of the report.
- INFO:Timing:3339 - The clock-to-out numbers in this timing report are based on
- a 50 Ohm transmission line loading model. For the details of this model,
- and for more information on accounting for different loading conditions,
- please see the device datasheet.
- Data Sheet report:
- -----------------
- All values displayed in nanoseconds (ns)
- Setup/Hold to clock clk_in
- ------------+------------+------------+------------------+--------+
- | Setup to | Hold to | | Clock |
- Source | clk (edge) | clk (edge) |Internal Clock(s) | Phase |
- ------------+------------+------------+------------------+--------+
- switch_in<0>| 5.715(R)| -1.699(R)|clk_in_BUFGP | 0.000|
- switch_in<1>| 6.159(R)| -2.983(R)|clk_in_BUFGP | 0.000|
- switch_in<2>| 5.282(R)| -1.582(R)|clk_in_BUFGP | 0.000|
- switch_in<3>| 5.030(R)| -1.765(R)|clk_in_BUFGP | 0.000|
- switch_in<4>| 5.877(R)| -2.339(R)|clk_in_BUFGP | 0.000|
- switch_in<5>| 5.581(R)| -2.685(R)|clk_in_BUFGP | 0.000|
- switch_in<6>| 6.607(R)| -2.160(R)|clk_in_BUFGP | 0.000|
- switch_in<7>| 6.661(R)| -2.597(R)|clk_in_BUFGP | 0.000|
- ------------+------------+------------+------------------+--------+
- Clock to Setup on destination clock clk_in
- ---------------+---------+---------+---------+---------+
- | Src:Rise| Src:Fall| Src:Rise| Src:Fall|
- Source Clock |Dest:Rise|Dest:Rise|Dest:Fall|Dest:Fall|
- ---------------+---------+---------+---------+---------+
- clk_in | 13.912| | | |
- ---------------+---------+---------+---------+---------+
- Analysis completed Wed May 05 21:43:55 2010
- --------------------------------------------------------------------------------
- Trace Settings:
- -------------------------
- Trace Settings
- Peak Memory Usage: 101 MB
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