switch_to_led7_map.map
上传用户：hbxtsdjs
上传日期：2022-07-03
资源大小：753k
文件大小：3k
- Release 10.1.03 Map K.39 (nt)
Xilinx Map Application Log File for Design 'switch_to_led7'
Design Information
------------------
Command Line : map -ise F:/lilihua/switch_to_led7/switch_to_led7.ise -intstyle
- ise -p xc3s500e-pq208-4 -cm area -pr off -k 4 -c 100 -o switch_to_led7_map.ncd
- switch_to_led7.ngd switch_to_led7.pcf
Target Device : xc3s500e
Target Package : pq208
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.46.12.2 $
Mapped Date : Wed May 05 21:40:04 2010
Mapping design into LUTs...
Running directed packing...
Running delay-based LUT packing...
Running related packing...
Design Summary
--------------
Design Summary:
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 120 out of 9,312 1%
Number of 4 input LUTs: 239 out of 9,312 2%
Logic Distribution:
Number of occupied Slices: 154 out of 4,656 3%
Number of Slices containing only related logic: 154 out of 154 100%
Number of Slices containing unrelated logic: 0 out of 154 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 256 out of 9,312 2%
Number used as logic: 171
Number used as a route-thru: 17
Number used for Dual Port RAMs: 16
(Two LUTs used per Dual Port RAM)
Number used for 32x1 RAMs: 52
(Two LUTs used per 32x1 RAM)
Number of bonded IOBs: 21 out of 158 13%
Number of RAMB16s: 1 out of 20 5%
Number of BUFGMUXs: 2 out of 24 8%
Peak Memory Usage: 158 MB
Total REAL time to MAP completion: 3 secs
Total CPU time to MAP completion: 2 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Mapping completed.
See MAP report file "switch_to_led7_map.mrp" for details.
English
