switch_to_led7_map.mrp
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上传日期：2022-07-03
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- Release 10.1.03 Map K.39 (nt)
Xilinx Mapping Report File for Design 'switch_to_led7'
Design Information
------------------
Command Line : map -ise F:/lilihua/switch_to_led7/switch_to_led7.ise -intstyle
- ise -p xc3s500e-pq208-4 -cm area -pr off -k 4 -c 100 -o switch_to_led7_map.ncd
- switch_to_led7.ngd switch_to_led7.pcf
Target Device : xc3s500e
Target Package : pq208
Target Speed : -4
Mapper Version : spartan3e -- $Revision: 1.46.12.2 $
Mapped Date : Wed May 05 21:40:04 2010
Design Summary
--------------
Number of errors: 0
Number of warnings: 0
Logic Utilization:
Number of Slice Flip Flops: 120 out of 9,312 1%
Number of 4 input LUTs: 239 out of 9,312 2%
Logic Distribution:
Number of occupied Slices: 154 out of 4,656 3%
Number of Slices containing only related logic: 154 out of 154 100%
Number of Slices containing unrelated logic: 0 out of 154 0%
*See NOTES below for an explanation of the effects of unrelated logic.
Total Number of 4 input LUTs: 256 out of 9,312 2%
Number used as logic: 171
Number used as a route-thru: 17
Number used for Dual Port RAMs: 16
(Two LUTs used per Dual Port RAM)
Number used for 32x1 RAMs: 52
(Two LUTs used per 32x1 RAM)
Number of bonded IOBs: 21 out of 158 13%
Number of RAMB16s: 1 out of 20 5%
Number of BUFGMUXs: 2 out of 24 8%
Peak Memory Usage: 158 MB
Total REAL time to MAP completion: 3 secs
Total CPU time to MAP completion: 2 secs
NOTES:
Related logic is defined as being logic that shares connectivity - e.g. two
LUTs are "related" if they share common inputs. When assembling slices,
Map gives priority to combine logic that is related. Doing so results in
the best timing performance.
Unrelated logic shares no connectivity. Map will only begin packing
unrelated logic into a slice once 99% of the slices are occupied through
related logic packing.
Note that once logic distribution reaches the 99% level through related
logic packing, this does not mean the device is completely utilized.
Unrelated logic packing will then begin, continuing until all usable LUTs
and FFs are occupied. Depending on your timing budget, increased levels of
unrelated logic packing may adversely affect the overall timing performance
of your design.
Table of Contents
-----------------
Section 1 - Errors
Section 2 - Warnings
Section 3 - Informational
Section 4 - Removed Logic Summary
Section 5 - Removed Logic
Section 6 - IOB Properties
Section 7 - RPMs
Section 8 - Guide Report
Section 9 - Area Group and Partition Summary
Section 10 - Modular Design Summary
Section 11 - Timing Report
Section 12 - Configuration String Information
Section 13 - Control Set Information
Section 14 - Utilization by Hierarchy
Section 1 - Errors
------------------
Section 2 - Warnings
--------------------
Section 3 - Informational
-------------------------
INFO:MapLib:562 - No environment variables are currently set.
INFO:LIT:244 - All of the single ended outputs in this design are using slew
- rate limited output drivers. The delay on speed critical single ended outputs
- can be dramatically reduced by designating them as fast outputs.
Section 4 - Removed Logic Summary
---------------------------------
7 block(s) removed
9 block(s) optimized away
8 signal(s) removed
Section 5 - Removed Logic
-------------------------
The trimmed logic report below shows the logic removed from your design due to
- sourceless or loadless signals, and VCC or ground connections. If the removal
- of a signal or symbol results in the subsequent removal of an additional signal
- or symbol, the message explaining that second removal will be indented. This
- indentation will be repeated as a chain of related logic is removed.
To quickly locate the original cause for the removal of a chain of logic, look
- above the place where that logic is listed in the trimming report, then locate
- the lines that are least indented (begin at the leftmost edge).
Loadless block "Inst_kcpsm3/read_strobe_flop" (SFF) removed.
The signal "Inst_kcpsm3/read_active" is loadless and has been removed.
Loadless block "Inst_kcpsm3/read_active_lut" (ROM) removed.
The trimmed logic reported below is either:
1. part of a cycle
2. part of disabled logic
3. a side-effect of other trimmed logic
The signal "Inst_kcpsm3/int_enable" is unused and has been removed.
Unused block "Inst_kcpsm3/int_enable_flop" (SFF) removed.
The signal "Inst_kcpsm3/int_update_enable" is unused and has been removed.
Unused block "Inst_kcpsm3/int_update_lut" (ROM) removed.
The signal "Inst_kcpsm3/int_enable_value" is unused and has been removed.
Unused block "Inst_kcpsm3/int_value_lut" (ROM) removed.
The signal "Inst_kcpsm3/interrupt_ack" is unused and has been removed.
Unused block "Inst_kcpsm3/ack_flop" (FF) removed.
The signal "Inst_kcpsm3/int_pulse" is unused and has been removed.
The signal "Inst_kcpsm3/not_active_interrupt" is unused and has been removed.
The signal "Inst_kcpsm3/sel_shadow_carry" is unused and has been removed.
Unused block "Inst_kcpsm3/sel_shadow_carry_lut" (ROM) removed.
Optimized Block(s):
TYPE BLOCK
FDR Inst_kcpsm3/int_capture_flop
optimized to 0
FDR Inst_kcpsm3/int_flop
optimized to 0
LUT4 Inst_kcpsm3/int_pulse_lut
FDE Inst_kcpsm3/shadow_carry_flop
optimized to 0
FDE Inst_kcpsm3/shadow_zero_flop
optimized to 0
INV Inst_kcpsm3/stack_count_inv
GND XST_GND
VCC XST_VCC
MUXCY Inst_kcpsm3/sel_shadow_muxcy
To enable printing of redundant blocks removed and signals merged, set the
- detailed map report option and rerun map.
Section 6 - IOB Properties
--------------------------
+-------------------------------------------------------------------------------------------------------------------------------------------------+
| IOB Name | Type | Direction | IO Standard | Drive | Slew | Reg (s) | Resistor | IOB |
| | | | | Strength | Rate | | | Delay |
+-------------------------------------------------------------------------------------------------------------------------------------------------+
| clk_in | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| led7<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| led7<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| led7<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| led7<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| led7<4> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| led7<5> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| led7<6> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| led7<7> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| sel<0> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| sel<1> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| sel<2> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| sel<3> | IOB | OUTPUT | LVCMOS25 | 12 | SLOW | | | 0 / 0 |
| switch_in<0> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| switch_in<1> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| switch_in<2> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| switch_in<3> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| switch_in<4> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| switch_in<5> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| switch_in<6> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
| switch_in<7> | IBUF | INPUT | LVCMOS25 | | | | | 0 / 0 |
+-------------------------------------------------------------------------------------------------------------------------------------------------+
Section 7 - RPMs
----------------
Section 8 - Guide Report
------------------------
Guide not run on this design.
Section 9 - Area Group and Partition Summary
--------------------------------------------
Partition Implementation Status
-------------------------------
No Partitions were found in this design.
-------------------------------
Area Group Information
----------------------
No area groups were found in this design.
----------------------
Section 10 - Modular Design Summary
-----------------------------------
Modular Design not used for this design.
Section 11 - Timing Report
--------------------------
This design was not run using timing mode.
Section 12 - Configuration String Details
-----------------------------------------
Use the "-detail" map option to print out Configuration Strings
Section 13 - Control Set Information
------------------------------------
No control set information for this architecture.
Section 14 - Utilization by Hierarchy
-------------------------------------
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| Module | Partition | Slices | Slice Reg | LUTs | LUTRAM | BRAM | MULT18X18 | BUFG | DCM | Full Hierarchical Name |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
| switch_to_led7/ | | 45/188 | 0/120 | 42/256 | 0/68 | 0/1 | 0/0 | 2/2 | 0/0 | switch_to_led7 |
| +Inst_LED_7scan | | 23/23 | 2/2 | 39/39 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | switch_to_led7/Inst_LED_7scan |
| +Inst_Latch0 | | 4/4 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | switch_to_led7/Inst_Latch0 |
| +Inst_Latch1 | | 4/4 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | switch_to_led7/Inst_Latch1 |
| +Inst_Latch2 | | 4/4 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | switch_to_led7/Inst_Latch2 |
| +Inst_Latch3 | | 4/4 | 8/8 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | switch_to_led7/Inst_Latch3 |
| +Inst_divid_200 | | 13/13 | 17/17 | 6/6 | 0/0 | 0/0 | 0/0 | 0/0 | 0/0 | switch_to_led7/Inst_divid_200 |
| +Inst_kcpsm3 | | 91/91 | 69/69 | 169/169 | 68/68 | 0/0 | 0/0 | 0/0 | 0/0 | switch_to_led7/Inst_kcpsm3 |
| +Inst_sw_led | | 0/0 | 0/0 | 0/0 | 0/0 | 1/1 | 0/0 | 0/0 | 0/0 | switch_to_led7/Inst_sw_led |
+------------------------------------------------------------------------------------------------------------------------------------------------------------------------+
* Slices can be packed with basic elements from multiple hierarchies.
Therefore, a slice will be counted in every hierarchical module
that each of its packed basic elements belong to.
** For each column, there are two numbers reported <A>/<B>.
<A> is the number of elements that belong to that specific hierarchical module.
<B> is the total number of elements from that hierarchical module and any lower level
hierarchical modules below.
*** The LUTRAM column counts all LUTs used as memory including RAM, ROM, and shift registers.
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