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at91sam7se-ek-sdram.ini：源码内容
							// ----------------------------------------------------------------------------
//         ATMEL Microcontroller Software Support 
// ----------------------------------------------------------------------------
// Copyright (c) 2008, Atmel Corporation
//
// All rights reserved.
//
// Redistribution and use in source and binary forms, with or without
// modification, are permitted provided that the following conditions are met:
//
// - Redistributions of source code must retain the above copyright notice,
// this list of conditions and the disclaimer below.
//
// Atmel's name may not be used to endorse or promote products derived from
// this software without specific prior written permission.
//
// DISCLAIMER: THIS SOFTWARE IS PROVIDED BY ATMEL "AS IS" AND ANY EXPRESS OR
// IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF
// MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT ARE
// DISCLAIMED. IN NO EVENT SHALL ATMEL BE LIABLE FOR ANY DIRECT, INDIRECT,
// INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
// LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE, DATA,
// OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF
// LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT (INCLUDING
// NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
// ----------------------------------------------------------------------------
//----------------------------------------------------------------------------
//  File Name           : at91sam7se-ek-sdram.ini
//  Object              : Generic Macro File for KEIL
//----------------------------------------------------------------------------
//----------------------------------------------------------------------------
// MapRAMAt0()
// Function description: Maps RAM at 0.
//----------------------------------------------------------------------------
FUNC void MapRAMAt0(){
    printf ("Changing mapping: RAM mapped to 0 n");
    _WDWORD(0xFFFFFF00,0x00000001);
}
//----------------------------------------------------------------------------
// initSDRAM()
// Function description: Set SDRAM for works at 48 MHz
//----------------------------------------------------------------------------
FUNC void initSDRAM(){
//  Enable clock on EBI pios
//  pPMC->PMC_PCER = AT91C_EBI_CS1A_SDRAMC;
//  PMC_PCER        ((AT91_REG *)  0xFFFFFC10) // (PMC_PCER) Peripheral Clock Enable Register
    _WDWORD(0xFFFFFC10,0x0000001C);
//*  Configure PIOs
    _WDWORD(0xFFFFF470,0x00000000);
    _WDWORD(0xFFFFF474,0x3F800000);
    _WDWORD(0xFFFFF404,0x3F800000);
    _WDWORD(0xFFFFF670,0x00000000);	
    _WDWORD(0xFFFFF674,0x0003FFFF);	
    _WDWORD(0xFFFFF604,0x0003FFFF);	
    _WDWORD(0xFFFFF870,0x0000FFFF);
    _WDWORD(0xFFFFF874,0x00000000);
    _WDWORD(0xFFFFF804,0x0000FFFF);
//  Configure EBI Chip select	
//  pCCFG->CCFG_EBICSA |= AT91C_EBI_CS1A_SDRAMC;
//  AT91C_CCFG_EBICSA ((AT91_REG *) 	0xFFFFEF1C) // (CCFG)  EBI Chip Select Assignement Register
    _WDWORD(0xFFFFFF80,0x02);
//  psdrc->SDRC_CR =  AT91C_SDRAMC_NC_9  | AT91C_SDRAMC_NR_13 | AT91C_SDRAMC_CAS_2 |
//  AT91C_SDRAMC_NB_4_BANKS | AT91C_SDRAMC_TWR_2 | AT91C_SDRAMC_TRC_4 |
//  AT91C_SDRAMC_TRP_2 | AT91C_SDRAMC_TRCD_2 | AT91C_SDRAMC_TRAS_3 | AT91C_SDRAMC_TXSR_4 ;
    _WDWORD(0xFFFFFFB8,0x21922159);
    
    _sleep_(20);
//	psdrc->SDRC_MR	= 0x00000011;		    // NOP CMD
    _WDWORD(0xFFFFFFB0,0x00000011);
    
// *AT91C_SDRAM	= 0x00000000;
    _WDWORD(0x20000000,0x00000000);
//	psdrc->SDRC_MR	= 0x00000012;			// Perform PRCHG
    _WDWORD(0xFFFFFFB0,0x00000012);
    
//	*AT91C_SDRAM	= 0x00000000;
    _WDWORD(0x20000000,0x00000000);
    _sleep_(20);
//	psdrc->SDRC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
    _WDWORD(0xFFFFFFB0,0x0000014);
    _WDWORD(0x20000000,0x00000000);
//	psdrc->SDRC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
    _WDWORD(0xFFFFFFB0,0x0000014);
    _WDWORD(0x20000000,0x00000000);
//	psdrc->SDRC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
    _WDWORD(0xFFFFFFB0,0x0000014);
    _WDWORD(0x20000000,0x00000000);
//	psdrc->SDRC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
    _WDWORD(0xFFFFFFB0,0x0000014);
    _WDWORD(0x20000000,0x00000000);
//	psdrc->SDRC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
    _WDWORD(0xFFFFFFB0,0x0000014);
    _WDWORD(0x20000000,0x00000000);
//	psdrc->SDRC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
    _WDWORD(0xFFFFFFB0,0x0000014);
    _WDWORD(0x20000000,0x00000000);
//	psdrc->SDRC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
    _WDWORD(0xFFFFFFB0,0x0000014);
    _WDWORD(0x20000000,0x00000000);
//*	psdrc->SDRC_MR	= AT91C_SDRAMC_MODE_RFSH_CMD;		// Set 1st CBR
    _WDWORD(0xFFFFFFB0,0x0000014);
    _WDWORD(0x20000000,0x00000000);
//	psdrc->SDRC_MR	= AT91C_SDRAMC_MODE_LMR_CMD;		// Set LMR operation
    _WDWORD(0xFFFFFFB0,0x00000013);
//	*(AT91C_SDRAM+0x20)	= 0xcafedede;		// Perform LMR burst=1, lat=2
    _WDWORD(0x20000020,0xCAFEDEDE);
//	psdrc->SDRC_MR	= AT91C_SDRAMC_MODE_NORMAL_CMD;		// Set Normal mode
    _WDWORD(0xFFFFFFB0,0x00000010);
//	psdrc->SDRC_TR	= (AT91C_MASTER_CLOCK * 8)/1000000;				// Set Refresh Timer 390 for 25MHz (TR= 15.6 * F )
//									               // (F : system clock freq. MHz
    _WDWORD(0xFFFFFFB4,0x00000150);
//	*AT91C_SDRAM	= 0x00000000;	// Perform Normal mode
    _WDWORD(0x20000000,0x00000000);
    printf ("------------------------------- SDRAM Done at 48 MHz -------------------------------n");
}
//----------------------------------------------------------------------------
// InitRSTC()
// Function description
//   Initializes the RSTC (Reset controller).
//   This makes sense since the default is to not allow user resets, which makes it impossible to
//   apply a second RESET via J-Link
//----------------------------------------------------------------------------
FUNC void InitRSTC() {
    _WDWORD(0xFFFFFD08,0xA5000001);    // Allow user reset
}
//----------------------------------------------------------------------------
// InitPLL()
// Function description
//   Initializes the PMC.
//   1. Enable the Main Oscillator
//   2. Configure PLL to 96MHz
//   3. Switch Master Clock (MCK) on PLL/2 = 48MHz
//----------------------------------------------------------------------------
FUNC void InitPLL() {
    printf( "Set Main Oscillator n");
    _WDWORD(0xFFFFFC20,0x00004001);    // MOSC
    while( !(_RDWORD(0xFFFFFC68) & 0x1)  );
_sleep_(100);                       // Wait for stable Main Oscillator
    printf( "Set PLL to 96MHz n");
    _WDWORD(0xFFFFFC2C,0x1048100e);    // LOCK
    while( !(_RDWORD(0xFFFFFC68) & 0x4)  );
_sleep_(100);                       // Wait for stable Main Oscillator
    printf( "Set Master Clock to 48MHz n ");
    _WDWORD(0xFFFFFC30,0x00000004);    // MCKRDY
    while( !(_RDWORD(0xFFFFFC68) & 0x8)  );
_sleep_(100);                       // Wait for stable Main Oscillator    
    _WDWORD(0xFFFFFC30,0x00000007);    // MCKRDY
    while( !(_RDWORD(0xFFFFFC68) & 0x8)  );
_sleep_(100);                       // Wait for stable Main Oscillator    
}
InitPLL();                         // Allow to load Code at JTAG Full Speed
initSDRAM();                       // Init SDRAM before load
MapRAMAt0();                       // Remap SRAM to address 0
InitRSTC();                        // Enable User Reset to allow execUserReset() execution
LOAD at91sam7se256-sdram\at91sam7se256-sdram.axf INCREMENTAL
//LOAD at91sam7se512-sdram\at91sam7se512-sdram.axf INCREMENTAL
//LOAD at91sam7se32-sdram\at91sam7se32-sdram.axf INCREMENTAL
PC = 0x20000000;
g,main

						