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PLX_Regs.cs
资源名称：PLX_code_dotnet_10.rar　[点击查看]
上传用户：huajielb
上传日期：2022-07-29
资源大小：626k
文件大小：22k
源码类别：

驱动编程

开发平台：

Visual C++

PLX_Regs.cs：源码内容
  1. using System;
  3. using Jungo.wdapi_dotnet;
  4. using DWORD = System.UInt32;
  6. namespace Jungo.plx_lib
  7. {
  8.     public struct WDC_REG
  9.     {
  10.         public DWORD dwAddrSpace;       /* Number of address space in which the register resides */
  11.         /* For PCI configuration registers, use WDC_AD_CFG_SPACE */
  12.         public DWORD dwOffset;          /* Offset of the register in the dwAddrSpace address space */
  13.         public DWORD dwSize;            /* Register's size (in bytes) */
  14.         public WDC_DIRECTION direction; /* Read/write access mode - see WDC_DIRECTION options */
  15.         public string  sName;           /* Register's name */
  16.         public string  sDesc;           /* Register's description */
  18.         public WDC_REG(DWORD _dwAddrSpace, DWORD _dwOffset, DWORD _dwSize, 
  19.             WDC_DIRECTION _direction, string  _sName, string _sDesc)
  20.         {
  21.             dwAddrSpace = _dwAddrSpace;
  22.             dwOffset = _dwOffset;
  23.             dwSize = _dwSize;
  24.             direction = _direction;
  25.             sName = _sName;
  26.             sDesc = _sDesc;
  27.         }
  28.     };
  30.     public class PLX_Regs
  31.     {
  32.         private const uint WDC_AD_CFG_SPACE = 0xFF;
  33.         public static readonly WDC_REG[] gPLX_CfgRegs = new WDC_REG[]
  34.         {
  35.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_VID, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "VID", "Vendor ID" ),
  36.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_DID, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "DID", "Device ID" ),
  37.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_CR, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "CMD", "Command" ),
  38.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_SR, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "STS", "Status" ),
  39.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_REV, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "RID_CLCD", "Revision ID & Class Code" ),
  40.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_CCSC, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "SCC", "Sub Class Code" ),
  41.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_CCBC, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "BCC", "Base Class Code" ),
  42.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_CLSR, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "CALN", "Cache Line Size" ),
  43.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_LTR, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "LAT", "Latency Timer" ),
  44.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_HDR, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "HDR", "Header Type" ),
  45.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_BISTR, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "BIST", "Built-in Self Test" ),
  46.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_BAR0, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "BADDR0", "Base Address 0" ),
  47.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_BAR1, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "BADDR1", "Base Address 1" ),
  48.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_BAR2, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "BADDR2", "Base Address 2" ),/* Mark end of chain */
  49.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_BAR3, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "BADDR3", "Base Address 3" ),
  50.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_BAR4, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "BADDR4", "Base Address 4" ),
  51.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_BAR5, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "BADDR5", "Base Address 5" ),
  52.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_CIS, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "CIS", "CardBus CIS pointer" ),
  53.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_SVID, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "SVID", "Sub-system Vendor ID" ),
  54.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_SDID, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "SDID", "Sub-system Device ID" ),
  55.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_EROM, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "EROM", "Expansion ROM Base Address" ),
  56.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_CAP, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "NEW_CAP", "New Capabilities Pointer" ),
  57.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_ILR, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "INTLN", "Interrupt Line" ),
  58.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_IPR, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "INTPIN", "Interrupt Pin" ),
  59.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_MGR, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MINGNT", "Minimum Required Burst Period" ),
  60.             new WDC_REG(WDC_AD_CFG_SPACE, (DWORD)PCI_CFG_REG.PCI_MLR, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MAXLAT", "Maximum Latency" ),
  61.             /* PLX-specific configuration registers */
  62.             new WDC_REG(WDC_AD_CFG_SPACE, 0x40, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "PMCAPID", "Power Management Capability ID" ),
  63.             new WDC_REG(WDC_AD_CFG_SPACE, 0x41, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "PMNEXT", "Power Management Next Capability Pointer" ),
  64.             new WDC_REG(WDC_AD_CFG_SPACE, 0x42, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "PMCAP", "Power Management Capabilities" ),
  65.             new WDC_REG(WDC_AD_CFG_SPACE, 0x44, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "PMCSR", "Power Management Control/Status" ),
  66.             new WDC_REG(WDC_AD_CFG_SPACE, 0x48, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "HS_CAPID", "Hot Swap Capability ID" ),
  67.             new WDC_REG(WDC_AD_CFG_SPACE, 0x49, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "HS_NEXT", "Hot Swap Next Capability Pointer" ),
  68.             new WDC_REG(WDC_AD_CFG_SPACE, 0x4A, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "HS_CSR", "Hot Swap Control/Status" ),
  69.             new WDC_REG(WDC_AD_CFG_SPACE, 0x4C, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "VPD_CAPID", "PCI Vital Product Data Control" ),
  70.             new WDC_REG(WDC_AD_CFG_SPACE, 0x4D, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "VPD_NEXT", "PCI Vital Product Next Capability Pointer" ),
  71.             new WDC_REG(WDC_AD_CFG_SPACE, 0x4E, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "VPD_ADDR", "PCI Vital Product Data Address" ),
  72.             new WDC_REG(WDC_AD_CFG_SPACE, 0x50, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "VPD_DATA", "PCI VPD Data" ),
  73.         };
  75.         /* PLX run-time registers information array */
  76.         public static readonly WDC_REG[] gPLX_M_Regs = 
  77.         {
  78.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x00, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS0RR", "Local Addr Space 0 Range for PCI-to-Local Bus" ),
  79.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x04, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS0BA", "Local BAR (Remap) for PCI-to-Local Addr Space 0" ),
  80.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x08, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MARBR", "Mode/DMA Arbitration" ),
  81.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x0C, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "BIGEND", "Big/Little Endian Descriptor" ),
  82.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x0D, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "LMISC", "Local Miscellananeous Control" ),
  83.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x0E, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "PROT_AREA", "Serial EEPROM Write-Protected Addr Boundary" ),
  84.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x10, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "EROMRR", "Expansion ROM Range" ),
  85.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x14, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "EROMBA", "EROM Local BAR (Remap) & BREQ0 Control" ),
  86.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x18, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LBRD0", "Local Addr Space 0 Bus Region Descriptor" ),
  87.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x1C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMRR", "Local Range for PCI initiatior-to-PCI" ),
  88.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x20, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMLBAM", "Local Bus Addr for PCI Initiatior-to-PCI Mem" ),
  89.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x24, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMLBAI", "Local BAR for PCI Initiatior-to-PCI I/O" ),
  90.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x28, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMPBAM", "PCI BAR (Remap) for Initiatior-to-PCI Mem" ),
  91.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x2C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMCFGA", "PCI Config Addr for PCI Initiatior-to-PCI I/O" ),
  92.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x30, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "OPQIS", "Outbound Post Queue Interrupt Status" ),
  93.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x34, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "OPQIM", "Outbound Post Queue Interrupt Mask" ),
  94.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x40, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "IQP", "Inbound Queue Post" ),
  95.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x44, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "OQP", "Outbound Queue Post" ),
  96.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x40, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MBOX0_NO_I2O", "Mailbox 0 (I2O disabled)" ),
  97.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x44, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MBOX1_NO_I2O", "Mailbox 1 (I2O disabled)" ),
  98.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x78, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MBOXO", "Mailbox 0" ),
  99.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x7C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MBOX1", "Mailbox 1" ),
  100.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x48, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MBOX2", "Mailbox 2" ),
  101.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x4C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MBOX3", "Mailbox 3" ),
  102.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x50, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MBOX4", "Mailbox 4" ),
  103.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x54, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MBOX5", "Mailbox 5" ),
  104.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x58, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MBOX6", "Mailbox 6" ),
  105.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x5C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MBOX7", "Mailbox 7" ),
  106.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x60, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "P2LDBELL", "PCI-to-Local Doorbell" ),
  107.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x64, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "L2PDBELL", "Local-to-PCI Doorbell" ),
  108.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x68, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "INTCSR", "Interrupt Control/Status"  ),
  109.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x6C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "CNTRL", "Serial EEPROM/User I/O/Init Ctr & PCI Cmd Codes" ),
  110.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x70, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "PCIHIDR", "PCI Hardcoded Configuration ID" ),
  111.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x74, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "PCIHREV", "PCI Hardcoded Revision ID" ),
  112.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x80, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMAMODE0", "DMA Channel 0 Mode" ),
  113.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x84, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMAPADR0", "DMA Channel 0 PCI Address" ),
  114.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x88, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMALADR0", "DMA Channel 0 Local Address" ),
  115.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x8C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMASIZ0", "DMA Channel 0 Transfer Size (bytes)" ),
  116.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x90, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMADPR0", "DMA Channel 0 Descriptor Pointer" ),
  117.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x94, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMAMODE1", "DMA Channel 1 Mode" ),
  118.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x98, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMAPADR1", "DMA Channel 1 PCI Address" ),
  119.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x9C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMALADR1", "DMA Channel 1 Local Address" ),
  120.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xA0, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMASIZ1", "DMA Channel 1 Transfer Size (bytes)" ),
  121.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xA4, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMADPR1", "DMA Channel 1 Descriptor Pointer" ),
  122.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xA8, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "DMACSR0", "DMA Channel 0 Command/Status" ),
  123.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xA9, wdc_lib_consts.WDC_SIZE_8, WDC_DIRECTION.WDC_READ_WRITE, "DMACSR1", "DMA Channel 1 Command/Status" ),
  124.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xAC, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMAARB", "DMA Arbitration" ),
  125.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xB0, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMATHR", "DMA Threshold (Channel 0 only)" ),
  126.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xB4, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMADAC0", "DMA 0 PCI Dual Address Cycle Address" ),
  127.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xB8, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMADAC1", "DMA 1 PCI Dual Address Cycle Address" ),
  128.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xC0, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "MQCR", "Messaging Queue Configuration" ),
  129.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xC4, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "QBAR", "Queue Base Address" ),
  130.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xC8, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "IFHPR", "Inbound Free Head Pointer" ),
  131.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xCC, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "IFTPR", "Inbound Free Tail Pointer" ),
  132.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xD0, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "IPHPR", "Inbound Post Head Pointer" ),
  133.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xD4, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "IPTPR", "Inbound Post Tail Pointer" ),
  134.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xD8, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "OFHPR", "Outbound Free Head Pointer" ),
  135.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xDC, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "OFTPR", "Outbound Free Tail Pointer" ),
  136.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xE0, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "OPHPR", "Outbound Post Head Pointer" ),
  137.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xE4, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "OPTPR", "Outbound Post Tail Pointer" ),
  138.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xE8, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "QSR", "Queue Status/Control" ),
  139.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xF0, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS1RR", "Local Addr Space 1 Range for PCI-to-Local Bus" ),
  140.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xF4, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS1BA", "Local Addr Space 1 Local BAR (Remap)" ),
  141.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xF8, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LBRD1", "Local Addr Space 1 Bus Region Descriptor" ),
  142.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0xFC, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "DMDAC", "PCI Initiatior PCI Dual Address Cycle" ),
  143.         };
  145.         public static readonly WDC_REG[] gPLX_T_Regs = 
  146.         {
  147.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x00, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS0RR", "Local Addr Space 0 Range" ),
  148.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x04, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS1RR", "Local Addr Space 1 Range" ),
  149.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x08, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS2RR", "Local Addr Space 2 Range" ),
  150.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x0C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS3RR", "Local Addr Space 3 Range" ),
  151.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x10, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "EROMRR", "Expansion ROM Range" ),
  152.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x14, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS0BA", "Local Addr Space 0 Local BAR (Remap)" ),
  153.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x18, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS1BA", "Local Addr Space 1 Local BAR (Remap)" ),
  154.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x1C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS2BA", "Local Addr Space 2 Local BAR (Remap)" ),
  155.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x20, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS3BA", "Local Addr Space 3 Local BAR (Remap)" ),
  156.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x24, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "EROMBA", "Expansion ROM Local BAR (Remap)" ),
  157.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x28, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS0BRD", "Local Addr Space 0 Bus Region Descriptors" ),
  158.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x2C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS1BRD", "Local Addr Space 1 Bus Region Descriptors" ),
  159.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x30, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS2BRD", "Local Addr Space 2 Bus Region Descriptors" ),
  160.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x34, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "LAS3BRD", "Local Addr Space 3 Bus Region Descriptors" ),
  161.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x38, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "EROMBRD", "Expansion ROM Bus Region Descriptors" ),
  162.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x3C, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "CS0BASE", "Chip Select 0 Base Address" ),
  163.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x40, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "CS1BASE", "Chip Select 1 Base Address" ),
  164.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x44, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "CS2BASE", "Chip Select 2 Base Address" ),
  165.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x48, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "CS3BASE", "Chip Select 3 Base Address" ),
  166.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x4C, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "INTCSR", "Interrupt Control/Status" ),
  167.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x4E, wdc_lib_consts.WDC_SIZE_16, WDC_DIRECTION.WDC_READ_WRITE, "PROT_AREA", "Serial EEPROM Write-Protected Addr Boundary" ),
  168.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x50, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "CNTRL", "PCI Target Response; Serial EEPROM; Init Ctr" ),
  169.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x54, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "GPIOC", "General Purpose I/O Control" ),
  170.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x70, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "PMDATASEL", "Hidden 1 Power Management Data Select" ),
  171.             new WDC_REG((DWORD)PLX_ADDR.PLX_ADDR_REG, 0x74, wdc_lib_consts.WDC_SIZE_32, WDC_DIRECTION.WDC_READ_WRITE, "PMDATASCALE", "Hidden 2 Power Management Data Scale" ),
  172.         };
  173.     };
  174. }