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Test_OV9650.h
资源名称：inc.rar　[点击查看]
上传用户：dzdeming
上传日期：2022-08-03
资源大小：381k
文件大小：8k
源码类别：

Windows CE

开发平台：

Visual C++

Test_OV9650.h：源码内容
  1. #ifndef _SMDK2440_OV7620_H_
  2. #define _SMDK2440_OV7620_H_
  4. #define CHIP_DELAY 0xFF
  6. #define BUSHI_DEF 0
  8. static struct ov7620_t {
  9. int subaddr;
  10. int value;
  11. } ov7620_reg[] = {
  12. {0x12, 0x80}, // Camera Soft reset. Self cleared after reset.
  13. {CHIP_DELAY, 10},
  14. {0x00, 0x00}, // 
  15. {0x01, 0x80}, // set blue gain
  16. {0x02, 0x80}, // set red gain
  17. #ifdef BUSHI_DEF
  18. {0x03, 0x80}, // saturation control
  19. #else
  20. {0x03, 0xb0}, // saturation control
  21. #endif
  22. // {0x06, 0x60}, // set brightness - CJH
  23. {0x06, 0x80}, // set brightness - SW.LEE
  24. // {0x0c, 0x24}, // set white balance blue background
  25. {0x0c, 0x20}, // set white balance blue background - SW.LEE
  26. // {0x0d, 0x24}, // set white balance red background
  27. {0x0d, 0x20}, // set white balance red background  - SW.LEE
  28. {0x10, 0xff}, // set auto exposure time, brightness control - CJH
  29. {0x11, (1<<7)+(0<<6)+(0x0)}, // HSYNC positive, CHSYNC negative, VSYNC posigive, 16 Bit : PCLK = CLK_in/((1+x)*2), 8 Bit : PCLK = CLK_in/(1+x)
  30. {0x12, 0x34}, // mirror image, enable AGC/AWB, precise A/D black level compensation
  31. {0x13, (0x1<<5)+(0x0<<4)+(0x1)},  // 8bit Data, CCIR601 Format
  32. {0x15, 0x01}, // Use PCLK rising edge to latch data, UV data output: 16 Bit - UVUV..., 8 Bit - UYVY...
  33. {0x16, 0x03}, // Field mode : 00-OFF mode, 01-ODD mode, 10-EVEN mode, 11-FRAME mode 
  34. {0x17, 0x2f}, //47
  35. {0x18, 0xcf}, // (207-47)*4=640
  36. {0x19, 0x06}, // 6
  37. {0x1a, 0xf5}, // (245-6+1)*2=480
  38. {0x1b, 0x00}, // Pixel Shift
  39. {0x20, 0x00}, // limit vertical size to 480, second stage aperture correction enable
  40. {0x21, 0x80}, // Y Channel Offset Adjustment - 0 , direction - Subtract
  41. {0x22, 0x80}, // U Channel Offset Adjustment - 0
  42. {0x23, 0x00}, // Crystal Current control : maximum current
  43. #ifdef BUSHI_DEF
  44. {0x24, 0x10}, // white pixel ratio,
  45. {0x25, 0x8a}, // black pixel ratio,
  46. #endif
  47. {0x26, 0xa2}, // Digital sharpness threshold, magnitude.
  48. #ifndef BUSHI_DEF
  49. {0x27, 0xea}, // Disable CCIR rang clip
  50. #else
  51. {0x27, 0xe2}, // Disable CCIR rang clip
  52. #endif
  53. {0x29, 0x00}, // 
  54. {0x2a, 0x00}, // frame rate high, 60Hz, 50Hz:0x80, UV delay 2 pixel. - CJH
  55. {0x2b, 0x00}, // frame rate low, 60Hz, 50Hz:0xac
  56. {0x2c, 0x88}, // 
  57. #ifdef BUSHI_DEF
  58. {0x2d, 0x91}, // 
  59. #endif
  60. {0x2e, 0x80}, // 
  61. #ifndef BUSHI_DEF
  62. {0x2f, 0x44}, // 
  63. #endif
  64. {0x60, 0x27}, // 
  65. {0x61, 0x82}, // 02?x.........................................
  66. #ifndef BUSHI_DEF
  67. {0x62, 0x5f}, // 
  68. #else
  69. {0x62, 0x5e}, // 
  70. #endif
  71. #ifndef BUSHI_DEF
  72. {0x63, 0xd5}, // 
  73. #endif
  74. {0x64, 0x57}, // Enable Y Gamma
  75. #ifndef BUSHI_DEF
  76. {0x65, 0x83}, // 
  77. #else
  78. {0x65, 0x43}, // 
  79. #endif
  80. {0x66, 0x55}, // 
  81. #ifdef BUSHI_DEF
  82. {0x67, 0x9a}, // 
  83. #endif
  84. #ifndef BUSHI_DEF
  85. {0x68, 0xcf}, // 
  86. #else
  87. {0x68, 0xcc}, // 
  88. #endif
  89. {0x69, 0x76}, // 
  90. {0x6a, 0x22}, // 
  91. #ifndef BUSHI_DEF
  92. {0x6b, 0x00}, // 
  93. {0x6c, 0x08}, // 
  94. {0x6d, 0x48}, // 
  95. {0x6e, 0x80}, // 
  96. #endif
  97. #ifndef BUSHI_DEF
  98. {0x6f, 0x0c}, // -CJH
  99. #else
  100. {0x6f, 0x3c}, // -CJH
  101. #endif
  102. {0x70, 0x89}, // -CJH
  103. {0x71, 0x00}, //  freerun PCLK
  104. {0x72, 0x14}, // 
  105. {0x73, 0x54}, // 
  106. {0x75, 0x0e}, // -CJH
  107. {0x76, 0x00}, // 
  108. #ifndef BUSHI_DEF
  109. {0x77, 0xff}, // 
  110. {0x78, 0x80}, // 
  111. {0x79, 0x80}, // 
  112. {0x7a, 0x80}, // 
  113. {0x7b, 0xe6}, // -CJH
  114. #endif
  115. {0x7c, 0x00}, // 
  116. #ifndef BUSHI_DEF
  117. {0x14, 0x94}, // turn off GAMMA - CJH
  118. #else
  119. {0x14, 0x14}, // turn off GAMMA - CJH
  120. #endif
  121. {0x24, 0x10}, // -CJH
  122. {0x25, 0x8a}, // -CJH
  123. {0x28, 0x20}, // Progressive mode.
  124. {0x2d, 0x95}, //
  125. {0x67, 0x92}, // 
  126. {0x74, 0x00}, // -CJH
  127. };
  129. #define OV7620_REGS (sizeof(ov7620_reg)/sizeof(ov7620_reg[0]))
  131. static struct ov7620_t ov9650_reg[] = 
  132. {
  133. {0x12, 0x80}, // Camera Soft reset. Self cleared after reset.
  134. {CHIP_DELAY, 10},
  135. /* {0x00, 0x00}, // 
  136. {0x01, 0x80}, // set blue gain
  137. {0x02, 0x80}, // set red gain
  138. {0x03, 0x00}, // saturation control ???
  139. //--- hzh
  140. //{0x04, 0x43}, // CCIR656 format, AEC low 2 LSB = 3
  141. {0x04, 0x03}, // CCIR601 format, AEC low 2 LSB = 3
  142. // {0x09, 0x03}, // output drive = 4x, default is 2x
  143. {0x10, 0xff}, // AEC[9:2] = 0xff
  144. {0x11, 0x40}, // PCLK use input clock directly
  145. //{0x11, 0x00}, // PCLK = input clock/2
  146. {0x12, 0x40}, // VGA
  147. {0x17, 0x10}, // hstart, 128, 128>>3 = 16
  148. {0x18, 0x60}, // hstop, 768, 768>>3 = 96
  149. {0x19, 0x20}, // vstart, 256, 256/8 = 32
  150. {0x1a, 0x5c}, // vstop, , 736/8 = 92
  151. //{0x1a, 0x3e}, // vstop, , 736/8 = 92
  152. {0x32, 0x00},
  153. // {0x0c, 0x40},
  154. // {0x3a, 0x18},
  155. // {0x67, 0x00},
  156. // {0x68, 0xff},
  157. // {0x40, 0xd0},
  158. {0x15, 0x10}, // PCLK reverse
  159. //---
  160. */
  161. #if 0
  162. //{0x12, 0x80}, 
  163. {0x39, 0x43}, {0x38, 0x12}, {0x37, 0x00}, {0x0e, 0x20},
  164. {0x1e, 0x0c}, {0x01, 0x80}, {0x02, 0x80}, {0x00, 0x00}, {0x10, 0xf0},
  165. {0x04, 0x00}, {0x0c, 0x00}, {0x0d, 0x00}, {0x11, 0x80}, {0x12, 0x00},
  166. {0x14, 0x2e}, {0x15, 0x00}, {0x18, 0x60}, {0x17, 0x10}, {0x32, 0xbf}, 
  167. {0x03, 0x12}, {0x1a, 0x5c}, {0x19, 0x20}, {0x3f, 0xa6}, {0x41, 0x02},
  168. {0x42, 0x08}, {0x1b, 0x00}, {0x16, 0x06}, {0x33, 0xc0}, {0x34, 0xbf},
  169. //{0xa8, 0x80}, //???
  170. {0x96, 0x04}, 
  171. {0x3a, 0x00}, 
  172. {0x8e, 0x00}, 
  173. {0x3c, 0x77}, 
  174. {0x8b, 0x06}, {0x35, 0x91}, {0x94, 0x88}, {0x95, 0x88}, {0x40, 0xc1}, 
  175. {0x29, 0x3f}, {0x0f, 0x42}, {0x13, 0xe5}, {0x3d, 0x92}, {0x69, 0x80}, 
  176. {0x5c, 0x96}, {0x5d, 0x96}, {0x5e, 0x10}, {0x59, 0xeb}, {0x5a, 0x9c},
  177. {0x5b, 0x55}, {0x43, 0xf0}, {0x44, 0x10}, {0x45, 0x55}, {0x46, 0x86},
  178. {0x47, 0x64}, {0x48, 0x86}, {0x5f, 0xe0}, {0x60, 0x8c}, {0x61, 0x20},
  179. {0xa5, 0xd9}, {0xa4, 0x74}, {0x8d, 0x02}, {0x13, 0xe7}, {0x4f, 0x3a}, 
  180. {0x50, 0x3d}, {0x51, 0x03}, {0x52, 0x12}, {0x53, 0x26}, {0x54, 0x38},
  181. {0x55, 0x40}, {0x56, 0x40}, {0x57, 0x40}, {0x58, 0x0d}, {0x8c, 0x23},
  182. {0x3e, 0x02}, {0xa9, 0xb8}, {0xaa, 0x92}, {0xab, 0x0a}, {0x8f, 0xdf},
  183. {0x90, 0x00}, {0x91, 0x00}, {0x9f, 0x00}, {0x3a, 0x0c}, {0x24, 0x70},
  184. {0x25, 0x64}, {0x26, 0xc3}, {0x2a, 0x12}, {0x2b, 0x46}, {0x3b, 0x19},
  185. {0x6c, 0x40}, {0x6d, 0x30}, {0x6e, 0x4b}, {0x6f, 0x60},  
  186. {0x70, 0x70}, {0x71, 0x70}, {0x72, 0x70}, {0x73, 0x70},
  187. {0x74, 0x60}, {0x75, 0x60}, {0x76, 0x50}, {0x77, 0x48},
  188. {0x78, 0x3a}, {0x79, 0x2e}, {0x7a, 0x28}, {0x7b, 0x22},
  189. {0x7c, 0x04}, {0x7d, 0x07}, {0x7e, 0x10}, {0x7f, 0x28},
  190. {0x80, 0x36}, {0x81, 0x44}, {0x82, 0x52}, {0x83, 0x60},
  191. {0x84, 0x6c}, {0x85, 0x78}, {0x86, 0x8c}, {0x87, 0x9e},
  192. {0x88, 0xbb}, {0x89, 0xd2}, {0x8a, 0xe6},
  193. {0x6a, 0x41}, {0x66, 0x00},
  194. {0x3e, 0x00}, {0x3f, 0xa4},
  196. {0x3a, 0x00}, //UYVY is suitable!
  197. {0x67, 0x55},  //0x67->U(RGB 1st lower),
  198. {0x68, 0xaa}, //0x68->V(RGB 2nd lower),
  199. //{0x0c, 0x40}, //MSB and LSB swap
  200. //{0x12, 0x40}, //VGA
  201.         {0x12, 0x44}, //VGA and RGB format
  202. {0x40, 0xd1}, //RGB565
  203. {0x11, 0x80}, //set PCLK as high as input clock
  204. //{0x11, 0x00}, //set PCLK as high as half of input clock
  205. {0x15, 0x10}, //PCLK reverse
  206. //{0x8d, 0x12},
  207. #else
  208. //change 0x11[0x81->0x80], 0x15[0x02->0x10], hzh
  209. //{0x12,0x80},
  210. {0x11,0x80},{0x6a,0x3e},{0x3b,0x09},{0x13,0xe0},{0x01,0x80},{0x02,0x80},{0x00,0x00},{0x10,0x00},
  211. {0x13,0xe5},{0x39,0x43},{0x38,0x12},{0x37,0x00},{0x35,0x91},{0x0e,0xa0},{0x1e,0x04},{0xA8,0x80},
  212. {0x12,0x40},{0x04,0x00},{0x0c,0x04},{0x0d,0x80},{0x18,0xc6},{0x17,0x26},{0x32,0xad},{0x03,0x00},
  213. {0x1a,0x3d},{0x19,0x01},{0x3f,0xa6},{0x14,0x2e},{0x15,0x10},{0x41,0x02},{0x42,0x08},{0x1b,0x00},
  214. {0x16,0x06},{0x33,0xe2},{0x34,0xbf},{0x96,0x04},{0x3a,0x00},{0x8e,0x00},{0x3c,0x77},{0x8B,0x06},
  215. {0x94,0x88},{0x95,0x88},{0x40,0xc1},{0x29,0x3f},{0x0f,0x42},{0x3d,0x92},{0x69,0x40},{0x5C,0xb9},
  216. {0x5D,0x96},{0x5E,0x10},{0x59,0xc0},{0x5A,0xaf},{0x5B,0x55},{0x43,0xf0},{0x44,0x10},{0x45,0x68},
  217. {0x46,0x96},{0x47,0x60},{0x48,0x80},{0x5F,0xe0},{0x60,0x8c},{0x61,0x20},{0xa5,0xd9},{0xa4,0x74},
  218. {0x8d,0x02},{0x13,0xe7},{0x4f,0x3a},{0x50,0x3d},{0x51,0x03},{0x52,0x12},{0x53,0x26},{0x54,0x38},
  219. {0x55,0x40},{0x56,0x40},{0x57,0x40},{0x58,0x0d},{0x8C,0x23},{0x3E,0x02},{0xa9,0xb8},{0xaa,0x92},
  220. {0xab,0x0a},{0x8f,0xdf},{0x90,0x00},{0x91,0x00},{0x9f,0x00},{0xa0,0x00},{0x3A,0x01},{0x24,0x70},
  221. {0x25,0x64},{0x26,0xc3},{0x2a,0x00},{0x2b,0x00},{0x6c,0x40},{0x6d,0x30},{0x6e,0x4b},{0x6f,0x60},
  222. {0x70,0x70},{0x71,0x70},{0x72,0x70},{0x73,0x70},{0x74,0x60},{0x75,0x60},{0x76,0x50},{0x77,0x48},
  223. {0x78,0x3a},{0x79,0x2e},{0x7a,0x28},{0x7b,0x22},{0x7c,0x04},{0x7d,0x07},{0x7e,0x10},{0x7f,0x28},
  224. {0x80,0x36},{0x81,0x44},{0x82,0x52},{0x83,0x60},{0x84,0x6c},{0x85,0x78},{0x86,0x8c},{0x87,0x9e},
  225. {0x88,0xbb},{0x89,0xd2},{0x8a,0xe6},
  226. //{0x15, 0x12}, // PCLK reverse
  227. #endif
  228. };
  230. #define OV9650_REGS (sizeof(ov9650_reg)/sizeof(ov9650_reg[0]))
  233. #endif /* _SMDK2440_OV7620_H_ */