mul_1.asm
上传用户:qaz666999
上传日期:2022-08-06
资源大小:2570k
文件大小:7k
源码类别:

数学计算

开发平台:

Unix_Linux

  1. dnl  Alpha ev6 nails mpn_mul_1.
  2. dnl  Copyright 2002, 2005, 2006 Free Software Foundation, Inc.
  3. dnl
  4. dnl  This file is part of the GNU MP Library.
  5. dnl
  6. dnl  The GNU MP Library is free software; you can redistribute it and/or
  7. dnl  modify it under the terms of the GNU Lesser General Public License as
  8. dnl  published by the Free Software Foundation; either version 3 of the
  9. dnl  License, or (at your option) any later version.
  10. dnl
  11. dnl  The GNU MP Library is distributed in the hope that it will be useful,
  12. dnl  but WITHOUT ANY WARRANTY; without even the implied warranty of
  13. dnl  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the GNU
  14. dnl  Lesser General Public License for more details.
  15. dnl
  16. dnl  You should have received a copy of the GNU Lesser General Public License
  17. dnl  along with the GNU MP Library.  If not, see http://www.gnu.org/licenses/.
  18. include(`../config.m4')
  19. C      cycles/limb
  20. C EV4:    42
  21. C EV5:    18
  22. C EV6:     3.25
  23. C TODO
  24. C  * Reroll loop for 3.0 c/l with current 4-way unrolling.
  25. C  * The loop is overscheduled wrt loads and wrt multiplies, in particular
  26. C    umulh.
  27. C  * Use FP loop count and multiple exit points, that would simplify feed-in lp0
  28. C    and would work since the loop structure is really regular.
  29. C  INPUT PARAMETERS
  30. define(`rp',`r16')
  31. define(`up',`r17')
  32. define(`n', `r18')
  33. define(`vl0',`r19')
  34. define(`numb_mask',`r6')
  35. define(`m0a',`r0')
  36. define(`m0b',`r1')
  37. define(`m1a',`r2')
  38. define(`m1b',`r3')
  39. define(`m2a',`r20')
  40. define(`m2b',`r21')
  41. define(`m3a',`r22')
  42. define(`m3b',`r23')
  43. define(`acc0',`r25')
  44. define(`acc1',`r27')
  45. define(`ul0',`r4')
  46. define(`ul1',`r5')
  47. define(`ul2',`r4')
  48. define(`ul3',`r5')
  49. define(`rl0',`r24')
  50. define(`rl1',`r24')
  51. define(`rl2',`r24')
  52. define(`rl3',`r24')
  53. define(`t0',`r7')
  54. define(`t1',`r8')
  55. define(`NAIL_BITS',`GMP_NAIL_BITS')
  56. define(`NUMB_BITS',`GMP_NUMB_BITS')
  57. dnl  This declaration is munged by configure
  58. NAILS_SUPPORT(1-63)
  59. ASM_START()
  60. PROLOGUE(mpn_mul_1)
  61. sll vl0, NAIL_BITS, vl0
  62. lda numb_mask, -1(r31)
  63. srl numb_mask, NAIL_BITS, numb_mask
  64. and n, 3, r25
  65. cmpeq r25, 1, r21
  66. bne r21, L(1m4)
  67. cmpeq r25, 2, r21
  68. bne r21, L(2m4)
  69. beq r25, L(0m4)
  70. L(3m4): ldq ul3, 0(up)
  71. lda n, -4(n)
  72. ldq ul0, 8(up)
  73. mulq vl0, ul3, m3a
  74. umulh vl0, ul3, m3b
  75. ldq ul1, 16(up)
  76. lda up, 24(up)
  77. lda rp, -8(rp)
  78. mulq vl0, ul0, m0a
  79. umulh vl0, ul0, m0b
  80. bge n, L(ge3)
  81. mulq vl0, ul1, m1a
  82. umulh vl0, ul1, m1b
  83. srl m3a,NAIL_BITS, t0
  84. addq t0, r31, acc1
  85. srl m0a,NAIL_BITS, t0
  86. addq t0, m3b, acc0
  87. srl acc1,NUMB_BITS, t1
  88. br r31, L(ta3)
  89. L(ge3): ldq ul2, 0(up)
  90. mulq vl0, ul1, m1a
  91. umulh vl0, ul1, m1b
  92. srl m3a,NAIL_BITS, t0
  93. ldq ul3, 8(up)
  94. lda n, -4(n)
  95. mulq vl0, ul2, m2a
  96. addq t0, r31, acc1
  97. umulh vl0, ul2, m2b
  98. srl m0a,NAIL_BITS, t0
  99. ldq ul0, 16(up)
  100. mulq vl0, ul3, m3a
  101. addq t0, m3b, acc0
  102. srl acc1,NUMB_BITS, t1
  103. br r31, L(el3)
  104. L(0m4): lda n, -8(n)
  105. ldq ul2, 0(up)
  106. ldq ul3, 8(up)
  107. mulq vl0, ul2, m2a
  108. umulh vl0, ul2, m2b
  109. ldq ul0, 16(up)
  110. mulq vl0, ul3, m3a
  111. umulh vl0, ul3, m3b
  112. ldq ul1, 24(up)
  113. lda up, 32(up)
  114. mulq vl0, ul0, m0a
  115. umulh vl0, ul0, m0b
  116. bge n, L(ge4)
  117. srl m2a,NAIL_BITS, t0
  118. mulq vl0, ul1, m1a
  119. addq t0, r31, acc0
  120. umulh vl0, ul1, m1b
  121. srl m3a,NAIL_BITS, t0
  122. addq t0, m2b, acc1
  123. srl acc0,NUMB_BITS, t1
  124. br r31, L(ta4)
  125. L(ge4): srl m2a,NAIL_BITS, t0
  126. ldq ul2, 0(up)
  127. mulq vl0, ul1, m1a
  128. addq t0, r31, acc0
  129. umulh vl0, ul1, m1b
  130. srl m3a,NAIL_BITS, t0
  131. ldq ul3, 8(up)
  132. lda n, -4(n)
  133. mulq vl0, ul2, m2a
  134. addq t0, m2b, acc1
  135. srl acc0,NUMB_BITS, t1
  136. br r31, L(el0)
  137. L(2m4): lda n, -4(n)
  138. ldq ul0, 0(up)
  139. ldq ul1, 8(up)
  140. lda up, 16(up)
  141. lda rp, -16(rp)
  142. mulq vl0, ul0, m0a
  143. umulh vl0, ul0, m0b
  144. bge n, L(ge2)
  145. mulq vl0, ul1, m1a
  146. umulh vl0, ul1, m1b
  147. srl m0a,NAIL_BITS, t0
  148. addq t0, r31, acc0
  149. srl m1a,NAIL_BITS, t0
  150. addq t0, m0b, acc1
  151. srl acc0,NUMB_BITS, t1
  152. br r31, L(ta2)
  153. L(ge2): ldq ul2, 0(up)
  154. mulq vl0, ul1, m1a
  155. umulh vl0, ul1, m1b
  156. ldq ul3, 8(up)
  157. lda n, -4(n)
  158. mulq vl0, ul2, m2a
  159. umulh vl0, ul2, m2b
  160. srl m0a,NAIL_BITS, t0
  161. ldq ul0, 16(up)
  162. mulq vl0, ul3, m3a
  163. addq t0, r31, acc0
  164. umulh vl0, ul3, m3b
  165. srl m1a,NAIL_BITS, t0
  166. ldq ul1, 24(up)
  167. lda up, 32(up)
  168. lda rp, 32(rp)
  169. mulq vl0, ul0, m0a
  170. addq t0, m0b, acc1
  171. srl acc0,NUMB_BITS, t1
  172. bge n, L(el2)
  173. br r31, L(ta6)
  174. L(1m4): lda n, -4(n)
  175. ldq ul1, 0(up)
  176. lda up, 8(up)
  177. lda rp, -24(rp)
  178. bge n, L(ge1)
  179. mulq vl0, ul1, m1a
  180. umulh vl0, ul1, m1b
  181. srl m1a,NAIL_BITS, t0
  182. addq t0, r31, acc1
  183. and acc1,numb_mask, r28
  184. srl acc1,NUMB_BITS, t1
  185. stq r28, 24(rp)
  186. addq t1, m1b, r0
  187. ret r31, (r26), 1
  188. L(ge1): ldq ul2, 0(up)
  189. mulq vl0, ul1, m1a
  190. umulh vl0, ul1, m1b
  191. ldq ul3, 8(up)
  192. lda n, -4(n)
  193. mulq vl0, ul2, m2a
  194. umulh vl0, ul2, m2b
  195. ldq ul0, 16(up)
  196. mulq vl0, ul3, m3a
  197. umulh vl0, ul3, m3b
  198. srl m1a,NAIL_BITS, t0
  199. ldq ul1, 24(up)
  200. lda up, 32(up)
  201. lda rp, 32(rp)
  202. mulq vl0, ul0, m0a
  203. addq t0, r31, acc1
  204. umulh vl0, ul0, m0b
  205. srl m2a,NAIL_BITS, t0
  206. mulq vl0, ul1, m1a
  207. addq t0, m1b, acc0
  208. srl acc1,NUMB_BITS, t1
  209. blt n, L(ta5)
  210. L(ge5): ldq ul2, 0(up)
  211. br r31, L(el1)
  212. ALIGN(16)
  213. L(top): mulq vl0, ul0, m0a C U1
  214. addq t0, m0b, acc1 C L0
  215. srl acc0,NUMB_BITS, t1 C U0
  216. stq r28, -24(rp) C L1
  217. C
  218. L(el2): umulh vl0, ul0, m0b C U1
  219. and acc0,numb_mask, r28 C L0
  220. unop C U0
  221. unop C L1
  222. C
  223. unop C U1
  224. addq t1, acc1, acc1 C L0
  225. srl m2a,NAIL_BITS, t0 C U0
  226. ldq ul2, 0(up) C L1
  227. C
  228. mulq vl0, ul1, m1a C U1
  229. addq t0, m1b, acc0 C L0
  230. srl acc1,NUMB_BITS, t1 C U0
  231. stq r28, -16(rp) C L1
  232. C
  233. L(el1): umulh vl0, ul1, m1b C U1
  234. and acc1,numb_mask, r28 C L0
  235. unop C U0
  236. lda n, -4(n) C L1
  237. C
  238. unop C U1
  239. addq t1, acc0, acc0 C L0
  240. srl m3a,NAIL_BITS, t0 C U0
  241. ldq ul3, 8(up) C L1
  242. C
  243. mulq vl0, ul2, m2a C U1
  244. addq t0, m2b, acc1 C L0
  245. srl acc0,NUMB_BITS, t1 C U0
  246. stq r28, -8(rp) C L1
  247. C
  248. L(el0): umulh vl0, ul2, m2b C U1
  249. and acc0,numb_mask, r28 C L0
  250. unop C U0
  251. unop C L1
  252. C
  253. unop C U1
  254. addq t1, acc1, acc1 C L0
  255. srl m0a,NAIL_BITS, t0 C U0
  256. ldq ul0, 16(up) C L1
  257. C
  258. mulq vl0, ul3, m3a C U1
  259. addq t0, m3b, acc0 C L0
  260. srl acc1,NUMB_BITS, t1 C U0
  261. stq r28, 0(rp) C L1
  262. C
  263. L(el3): umulh vl0, ul3, m3b C U1
  264. and acc1,numb_mask, r28 C L0
  265. unop C U0
  266. unop C L1
  267. C
  268. unop C U1
  269. addq t1, acc0, acc0 C L0
  270. srl m1a,NAIL_BITS, t0 C U0
  271. ldq ul1, 24(up) C L1
  272. C
  273. lda up, 32(up) C L0
  274. unop C U1
  275. lda rp, 32(rp) C L1
  276. bge n, L(top) C U0
  277. L(end): mulq vl0, ul0, m0a
  278. addq t0, m0b, acc1
  279. srl acc0,NUMB_BITS, t1
  280. stq r28, -24(rp)
  281. L(ta6): umulh vl0, ul0, m0b
  282. and acc0,numb_mask, r28
  283. addq t1, acc1, acc1
  284. srl m2a,NAIL_BITS, t0
  285. mulq vl0, ul1, m1a
  286. addq t0, m1b, acc0
  287. srl acc1,NUMB_BITS, t1
  288. stq r28, -16(rp)
  289. L(ta5): umulh vl0, ul1, m1b
  290. and acc1,numb_mask, r28
  291. addq t1, acc0, acc0
  292. srl m3a,NAIL_BITS, t0
  293. addq t0, m2b, acc1
  294. srl acc0,NUMB_BITS, t1
  295. stq r28, -8(rp)
  296. ALIGN(16)
  297. L(ta4): and acc0,numb_mask, r28
  298. addq t1, acc1, acc1
  299. srl m0a,NAIL_BITS, t0
  300. addq t0, m3b, acc0
  301. srl acc1,NUMB_BITS, t1
  302. stq r28, 0(rp)
  303. unop
  304. ALIGN(16)
  305. L(ta3): and acc1,numb_mask, r28
  306. addq t1, acc0, acc0
  307. srl m1a,NAIL_BITS, t0
  308. addq t0, m0b, acc1
  309. srl acc0,NUMB_BITS, t1
  310. stq r28, 8(rp)
  311. unop
  312. ALIGN(16)
  313. L(ta2): and acc0,numb_mask, r28
  314. addq t1, acc1, acc1
  315. srl acc1,NUMB_BITS, t1
  316. stq r28, 16(rp)
  317. and acc1,numb_mask, r28
  318. addq t1, m1b, r0
  319. stq r28, 24(rp)
  320. ret r31, (r26), 1
  321. EPILOGUE()
  322. ASM_END()