DS18B20.tan.summary
资源名称:DS18B20.rar [点击查看]
上传用户:whms_168
上传日期:2022-08-09
资源大小:592k
文件大小:1k
源码类别:
VHDL/FPGA/Verilog
开发平台:
Others
- --------------------------------------------------------------------------------------
- Timing Analyzer Summary
- --------------------------------------------------------------------------------------
- Type : Worst-case tsu
- Slack : N/A
- Required Time : None
- Actual Time : -5.913 ns
- From : DT
- To : DS18B20VHDL:inst4|DATA[7]
- From Clock : --
- To Clock : GCLKP1
- Failed Paths : 0
- Type : Worst-case tco
- Slack : N/A
- Required Time : None
- Actual Time : 26.302 ns
- From : LED4:inst2|Refresh[1]
- To : LEDOUT[4]
- From Clock : GCLKP1
- To Clock : --
- Failed Paths : 0
- Type : Worst-case th
- Slack : N/A
- Required Time : None
- Actual Time : 9.089 ns
- From : DT
- To : DS18B20VHDL:inst4|DATA[6]
- From Clock : --
- To Clock : GCLKP1
- Failed Paths : 0
- Type : Clock Setup: 'GCLKP1'
- Slack : N/A
- Required Time : None
- Actual Time : 59.87 MHz ( period = 16.704 ns )
- From : DS18B20VHDL:inst4|Count[1]
- To : DS18B20VHDL:inst4|DATA[9]
- From Clock : GCLKP1
- To Clock : GCLKP1
- Failed Paths : 0
- Type : Total number of failed paths
- Slack :
- Required Time :
- Actual Time :
- From :
- To :
- From Clock :
- To Clock :
- Failed Paths : 0
- --------------------------------------------------------------------------------------